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1 ;; Scheduling description for IBM RS64 processors.
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2 ;; Copyright (C) 2003-2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5
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6 ;; GCC is free software; you can redistribute it and/or modify it
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7 ;; under the terms of the GNU General Public License as published
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8 ;; by the Free Software Foundation; either version 3, or (at your
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9 ;; option) any later version.
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10
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11 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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12 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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13 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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14 ;; License for more details.
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15
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 (define_automaton "rs64,rs64fp")
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21 (define_cpu_unit "iu_rs64" "rs64")
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22 (define_cpu_unit "mciu_rs64" "rs64")
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23 (define_cpu_unit "fpu_rs64" "rs64fp")
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24 (define_cpu_unit "lsu_rs64,bpu_rs64" "rs64")
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25
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26 ;; RS64a 64-bit IU, LSU, FPU, BPU
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27
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28 (define_insn_reservation "rs64a-load" 2
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111
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29 (and (eq_attr "type" "load")
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30 (eq_attr "cpu" "rs64a"))
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31 "lsu_rs64")
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32
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33 (define_insn_reservation "rs64a-store" 2
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111
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34 (and (eq_attr "type" "store,fpstore")
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35 (eq_attr "cpu" "rs64a"))
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36 "lsu_rs64")
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37
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38 (define_insn_reservation "rs64a-fpload" 3
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111
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39 (and (eq_attr "type" "fpload")
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40 (eq_attr "cpu" "rs64a"))
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41 "lsu_rs64")
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42
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43 (define_insn_reservation "rs64a-llsc" 2
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44 (and (eq_attr "type" "load_l,store_c")
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45 (eq_attr "cpu" "rs64a"))
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46 "lsu_rs64")
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47
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48 (define_insn_reservation "rs64a-integer" 1
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111
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49 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
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50 (and (eq_attr "type" "add,logical,shift,exts")
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51 (eq_attr "dot" "no")))
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52 (eq_attr "cpu" "rs64a"))
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53 "iu_rs64")
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54
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55 (define_insn_reservation "rs64a-two" 1
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56 (and (eq_attr "type" "two")
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57 (eq_attr "cpu" "rs64a"))
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58 "iu_rs64,iu_rs64")
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59
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60 (define_insn_reservation "rs64a-three" 1
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61 (and (eq_attr "type" "three")
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62 (eq_attr "cpu" "rs64a"))
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63 "iu_rs64,iu_rs64,iu_rs64")
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64
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65 (define_insn_reservation "rs64a-imul" 20
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111
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66 (and (eq_attr "type" "mul")
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67 (eq_attr "size" "32")
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68 (eq_attr "cpu" "rs64a"))
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69 "mciu_rs64*13")
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70
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71 (define_insn_reservation "rs64a-imul2" 12
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111
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72 (and (eq_attr "type" "mul")
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73 (eq_attr "size" "16")
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74 (eq_attr "cpu" "rs64a"))
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75 "mciu_rs64*5")
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76
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77 (define_insn_reservation "rs64a-imul3" 8
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111
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78 (and (eq_attr "type" "mul")
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79 (eq_attr "size" "8")
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80 (eq_attr "cpu" "rs64a"))
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81 "mciu_rs64*2")
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82
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83 (define_insn_reservation "rs64a-lmul" 34
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111
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84 (and (eq_attr "type" "mul")
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85 (eq_attr "size" "64")
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86 (eq_attr "cpu" "rs64a"))
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87 "mciu_rs64*34")
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88
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89 (define_insn_reservation "rs64a-idiv" 66
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111
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90 (and (eq_attr "type" "div")
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91 (eq_attr "size" "32")
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92 (eq_attr "cpu" "rs64a"))
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93 "mciu_rs64*66")
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94
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95 (define_insn_reservation "rs64a-ldiv" 66
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111
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96 (and (eq_attr "type" "div")
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97 (eq_attr "size" "64")
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98 (eq_attr "cpu" "rs64a"))
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99 "mciu_rs64*66")
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100
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101 (define_insn_reservation "rs64a-compare" 3
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111
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102 (and (ior (eq_attr "type" "cmp")
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103 (and (eq_attr "type" "add,logical,shift,exts")
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104 (eq_attr "dot" "yes")))
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0
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105 (eq_attr "cpu" "rs64a"))
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106 "iu_rs64,nothing,bpu_rs64")
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107
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108 (define_insn_reservation "rs64a-fpcompare" 5
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109 (and (eq_attr "type" "fpcompare")
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110 (eq_attr "cpu" "rs64a"))
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111 "mciu_rs64,fpu_rs64,bpu_rs64")
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112
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113 (define_insn_reservation "rs64a-fp" 4
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111
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114 (and (eq_attr "type" "fp,fpsimple,dmul")
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115 (eq_attr "cpu" "rs64a"))
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116 "mciu_rs64,fpu_rs64")
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117
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118 (define_insn_reservation "rs64a-sdiv" 31
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119 (and (eq_attr "type" "sdiv,ddiv")
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120 (eq_attr "cpu" "rs64a"))
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121 "mciu_rs64,fpu_rs64*31")
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122
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123 (define_insn_reservation "rs64a-sqrt" 49
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124 (and (eq_attr "type" "ssqrt,dsqrt")
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125 (eq_attr "cpu" "rs64a"))
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126 "mciu_rs64,fpu_rs64*49")
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127
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128 (define_insn_reservation "rs64a-mfcr" 2
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129 (and (eq_attr "type" "mfcr")
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130 (eq_attr "cpu" "rs64a"))
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131 "lsu_rs64")
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132
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133 (define_insn_reservation "rs64a-mtcr" 3
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134 (and (eq_attr "type" "mtcr")
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135 (eq_attr "cpu" "rs64a"))
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136 "lsu_rs64")
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137
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138 (define_insn_reservation "rs64a-mtjmpr" 3
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139 (and (eq_attr "type" "mtjmpr")
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140 (eq_attr "cpu" "rs64a"))
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141 "lsu_rs64")
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142
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143 (define_insn_reservation "rs64a-mfjmpr" 2
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144 (and (eq_attr "type" "mfjmpr")
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145 (eq_attr "cpu" "rs64a"))
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146 "lsu_rs64")
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147
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148 (define_insn_reservation "rs64a-jmpreg" 1
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131
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149 (and (eq_attr "type" "jmpreg,branch,cr_logical")
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150 (eq_attr "cpu" "rs64a"))
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151 "bpu_rs64")
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152
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153 (define_insn_reservation "rs64a-isync" 6
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154 (and (eq_attr "type" "isync")
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155 (eq_attr "cpu" "rs64a"))
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156 "bpu_rs64")
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157
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158 (define_insn_reservation "rs64a-sync" 1
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159 (and (eq_attr "type" "sync")
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160 (eq_attr "cpu" "rs64a"))
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161 "lsu_rs64")
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162
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