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1 ;; Machine description for PowerPC synchronization instructions.
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145
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2 ;; Copyright (C) 2005-2020 Free Software Foundation, Inc.
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3 ;; Contributed by Geoffrey Keating.
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4
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5 ;; This file is part of GCC.
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6
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7 ;; GCC is free software; you can redistribute it and/or modify it
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8 ;; under the terms of the GNU General Public License as published
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9 ;; by the Free Software Foundation; either version 3, or (at your
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10 ;; option) any later version.
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11
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12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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15 ;; License for more details.
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16
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17 ;; You should have received a copy of the GNU General Public License
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18 ;; along with GCC; see the file COPYING3. If not see
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19 ;; <http://www.gnu.org/licenses/>.
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20
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111
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21 (define_mode_attr larx [(QI "lbarx")
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22 (HI "lharx")
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23 (SI "lwarx")
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24 (DI "ldarx")
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25 (TI "lqarx")])
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26
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27 (define_mode_attr stcx [(QI "stbcx.")
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28 (HI "sthcx.")
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29 (SI "stwcx.")
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30 (DI "stdcx.")
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31 (TI "stqcx.")])
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0
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32
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33 (define_code_iterator FETCHOP [plus minus ior xor and])
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34 (define_code_attr fetchop_name
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111
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35 [(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
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0
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36 (define_code_attr fetchop_pred
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111
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37 [(plus "add_operand") (minus "int_reg_operand")
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0
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38 (ior "logical_operand") (xor "logical_operand") (and "and_operand")])
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39
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111
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40 (define_expand "mem_thread_fence"
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131
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41 [(match_operand:SI 0 "const_int_operand")] ;; model
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111
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42 ""
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43 {
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44 enum memmodel model = memmodel_base (INTVAL (operands[0]));
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45 switch (model)
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46 {
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47 case MEMMODEL_RELAXED:
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48 break;
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49 case MEMMODEL_CONSUME:
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50 case MEMMODEL_ACQUIRE:
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51 case MEMMODEL_RELEASE:
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52 case MEMMODEL_ACQ_REL:
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53 emit_insn (gen_lwsync ());
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54 break;
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55 case MEMMODEL_SEQ_CST:
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56 emit_insn (gen_hwsync ());
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57 break;
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58 default:
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59 gcc_unreachable ();
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60 }
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61 DONE;
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62 })
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63
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64 (define_expand "hwsync"
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0
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65 [(set (match_dup 0)
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66 (unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
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67 ""
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68 {
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69 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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70 MEM_VOLATILE_P (operands[0]) = 1;
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71 })
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72
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111
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73 (define_insn "*hwsync"
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0
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74 [(set (match_operand:BLK 0 "" "")
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75 (unspec:BLK [(match_dup 0)] UNSPEC_SYNC))]
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76 ""
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111
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77 "sync"
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0
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78 [(set_attr "type" "sync")])
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79
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111
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80 (define_expand "lwsync"
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81 [(set (match_dup 0)
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82 (unspec:BLK [(match_dup 0)] UNSPEC_LWSYNC))]
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83 ""
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0
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84 {
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111
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85 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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86 MEM_VOLATILE_P (operands[0]) = 1;
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0
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87 })
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88
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111
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89 (define_insn "*lwsync"
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90 [(set (match_operand:BLK 0 "" "")
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91 (unspec:BLK [(match_dup 0)] UNSPEC_LWSYNC))]
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92 ""
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0
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93 {
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111
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94 if (TARGET_NO_LWSYNC)
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95 return "sync";
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131
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96 else
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111
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97 return "lwsync";
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98 }
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99 [(set_attr "type" "sync")])
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100
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101 (define_insn "isync"
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102 [(unspec_volatile:BLK [(const_int 0)] UNSPECV_ISYNC)]
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103 ""
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104 "isync"
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105 [(set_attr "type" "isync")])
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0
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106
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111
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107 ;; Types that we should provide atomic instructions for.
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108 (define_mode_iterator AINT [QI
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109 HI
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110 SI
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111 (DI "TARGET_POWERPC64")
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112 (TI "TARGET_SYNC_TI")])
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113
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114 ;; The control dependency used for load dependency described
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115 ;; in B.2.3 of the Power ISA 2.06B.
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116 (define_insn "loadsync_<mode>"
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117 [(unspec_volatile:BLK [(match_operand:AINT 0 "register_operand" "r")]
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118 UNSPECV_ISYNC)
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119 (clobber (match_scratch:CC 1 "=y"))]
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120 ""
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121 "cmpw %1,%0,%0\;bne- %1,$+4\;isync"
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122 [(set_attr "type" "isync")
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123 (set_attr "length" "12")])
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124
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125 (define_insn "load_quadpti"
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126 [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
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127 (unspec:PTI
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128 [(match_operand:TI 1 "quad_memory_operand" "wQ")] UNSPEC_LSQ))]
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129 "TARGET_SYNC_TI
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130 && !reg_mentioned_p (operands[0], operands[1])"
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131 "lq %0,%1"
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131
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132 [(set_attr "type" "load")])
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0
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133
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111
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134 (define_expand "atomic_load<mode>"
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131
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135 [(set (match_operand:AINT 0 "register_operand") ;; output
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136 (match_operand:AINT 1 "memory_operand")) ;; memory
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137 (use (match_operand:SI 2 "const_int_operand"))] ;; model
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111
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138 ""
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0
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139 {
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111
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140 if (<MODE>mode == TImode && !TARGET_SYNC_TI)
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141 FAIL;
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142
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143 enum memmodel model = memmodel_base (INTVAL (operands[2]));
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144
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145 if (is_mm_seq_cst (model))
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146 emit_insn (gen_hwsync ());
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147
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148 if (<MODE>mode != TImode)
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149 emit_move_insn (operands[0], operands[1]);
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150 else
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151 {
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152 rtx op0 = operands[0];
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153 rtx op1 = operands[1];
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154 rtx pti_reg = gen_reg_rtx (PTImode);
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155
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156 if (!quad_address_p (XEXP (op1, 0), TImode, false))
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157 {
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158 rtx old_addr = XEXP (op1, 0);
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159 rtx new_addr = force_reg (Pmode, old_addr);
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160 operands[1] = op1 = replace_equiv_address (op1, new_addr);
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161 }
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0
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162
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111
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163 emit_insn (gen_load_quadpti (pti_reg, op1));
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164
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165 if (WORDS_BIG_ENDIAN)
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166 emit_move_insn (op0, gen_lowpart (TImode, pti_reg));
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167 else
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168 {
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169 emit_move_insn (gen_lowpart (DImode, op0), gen_highpart (DImode, pti_reg));
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170 emit_move_insn (gen_highpart (DImode, op0), gen_lowpart (DImode, pti_reg));
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171 }
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172 }
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173
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174 switch (model)
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175 {
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176 case MEMMODEL_RELAXED:
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177 break;
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178 case MEMMODEL_CONSUME:
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179 case MEMMODEL_ACQUIRE:
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180 case MEMMODEL_SEQ_CST:
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181 emit_insn (gen_loadsync_<mode> (operands[0]));
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182 break;
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183 default:
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184 gcc_unreachable ();
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185 }
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186 DONE;
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187 })
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188
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111
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189 (define_insn "store_quadpti"
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190 [(set (match_operand:PTI 0 "quad_memory_operand" "=wQ")
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191 (unspec:PTI
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192 [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))]
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193 "TARGET_SYNC_TI"
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194 "stq %1,%0"
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131
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195 [(set_attr "type" "store")])
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0
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196
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111
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197 (define_expand "atomic_store<mode>"
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131
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198 [(set (match_operand:AINT 0 "memory_operand") ;; memory
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199 (match_operand:AINT 1 "register_operand")) ;; input
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200 (use (match_operand:SI 2 "const_int_operand"))] ;; model
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111
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201 ""
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0
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202 {
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111
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203 if (<MODE>mode == TImode && !TARGET_SYNC_TI)
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204 FAIL;
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0
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205
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111
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206 enum memmodel model = memmodel_base (INTVAL (operands[2]));
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207 switch (model)
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208 {
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111
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209 case MEMMODEL_RELAXED:
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210 break;
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211 case MEMMODEL_RELEASE:
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212 emit_insn (gen_lwsync ());
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213 break;
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214 case MEMMODEL_SEQ_CST:
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215 emit_insn (gen_hwsync ());
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216 break;
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217 default:
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218 gcc_unreachable ();
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0
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219 }
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111
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220 if (<MODE>mode != TImode)
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221 emit_move_insn (operands[0], operands[1]);
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222 else
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223 {
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224 rtx op0 = operands[0];
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225 rtx op1 = operands[1];
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226 rtx pti_reg = gen_reg_rtx (PTImode);
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0
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227
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111
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228 if (!quad_address_p (XEXP (op0, 0), TImode, false))
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229 {
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230 rtx old_addr = XEXP (op0, 0);
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231 rtx new_addr = force_reg (Pmode, old_addr);
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232 operands[0] = op0 = replace_equiv_address (op0, new_addr);
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233 }
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0
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234
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111
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235 if (WORDS_BIG_ENDIAN)
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236 emit_move_insn (pti_reg, gen_lowpart (PTImode, op1));
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237 else
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238 {
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239 emit_move_insn (gen_lowpart (DImode, pti_reg), gen_highpart (DImode, op1));
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240 emit_move_insn (gen_highpart (DImode, pti_reg), gen_lowpart (DImode, op1));
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241 }
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242
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243 emit_insn (gen_store_quadpti (gen_lowpart (PTImode, op0), pti_reg));
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244 }
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245
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246 DONE;
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247 })
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248
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111
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249 ;; Any supported integer mode that has atomic l<x>arx/st<x>cx. instrucitons
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250 ;; other than the quad memory operations, which have special restrictions.
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251 ;; Byte/halfword atomic instructions were added in ISA 2.06B, but were phased
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252 ;; in and did not show up until power8. TImode atomic lqarx/stqcx. require
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253 ;; special handling due to even/odd register requirements.
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254 (define_mode_iterator ATOMIC [(QI "TARGET_SYNC_HI_QI")
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255 (HI "TARGET_SYNC_HI_QI")
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256 SI
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257 (DI "TARGET_POWERPC64")])
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0
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258
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111
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259 (define_insn "load_locked<mode>"
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260 [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r")
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261 (unspec_volatile:ATOMIC
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262 [(match_operand:ATOMIC 1 "memory_operand" "Z")] UNSPECV_LL))]
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263 ""
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264 "<larx> %0,%y1"
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265 [(set_attr "type" "load_l")])
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266
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267 (define_insn "load_locked<QHI:mode>_si"
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268 [(set (match_operand:SI 0 "int_reg_operand" "=r")
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269 (unspec_volatile:SI
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270 [(match_operand:QHI 1 "memory_operand" "Z")] UNSPECV_LL))]
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271 "TARGET_SYNC_HI_QI"
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272 "<QHI:larx> %0,%y1"
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273 [(set_attr "type" "load_l")])
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0
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274
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111
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275 ;; Use PTImode to get even/odd register pairs.
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276 ;; Use a temporary register to force getting an even register for the
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277 ;; lqarx/stqcrx. instructions. Normal optimizations will eliminate this extra
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278 ;; copy on big endian systems.
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279
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280 ;; On little endian systems where non-atomic quad word load/store instructions
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281 ;; are not used, the address can be register+offset, so make sure the address
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282 ;; is indexed or indirect before register allocation.
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0
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283
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111
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284 (define_expand "load_lockedti"
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131
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285 [(use (match_operand:TI 0 "quad_int_reg_operand"))
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286 (use (match_operand:TI 1 "memory_operand"))]
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111
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287 "TARGET_SYNC_TI"
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0
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288 {
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111
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289 rtx op0 = operands[0];
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290 rtx op1 = operands[1];
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291 rtx pti = gen_reg_rtx (PTImode);
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0
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292
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111
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293 if (!indexed_or_indirect_operand (op1, TImode))
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294 {
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295 rtx old_addr = XEXP (op1, 0);
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296 rtx new_addr = force_reg (Pmode, old_addr);
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297 operands[1] = op1 = change_address (op1, TImode, new_addr);
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298 }
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299
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300 emit_insn (gen_load_lockedpti (pti, op1));
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301 if (WORDS_BIG_ENDIAN)
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302 emit_move_insn (op0, gen_lowpart (TImode, pti));
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303 else
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304 {
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305 emit_move_insn (gen_lowpart (DImode, op0), gen_highpart (DImode, pti));
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306 emit_move_insn (gen_highpart (DImode, op0), gen_lowpart (DImode, pti));
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307 }
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0
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308 DONE;
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309 })
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310
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111
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311 (define_insn "load_lockedpti"
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312 [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
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313 (unspec_volatile:PTI
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314 [(match_operand:TI 1 "indexed_or_indirect_operand" "Z")] UNSPECV_LL))]
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315 "TARGET_SYNC_TI
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316 && !reg_mentioned_p (operands[0], operands[1])
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317 && quad_int_reg_operand (operands[0], PTImode)"
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318 "lqarx %0,%y1"
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319 [(set_attr "type" "load_l")])
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320
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321 (define_insn "store_conditional<mode>"
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322 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
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323 (unspec_volatile:CC [(const_int 0)] UNSPECV_SC))
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324 (set (match_operand:ATOMIC 1 "memory_operand" "=Z")
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325 (match_operand:ATOMIC 2 "int_reg_operand" "r"))]
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326 ""
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327 "<stcx> %2,%y1"
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328 [(set_attr "type" "store_c")])
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329
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330 ;; Use a temporary register to force getting an even register for the
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331 ;; lqarx/stqcrx. instructions. Normal optimizations will eliminate this extra
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332 ;; copy on big endian systems.
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333
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334 ;; On little endian systems where non-atomic quad word load/store instructions
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335 ;; are not used, the address can be register+offset, so make sure the address
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336 ;; is indexed or indirect before register allocation.
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337
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338 (define_expand "store_conditionalti"
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131
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339 [(use (match_operand:CC 0 "cc_reg_operand"))
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340 (use (match_operand:TI 1 "memory_operand"))
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341 (use (match_operand:TI 2 "quad_int_reg_operand"))]
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111
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342 "TARGET_SYNC_TI"
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0
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343 {
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111
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344 rtx op0 = operands[0];
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345 rtx op1 = operands[1];
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346 rtx op2 = operands[2];
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347 rtx addr = XEXP (op1, 0);
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348 rtx pti_mem;
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349 rtx pti_reg;
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350
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351 if (!indexed_or_indirect_operand (op1, TImode))
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0
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352 {
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111
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353 rtx new_addr = force_reg (Pmode, addr);
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354 operands[1] = op1 = change_address (op1, TImode, new_addr);
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355 addr = new_addr;
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0
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356 }
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111
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357
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358 pti_mem = change_address (op1, PTImode, addr);
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359 pti_reg = gen_reg_rtx (PTImode);
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0
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360
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111
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361 if (WORDS_BIG_ENDIAN)
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362 emit_move_insn (pti_reg, gen_lowpart (PTImode, op2));
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363 else
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364 {
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365 emit_move_insn (gen_lowpart (DImode, pti_reg), gen_highpart (DImode, op2));
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366 emit_move_insn (gen_highpart (DImode, pti_reg), gen_lowpart (DImode, op2));
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367 }
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368
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369 emit_insn (gen_store_conditionalpti (op0, pti_mem, pti_reg));
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0
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370 DONE;
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371 })
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372
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111
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373 (define_insn "store_conditionalpti"
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374 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
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375 (unspec_volatile:CC [(const_int 0)] UNSPECV_SC))
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376 (set (match_operand:PTI 1 "indexed_or_indirect_operand" "=Z")
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377 (match_operand:PTI 2 "quad_int_reg_operand" "r"))]
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378 "TARGET_SYNC_TI && quad_int_reg_operand (operands[2], PTImode)"
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379 "stqcx. %2,%y1"
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380 [(set_attr "type" "store_c")])
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0
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381
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111
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382 (define_expand "atomic_compare_and_swap<mode>"
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131
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383 [(match_operand:SI 0 "int_reg_operand") ;; bool out
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384 (match_operand:AINT 1 "int_reg_operand") ;; val out
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385 (match_operand:AINT 2 "memory_operand") ;; memory
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386 (match_operand:AINT 3 "reg_or_short_operand") ;; expected
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387 (match_operand:AINT 4 "int_reg_operand") ;; desired
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388 (match_operand:SI 5 "const_int_operand") ;; is_weak
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389 (match_operand:SI 6 "const_int_operand") ;; model succ
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390 (match_operand:SI 7 "const_int_operand")] ;; model fail
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111
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391 ""
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392 {
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393 rs6000_expand_atomic_compare_and_swap (operands);
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394 DONE;
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395 })
|
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0
|
396
|
|
111
|
397 (define_expand "atomic_exchange<mode>"
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131
|
398 [(match_operand:AINT 0 "int_reg_operand") ;; output
|
|
|
399 (match_operand:AINT 1 "memory_operand") ;; memory
|
|
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400 (match_operand:AINT 2 "int_reg_operand") ;; input
|
|
|
401 (match_operand:SI 3 "const_int_operand")] ;; model
|
|
111
|
402 ""
|
|
|
403 {
|
|
|
404 rs6000_expand_atomic_exchange (operands);
|
|
|
405 DONE;
|
|
|
406 })
|
|
0
|
407
|
|
111
|
408 (define_expand "atomic_<fetchop_name><mode>"
|
|
131
|
409 [(match_operand:AINT 0 "memory_operand") ;; memory
|
|
111
|
410 (FETCHOP:AINT (match_dup 0)
|
|
131
|
411 (match_operand:AINT 1 "<fetchop_pred>")) ;; operand
|
|
|
412 (match_operand:SI 2 "const_int_operand")] ;; model
|
|
111
|
413 ""
|
|
|
414 {
|
|
|
415 rs6000_expand_atomic_op (<CODE>, operands[0], operands[1],
|
|
|
416 NULL_RTX, NULL_RTX, operands[2]);
|
|
|
417 DONE;
|
|
|
418 })
|
|
0
|
419
|
|
111
|
420 (define_expand "atomic_nand<mode>"
|
|
131
|
421 [(match_operand:AINT 0 "memory_operand") ;; memory
|
|
|
422 (match_operand:AINT 1 "int_reg_operand") ;; operand
|
|
|
423 (match_operand:SI 2 "const_int_operand")] ;; model
|
|
0
|
424 ""
|
|
|
425 {
|
|
111
|
426 rs6000_expand_atomic_op (NOT, operands[0], operands[1],
|
|
|
427 NULL_RTX, NULL_RTX, operands[2]);
|
|
|
428 DONE;
|
|
|
429 })
|
|
|
430
|
|
|
431 (define_expand "atomic_fetch_<fetchop_name><mode>"
|
|
131
|
432 [(match_operand:AINT 0 "int_reg_operand") ;; output
|
|
|
433 (match_operand:AINT 1 "memory_operand") ;; memory
|
|
111
|
434 (FETCHOP:AINT (match_dup 1)
|
|
131
|
435 (match_operand:AINT 2 "<fetchop_pred>")) ;; operand
|
|
|
436 (match_operand:SI 3 "const_int_operand")] ;; model
|
|
111
|
437 ""
|
|
|
438 {
|
|
|
439 rs6000_expand_atomic_op (<CODE>, operands[1], operands[2],
|
|
|
440 operands[0], NULL_RTX, operands[3]);
|
|
|
441 DONE;
|
|
|
442 })
|
|
0
|
443
|
|
111
|
444 (define_expand "atomic_fetch_nand<mode>"
|
|
131
|
445 [(match_operand:AINT 0 "int_reg_operand") ;; output
|
|
|
446 (match_operand:AINT 1 "memory_operand") ;; memory
|
|
|
447 (match_operand:AINT 2 "int_reg_operand") ;; operand
|
|
|
448 (match_operand:SI 3 "const_int_operand")] ;; model
|
|
111
|
449 ""
|
|
|
450 {
|
|
|
451 rs6000_expand_atomic_op (NOT, operands[1], operands[2],
|
|
|
452 operands[0], NULL_RTX, operands[3]);
|
|
|
453 DONE;
|
|
|
454 })
|
|
|
455
|
|
|
456 (define_expand "atomic_<fetchop_name>_fetch<mode>"
|
|
131
|
457 [(match_operand:AINT 0 "int_reg_operand") ;; output
|
|
|
458 (match_operand:AINT 1 "memory_operand") ;; memory
|
|
111
|
459 (FETCHOP:AINT (match_dup 1)
|
|
131
|
460 (match_operand:AINT 2 "<fetchop_pred>")) ;; operand
|
|
|
461 (match_operand:SI 3 "const_int_operand")] ;; model
|
|
111
|
462 ""
|
|
|
463 {
|
|
|
464 rs6000_expand_atomic_op (<CODE>, operands[1], operands[2],
|
|
|
465 NULL_RTX, operands[0], operands[3]);
|
|
|
466 DONE;
|
|
|
467 })
|
|
|
468
|
|
|
469 (define_expand "atomic_nand_fetch<mode>"
|
|
131
|
470 [(match_operand:AINT 0 "int_reg_operand") ;; output
|
|
|
471 (match_operand:AINT 1 "memory_operand") ;; memory
|
|
|
472 (match_operand:AINT 2 "int_reg_operand") ;; operand
|
|
|
473 (match_operand:SI 3 "const_int_operand")] ;; model
|
|
111
|
474 ""
|
|
|
475 {
|
|
|
476 rs6000_expand_atomic_op (NOT, operands[1], operands[2],
|
|
|
477 NULL_RTX, operands[0], operands[3]);
|
|
|
478 DONE;
|
|
|
479 })
|
