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annotate gcc/config/rs6000/vector.md @ 158:494b0b89df80 default tip

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author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Mon, 25 May 2020 18:13:55 +0900
parents 1830386684a0
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ;; Expander definitions for vector support between altivec & vsx. No
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2 ;; instructions are in this file, this file provides the generic vector
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3 ;; expander, and the actual vector instructions will be in altivec.md and
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4 ;; vsx.md
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5
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6 ;; Copyright (C) 2009-2020 Free Software Foundation, Inc.
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7 ;; Contributed by Michael Meissner <meissner@linux.vnet.ibm.com>
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8
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9 ;; This file is part of GCC.
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10
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11 ;; GCC is free software; you can redistribute it and/or modify it
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12 ;; under the terms of the GNU General Public License as published
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13 ;; by the Free Software Foundation; either version 3, or (at your
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14 ;; option) any later version.
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15
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16 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
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17 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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18 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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19 ;; License for more details.
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20
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21 ;; You should have received a copy of the GNU General Public License
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22 ;; along with GCC; see the file COPYING3. If not see
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23 ;; <http://www.gnu.org/licenses/>.
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24
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25
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26 ;; Vector int modes
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27 (define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI])
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28
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29 ;; Vector int modes for parity
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30 (define_mode_iterator VEC_IP [V8HI
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31 V4SI
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32 V2DI
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33 V1TI
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34 TI])
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35
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36 ;; Vector float modes
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37 (define_mode_iterator VEC_F [V4SF V2DF])
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38
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39 ;; Vector arithmetic modes
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40 (define_mode_iterator VEC_A [V16QI V8HI V4SI V2DI V4SF V2DF])
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41
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42 ;; Vector modes that need alginment via permutes
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43 (define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF])
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44
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45 ;; Vector logical modes
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46 (define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF V1TI TI KF TF])
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47
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48 ;; Vector modes for moves. Don't do TImode or TFmode here, since their
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49 ;; moves are handled elsewhere.
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50 (define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF V1TI KF])
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51
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52 ;; Vector modes for types that don't need a realignment under VSX
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53 (define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF V1TI KF TF])
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54
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55 ;; Vector comparison modes
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56 (define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF])
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57
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58 ;; Vector init/extract modes
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59 (define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF])
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60
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61 ;; Vector modes for 64-bit base types
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62 (define_mode_iterator VEC_64 [V2DI V2DF])
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63
111
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64 ;; Vector integer modes
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65 (define_mode_iterator VI [V4SI V8HI V16QI])
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66
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67 ;; Base type from vector mode
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68 (define_mode_attr VEC_base [(V16QI "QI")
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69 (V8HI "HI")
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70 (V4SI "SI")
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71 (V2DI "DI")
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72 (V4SF "SF")
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73 (V2DF "DF")
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74 (V1TI "TI")
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75 (TI "TI")])
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76
111
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77 ;; As above, but in lower case
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78 (define_mode_attr VEC_base_l [(V16QI "qi")
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79 (V8HI "hi")
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80 (V4SI "si")
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81 (V2DI "di")
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82 (V4SF "sf")
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83 (V2DF "df")
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84 (V1TI "ti")
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85 (TI "ti")])
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86
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87 ;; Same size integer type for floating point data
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88 (define_mode_attr VEC_int [(V4SF "v4si")
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89 (V2DF "v2di")])
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90
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91 (define_mode_attr VEC_INT [(V4SF "V4SI")
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92 (V2DF "V2DI")])
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93
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94 ;; constants for unspec
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95 (define_c_enum "unspec" [UNSPEC_PREDICATE
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96 UNSPEC_REDUC
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97 UNSPEC_NEZ_P])
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98
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99 ;; Vector reduction code iterators
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100 (define_code_iterator VEC_reduc [plus smin smax])
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101
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102 (define_code_attr VEC_reduc_name [(plus "plus")
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103 (smin "smin")
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104 (smax "smax")])
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105
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106 (define_code_attr VEC_reduc_rtx [(plus "add")
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107 (smin "smin")
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108 (smax "smax")])
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109
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110 ;; code iterators and attributes for vector FP comparison operators:
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111 (define_code_iterator
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112 vector_fp_comparison_simple [lt le ne ungt unge unlt unle])
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113 (define_code_iterator
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114 vector_fp_comparison_complex [ltgt uneq unordered ordered])
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115
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116
111
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117 ;; Vector move instructions. Little-endian VSX loads and stores require
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118 ;; special handling to circumvent "element endianness."
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119 (define_expand "mov<mode>"
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120 [(set (match_operand:VEC_M 0 "nonimmediate_operand")
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121 (match_operand:VEC_M 1 "any_operand"))]
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122 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
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123 {
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124 if (can_create_pseudo_p ())
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125 {
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126 if (CONSTANT_P (operands[1]))
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127 {
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128 if (FLOAT128_VECTOR_P (<MODE>mode))
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129 {
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130 if (!easy_fp_constant (operands[1], <MODE>mode))
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131 operands[1] = force_const_mem (<MODE>mode, operands[1]);
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132 }
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133 else if (!easy_vector_constant (operands[1], <MODE>mode))
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134 operands[1] = force_const_mem (<MODE>mode, operands[1]);
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135 }
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136
111
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137 if (!vlogical_operand (operands[0], <MODE>mode)
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138 && !vlogical_operand (operands[1], <MODE>mode))
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139 operands[1] = force_reg (<MODE>mode, operands[1]);
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140 }
131
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141 /* When generating load/store instructions to/from VSX registers on
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142 pre-power9 hardware in little endian mode, we need to emit register
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143 permute instructions to byte swap the contents, since the VSX load/store
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144 instructions do not include a byte swap as part of their operation.
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145 Altivec loads and stores have no such problem, so we skip them below. */
111
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146 if (!BYTES_BIG_ENDIAN
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147 && VECTOR_MEM_VSX_P (<MODE>mode)
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148 && !TARGET_P9_VECTOR
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149 && !gpr_or_gpr_p (operands[0], operands[1])
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150 && ((memory_operand (operands[0], <MODE>mode)
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151 && !altivec_indexed_or_indirect_operand(operands[0], <MODE>mode))
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152 ^ (memory_operand (operands[1], <MODE>mode)
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153 && !altivec_indexed_or_indirect_operand(operands[1], <MODE>mode))))
111
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154 {
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155 rs6000_emit_le_vsx_move (operands[0], operands[1], <MODE>mode);
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156 DONE;
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157 }
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158 })
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159
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160 ;; Generic vector floating point load/store instructions. These will match
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161 ;; insns defined in vsx.md or altivec.md depending on the switches.
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162 (define_expand "vector_load_<mode>"
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163 [(set (match_operand:VEC_M 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
164 (match_operand:VEC_M 1 "memory_operand"))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
165 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
167
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
168 (define_expand "vector_store_<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
169 [(set (match_operand:VEC_M 0 "memory_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
170 (match_operand:VEC_M 1 "vfloat_operand"))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
171 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
172 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
173
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
174 ;; Splits if a GPR register was chosen for the move
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
175 (define_split
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
176 [(set (match_operand:VEC_L 0 "nonimmediate_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
177 (match_operand:VEC_L 1 "input_operand"))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
178 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
179 && reload_completed
111
kono
parents: 67
diff changeset
180 && gpr_or_gpr_p (operands[0], operands[1])
kono
parents: 67
diff changeset
181 && !direct_move_p (operands[0], operands[1])
kono
parents: 67
diff changeset
182 && !quad_load_store_p (operands[0], operands[1])"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
183 [(pc)]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
184 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 rs6000_split_multireg_move (operands[0], operands[1]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
187 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
188
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
189
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
190 ;; Generic floating point vector arithmetic support
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
191 (define_expand "add<mode>3"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
192 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
193 (plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
194 (match_operand:VEC_F 2 "vfloat_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
195 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
196 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
197
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
198 (define_expand "sub<mode>3"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
199 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
200 (minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
201 (match_operand:VEC_F 2 "vfloat_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
202 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
203 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
204
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
205 (define_expand "mul<mode>3"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
206 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
207 (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
208 (match_operand:VEC_F 2 "vfloat_operand")))]
111
kono
parents: 67
diff changeset
209 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
210 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
211 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
212 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
213 emit_insn (gen_altivec_mulv4sf3 (operands[0], operands[1], operands[2]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
214 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
215 }
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
216 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
217
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
218 (define_expand "div<mode>3"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
219 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
220 (div:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
221 (match_operand:VEC_F 2 "vfloat_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
222 "VECTOR_UNIT_VSX_P (<MODE>mode)"
111
kono
parents: 67
diff changeset
223 {
kono
parents: 67
diff changeset
224 if (RS6000_RECIP_AUTO_RE_P (<MODE>mode)
kono
parents: 67
diff changeset
225 && can_create_pseudo_p () && flag_finite_math_only
kono
parents: 67
diff changeset
226 && !flag_trapping_math && flag_reciprocal_math)
kono
parents: 67
diff changeset
227 {
kono
parents: 67
diff changeset
228 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
kono
parents: 67
diff changeset
229 DONE;
kono
parents: 67
diff changeset
230 }
kono
parents: 67
diff changeset
231 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
232
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
233 (define_expand "neg<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
234 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
235 (neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
236 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
237 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
238 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
239 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
240 emit_insn (gen_altivec_negv4sf2 (operands[0], operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
241 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
242 }
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
243 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
244
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
245 (define_expand "abs<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
246 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
247 (abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
248 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
249 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
250 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
252 emit_insn (gen_altivec_absv4sf2 (operands[0], operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
253 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
254 }
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
255 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
256
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
257 (define_expand "smin<mode>3"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
258 [(set (match_operand:VEC_F 0 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
259 (smin:VEC_F (match_operand:VEC_F 1 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
260 (match_operand:VEC_F 2 "register_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
261 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
262 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
263
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
264 (define_expand "smax<mode>3"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
265 [(set (match_operand:VEC_F 0 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
266 (smax:VEC_F (match_operand:VEC_F 1 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
267 (match_operand:VEC_F 2 "register_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
268 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
269 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
270
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
271
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
272 (define_expand "sqrt<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
273 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
274 (sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
275 "VECTOR_UNIT_VSX_P (<MODE>mode)"
111
kono
parents: 67
diff changeset
276 {
kono
parents: 67
diff changeset
277 if (<MODE>mode == V4SFmode
kono
parents: 67
diff changeset
278 && !optimize_function_for_size_p (cfun)
kono
parents: 67
diff changeset
279 && flag_finite_math_only && !flag_trapping_math
kono
parents: 67
diff changeset
280 && flag_unsafe_math_optimizations)
kono
parents: 67
diff changeset
281 {
kono
parents: 67
diff changeset
282 rs6000_emit_swsqrt (operands[0], operands[1], 0);
kono
parents: 67
diff changeset
283 DONE;
kono
parents: 67
diff changeset
284 }
kono
parents: 67
diff changeset
285 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
286
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
287 (define_expand "rsqrte<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
288 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
289 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
290 UNSPEC_RSQRT))]
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
291 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
292 "")
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
293
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
294 (define_expand "re<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
295 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
296 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
67
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
297 UNSPEC_FRES))]
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
298 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
299 "")
f6334be47118 update gcc from gcc-4.6-20100522 to gcc-4.6-20110318
nobuyasu <dimolto@cr.ie.u-ryukyu.ac.jp>
parents: 63
diff changeset
300
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
301 (define_expand "ftrunc<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
302 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
303 (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
304 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
305 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
306
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
307 (define_expand "vector_ceil<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
308 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
309 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
310 UNSPEC_FRIP))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
311 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
312 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
313
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
314 (define_expand "vector_floor<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
315 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
316 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
317 UNSPEC_FRIM))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
318 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
319 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
320
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
321 (define_expand "vector_btrunc<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
322 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
323 (fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
324 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
325 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
326
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
327 (define_expand "vector_copysign<mode>3"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
328 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
329 (unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
330 (match_operand:VEC_F 2 "vfloat_operand")] UNSPEC_COPYSIGN))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
331 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
332 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
333 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
334 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
335 emit_insn (gen_altivec_copysign_v4sf3 (operands[0], operands[1],
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
336 operands[2]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
337 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
338 }
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
339 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
340
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
341
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
342 ;; Vector comparisons
111
kono
parents: 67
diff changeset
343 (define_expand "vcond<mode><mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
344 [(set (match_operand:VEC_F 0 "vfloat_operand")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
345 (if_then_else:VEC_F
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
346 (match_operator 3 "comparison_operator"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
347 [(match_operand:VEC_F 4 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
348 (match_operand:VEC_F 5 "vfloat_operand")])
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
349 (match_operand:VEC_F 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
350 (match_operand:VEC_F 2 "vfloat_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
351 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
352 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
353 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
354 operands[3], operands[4], operands[5]))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
355 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
356 else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
357 FAIL;
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
358 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
359
111
kono
parents: 67
diff changeset
360 (define_expand "vcond<mode><mode>"
kono
parents: 67
diff changeset
361 [(set (match_operand:VEC_I 0 "vint_operand")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
362 (if_then_else:VEC_I
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
363 (match_operator 3 "comparison_operator"
111
kono
parents: 67
diff changeset
364 [(match_operand:VEC_I 4 "vint_operand")
kono
parents: 67
diff changeset
365 (match_operand:VEC_I 5 "vint_operand")])
kono
parents: 67
diff changeset
366 (match_operand:VEC_I 1 "vector_int_reg_or_same_bit")
kono
parents: 67
diff changeset
367 (match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))]
kono
parents: 67
diff changeset
368 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
369 {
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
370 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
371 operands[3], operands[4], operands[5]))
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
372 DONE;
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
373 else
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
374 FAIL;
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
375 })
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
376
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
377 (define_expand "vcondv4sfv4si"
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
378 [(set (match_operand:V4SF 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
379 (if_then_else:V4SF
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
380 (match_operator 3 "comparison_operator"
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
381 [(match_operand:V4SI 4 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
382 (match_operand:V4SI 5 "vint_operand")])
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
383 (match_operand:V4SF 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
384 (match_operand:V4SF 2 "vfloat_operand")))]
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
385 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
386 && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
111
kono
parents: 67
diff changeset
387 {
kono
parents: 67
diff changeset
388 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
kono
parents: 67
diff changeset
389 operands[3], operands[4], operands[5]))
kono
parents: 67
diff changeset
390 DONE;
kono
parents: 67
diff changeset
391 else
kono
parents: 67
diff changeset
392 FAIL;
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
393 })
111
kono
parents: 67
diff changeset
394
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
395 (define_expand "vcondv4siv4sf"
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
396 [(set (match_operand:V4SI 0 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
397 (if_then_else:V4SI
111
kono
parents: 67
diff changeset
398 (match_operator 3 "comparison_operator"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
399 [(match_operand:V4SF 4 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
400 (match_operand:V4SF 5 "vfloat_operand")])
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
401 (match_operand:V4SI 1 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
402 (match_operand:V4SI 2 "vint_operand")))]
111
kono
parents: 67
diff changeset
403 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
kono
parents: 67
diff changeset
404 && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
405 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
406 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
407 operands[3], operands[4], operands[5]))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
408 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
409 else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
410 FAIL;
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
411 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
412
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
413 (define_expand "vcondv2dfv2di"
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
414 [(set (match_operand:V2DF 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
415 (if_then_else:V2DF
111
kono
parents: 67
diff changeset
416 (match_operator 3 "comparison_operator"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
417 [(match_operand:V2DI 4 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
418 (match_operand:V2DI 5 "vint_operand")])
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
419 (match_operand:V2DF 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
420 (match_operand:V2DF 2 "vfloat_operand")))]
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
421 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
422 && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DImode)"
111
kono
parents: 67
diff changeset
423 {
kono
parents: 67
diff changeset
424 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
kono
parents: 67
diff changeset
425 operands[3], operands[4], operands[5]))
kono
parents: 67
diff changeset
426 DONE;
kono
parents: 67
diff changeset
427 else
kono
parents: 67
diff changeset
428 FAIL;
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
429 })
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
430
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
431 (define_expand "vcondv2div2df"
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
432 [(set (match_operand:V2DI 0 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
433 (if_then_else:V2DI
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
434 (match_operator 3 "comparison_operator"
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
435 [(match_operand:V2DF 4 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
436 (match_operand:V2DF 5 "vfloat_operand")])
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
437 (match_operand:V2DI 1 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
438 (match_operand:V2DI 2 "vint_operand")))]
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
439 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
440 && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DImode)"
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
441 {
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
442 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
443 operands[3], operands[4], operands[5]))
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
444 DONE;
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
445 else
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
446 FAIL;
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
447 })
111
kono
parents: 67
diff changeset
448
kono
parents: 67
diff changeset
449 (define_expand "vcondu<mode><mode>"
kono
parents: 67
diff changeset
450 [(set (match_operand:VEC_I 0 "vint_operand")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
451 (if_then_else:VEC_I
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
452 (match_operator 3 "comparison_operator"
111
kono
parents: 67
diff changeset
453 [(match_operand:VEC_I 4 "vint_operand")
kono
parents: 67
diff changeset
454 (match_operand:VEC_I 5 "vint_operand")])
kono
parents: 67
diff changeset
455 (match_operand:VEC_I 1 "vector_int_reg_or_same_bit")
kono
parents: 67
diff changeset
456 (match_operand:VEC_I 2 "vector_int_reg_or_same_bit")))]
kono
parents: 67
diff changeset
457 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
kono
parents: 67
diff changeset
458 {
kono
parents: 67
diff changeset
459 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
kono
parents: 67
diff changeset
460 operands[3], operands[4], operands[5]))
kono
parents: 67
diff changeset
461 DONE;
kono
parents: 67
diff changeset
462 else
kono
parents: 67
diff changeset
463 FAIL;
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
464 })
111
kono
parents: 67
diff changeset
465
kono
parents: 67
diff changeset
466 (define_expand "vconduv4sfv4si"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
467 [(set (match_operand:V4SF 0 "vfloat_operand")
111
kono
parents: 67
diff changeset
468 (if_then_else:V4SF
kono
parents: 67
diff changeset
469 (match_operator 3 "comparison_operator"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
470 [(match_operand:V4SI 4 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
471 (match_operand:V4SI 5 "vint_operand")])
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
472 (match_operand:V4SF 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
473 (match_operand:V4SF 2 "vfloat_operand")))]
111
kono
parents: 67
diff changeset
474 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
kono
parents: 67
diff changeset
475 && VECTOR_UNIT_ALTIVEC_P (V4SImode)"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
476 {
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
477 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
478 operands[3], operands[4], operands[5]))
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
479 DONE;
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
480 else
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
481 FAIL;
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
482 })
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
483
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
484 (define_expand "vconduv2dfv2di"
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
485 [(set (match_operand:V2DF 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
486 (if_then_else:V2DF
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
487 (match_operator 3 "comparison_operator"
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
488 [(match_operand:V2DI 4 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
489 (match_operand:V2DI 5 "vint_operand")])
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
490 (match_operand:V2DF 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
491 (match_operand:V2DF 2 "vfloat_operand")))]
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
492 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
493 && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DImode)"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
494 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
495 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
496 operands[3], operands[4], operands[5]))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
497 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
498 else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
499 FAIL;
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
500 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
501
145
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
502 ;; To support vector condition vectorization, define vcond_mask and vec_cmp.
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
503
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
504 ;; Same mode for condition true/false values and predicate operand.
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
505 (define_expand "vcond_mask_<mode><mode>"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
506 [(match_operand:VEC_I 0 "vint_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
507 (match_operand:VEC_I 1 "vint_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
508 (match_operand:VEC_I 2 "vint_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
509 (match_operand:VEC_I 3 "vint_operand")]
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
510 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
511 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
512 emit_insn (gen_vector_select_<mode> (operands[0], operands[2], operands[1],
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
513 operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
514 DONE;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
515 })
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
516
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
517 ;; Condition true/false values are float but predicate operand is of
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
518 ;; type integer vector with same element size.
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
519 (define_expand "vcond_mask_<mode><VEC_int>"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
520 [(match_operand:VEC_F 0 "vfloat_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
521 (match_operand:VEC_F 1 "vfloat_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
522 (match_operand:VEC_F 2 "vfloat_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
523 (match_operand:<VEC_INT> 3 "vint_operand")]
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
524 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
525 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
526 emit_insn (gen_vector_select_<mode> (operands[0], operands[2], operands[1],
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
527 gen_lowpart (<MODE>mode, operands[3])));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
528 DONE;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
529 })
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
530
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
531 ;; For signed integer vectors comparison.
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
532 (define_expand "vec_cmp<mode><mode>"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
533 [(set (match_operand:VEC_I 0 "vint_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
534 (match_operator 1 "signed_or_equality_comparison_operator"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
535 [(match_operand:VEC_I 2 "vint_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
536 (match_operand:VEC_I 3 "vint_operand")]))]
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
537 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
538 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
539 enum rtx_code code = GET_CODE (operands[1]);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
540 rtx tmp = gen_reg_rtx (<MODE>mode);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
541 switch (code)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
542 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
543 case NE:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
544 emit_insn (gen_vector_eq<mode> (operands[0], operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
545 emit_insn (gen_one_cmpl<mode>2 (operands[0], operands[0]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
546 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
547 case EQ:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
548 emit_insn (gen_vector_eq<mode> (operands[0], operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
549 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
550 case GE:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
551 emit_insn (gen_vector_nlt<mode> (operands[0],operands[2], operands[3],
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
552 tmp));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
553 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
554 case GT:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
555 emit_insn (gen_vector_gt<mode> (operands[0], operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
556 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
557 case LE:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
558 emit_insn (gen_vector_ngt<mode> (operands[0], operands[2], operands[3],
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
559 tmp));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
560 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
561 case LT:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
562 emit_insn (gen_vector_gt<mode> (operands[0], operands[3], operands[2]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
563 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
564 default:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
565 gcc_unreachable ();
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
566 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
567 }
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
568 DONE;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
569 })
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
570
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
571 ;; For unsigned integer vectors comparison.
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
572 (define_expand "vec_cmpu<mode><mode>"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
573 [(set (match_operand:VEC_I 0 "vint_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
574 (match_operator 1 "unsigned_or_equality_comparison_operator"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
575 [(match_operand:VEC_I 2 "vint_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
576 (match_operand:VEC_I 3 "vint_operand")]))]
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
577 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
578 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
579 enum rtx_code code = GET_CODE (operands[1]);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
580 rtx tmp = gen_reg_rtx (<MODE>mode);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
581 switch (code)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
582 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
583 case NE:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
584 emit_insn (gen_vector_eq<mode> (operands[0], operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
585 emit_insn (gen_one_cmpl<mode>2 (operands[0], operands[0]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
586 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
587 case EQ:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
588 emit_insn (gen_vector_eq<mode> (operands[0], operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
589 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
590 case GEU:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
591 emit_insn (gen_vector_nltu<mode> (operands[0], operands[2], operands[3],
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
592 tmp));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
593 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
594 case GTU:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
595 emit_insn (gen_vector_gtu<mode> (operands[0], operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
596 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
597 case LEU:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
598 emit_insn (gen_vector_ngtu<mode> (operands[0], operands[2], operands[3],
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
599 tmp));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
600 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
601 case LTU:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
602 emit_insn (gen_vector_gtu<mode> (operands[0], operands[3], operands[2]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
603 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
604 default:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
605 gcc_unreachable ();
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
606 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
607 }
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
608 DONE;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
609 })
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
610
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
611 ;; For float point vectors comparison.
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
612 (define_expand "vec_cmp<mode><VEC_int>"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
613 [(set (match_operand:<VEC_INT> 0 "vint_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
614 (match_operator 1 "comparison_operator"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
615 [(match_operand:VEC_F 2 "vfloat_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
616 (match_operand:VEC_F 3 "vfloat_operand")]))]
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
617 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
618 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
619 enum rtx_code code = GET_CODE (operands[1]);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
620 rtx res = gen_reg_rtx (<MODE>mode);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
621 switch (code)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
622 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
623 case NE:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
624 emit_insn (gen_vector_ne<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
625 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
626 case EQ:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
627 emit_insn (gen_vector_eq<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
628 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
629 case GE:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
630 emit_insn (gen_vector_ge<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
631 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
632 case GT:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
633 emit_insn (gen_vector_gt<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
634 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
635 case LE:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
636 emit_insn (gen_vector_le<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
637 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
638 case LT:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
639 emit_insn (gen_vector_lt<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
640 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
641 case LTGT:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
642 emit_insn (gen_vector_ltgt<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
643 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
644 case UNORDERED:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
645 emit_insn (gen_vector_unordered<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
646 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
647 case ORDERED:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
648 emit_insn (gen_vector_ordered<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
649 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
650 case UNEQ:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
651 emit_insn (gen_vector_uneq<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
652 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
653 case UNGE:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
654 emit_insn (gen_vector_unge<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
655 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
656 case UNGT:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
657 emit_insn (gen_vector_ungt<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
658 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
659 case UNLE:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
660 emit_insn (gen_vector_unle<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
661 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
662 case UNLT:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
663 emit_insn (gen_vector_unlt<mode> (res, operands[2], operands[3]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
664 break;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
665
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
666 default:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
667 gcc_unreachable ();
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
668 }
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
669
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
670 emit_insn (gen_move_insn (operands[0], gen_lowpart (<VEC_INT>mode, res)));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
671 DONE;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
672 })
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
673
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
674 (define_expand "vector_eq<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
675 [(set (match_operand:VEC_C 0 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
676 (eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
677 (match_operand:VEC_C 2 "vlogical_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
678 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
679 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
680
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
681 (define_expand "vector_gt<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
682 [(set (match_operand:VEC_C 0 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
683 (gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
684 (match_operand:VEC_C 2 "vlogical_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
685 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
686 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
687
111
kono
parents: 67
diff changeset
688 ; >= for integer vectors: swap operands and apply not-greater-than
kono
parents: 67
diff changeset
689 (define_expand "vector_nlt<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
690 [(set (match_operand:VEC_I 3 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
691 (gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
692 (match_operand:VEC_I 1 "vlogical_operand")))
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
693 (set (match_operand:VEC_I 0 "vlogical_operand")
111
kono
parents: 67
diff changeset
694 (not:VEC_I (match_dup 3)))]
kono
parents: 67
diff changeset
695 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
kono
parents: 67
diff changeset
696 {
kono
parents: 67
diff changeset
697 operands[3] = gen_reg_rtx_and_attrs (operands[0]);
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
698 })
111
kono
parents: 67
diff changeset
699
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
700 (define_expand "vector_gtu<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
701 [(set (match_operand:VEC_I 0 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
702 (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
703 (match_operand:VEC_I 2 "vint_operand")))]
111
kono
parents: 67
diff changeset
704 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
705 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
706
111
kono
parents: 67
diff changeset
707 ; >= for integer vectors: swap operands and apply not-greater-than
kono
parents: 67
diff changeset
708 (define_expand "vector_nltu<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
709 [(set (match_operand:VEC_I 3 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
710 (gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
711 (match_operand:VEC_I 1 "vlogical_operand")))
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
712 (set (match_operand:VEC_I 0 "vlogical_operand")
111
kono
parents: 67
diff changeset
713 (not:VEC_I (match_dup 3)))]
kono
parents: 67
diff changeset
714 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
kono
parents: 67
diff changeset
715 {
kono
parents: 67
diff changeset
716 operands[3] = gen_reg_rtx_and_attrs (operands[0]);
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
717 })
111
kono
parents: 67
diff changeset
718
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
719 (define_expand "vector_geu<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
720 [(set (match_operand:VEC_I 0 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
721 (geu:VEC_I (match_operand:VEC_I 1 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
722 (match_operand:VEC_I 2 "vint_operand")))]
111
kono
parents: 67
diff changeset
723 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
724 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
725
111
kono
parents: 67
diff changeset
726 ; <= for integer vectors: apply not-greater-than
kono
parents: 67
diff changeset
727 (define_expand "vector_ngt<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
728 [(set (match_operand:VEC_I 3 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
729 (gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
730 (match_operand:VEC_I 2 "vlogical_operand")))
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
731 (set (match_operand:VEC_I 0 "vlogical_operand")
111
kono
parents: 67
diff changeset
732 (not:VEC_I (match_dup 3)))]
kono
parents: 67
diff changeset
733 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
kono
parents: 67
diff changeset
734 {
kono
parents: 67
diff changeset
735 operands[3] = gen_reg_rtx_and_attrs (operands[0]);
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
736 })
111
kono
parents: 67
diff changeset
737
kono
parents: 67
diff changeset
738 (define_expand "vector_ngtu<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
739 [(set (match_operand:VEC_I 3 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
740 (gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
741 (match_operand:VEC_I 2 "vlogical_operand")))
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
742 (set (match_operand:VEC_I 0 "vlogical_operand")
111
kono
parents: 67
diff changeset
743 (not:VEC_I (match_dup 3)))]
kono
parents: 67
diff changeset
744 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
kono
parents: 67
diff changeset
745 {
kono
parents: 67
diff changeset
746 operands[3] = gen_reg_rtx_and_attrs (operands[0]);
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
747 })
111
kono
parents: 67
diff changeset
748
145
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
749 ; There are 14 possible vector FP comparison operators, gt and eq of them have
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
750 ; been expanded above, so just support 12 remaining operators here.
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
751
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
752 ; For ge:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
753 (define_expand "vector_ge<mode>"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
754 [(set (match_operand:VEC_F 0 "vlogical_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
755 (ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
756 (match_operand:VEC_F 2 "vlogical_operand")))]
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
757 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
758 "")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
759
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
760 ; For lt/le/ne/ungt/unge/unlt/unle:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
761 ; lt(a,b) = gt(b,a)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
762 ; le(a,b) = ge(b,a)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
763 ; unge(a,b) = ~lt(a,b)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
764 ; unle(a,b) = ~gt(a,b)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
765 ; ne(a,b) = ~eq(a,b)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
766 ; ungt(a,b) = ~le(a,b)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
767 ; unlt(a,b) = ~ge(a,b)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
768 (define_insn_and_split "vector_<code><mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
769 [(set (match_operand:VEC_F 0 "vfloat_operand")
145
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
770 (vector_fp_comparison_simple:VEC_F
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
771 (match_operand:VEC_F 1 "vfloat_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
772 (match_operand:VEC_F 2 "vfloat_operand")))]
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
773 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
111
kono
parents: 67
diff changeset
774 "#"
145
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
775 "&& can_create_pseudo_p ()"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
776 [(pc)]
111
kono
parents: 67
diff changeset
777 {
145
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
778 enum rtx_code cond = <CODE>;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
779 bool need_invert = false;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
780
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
781 if (cond == UNLE || cond == UNLT || cond == NE || cond == UNGE
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
782 || cond == UNGT)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
783 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
784 cond = reverse_condition_maybe_unordered (cond);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
785 need_invert = true;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
786 }
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
787
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
788 if (cond == LT || cond == LE)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
789 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
790 cond = swap_condition (cond);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
791 std::swap (operands[1], operands[2]);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
792 }
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
793
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
794 gcc_assert (cond == EQ || cond == GE || cond == GT);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
795
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
796 rtx comp = gen_rtx_fmt_ee (cond, <MODE>mode, operands[1], operands[2]);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
797
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
798 if (need_invert)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
799 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
800 rtx res = gen_reg_rtx (<MODE>mode);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
801 emit_insn (gen_rtx_SET (res, comp));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
802 emit_insn (gen_one_cmpl<mode>2 (operands[0], res));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
803 }
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
804 else
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
805 emit_insn (gen_rtx_SET (operands[0], comp));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
806
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
807 DONE;
111
kono
parents: 67
diff changeset
808 })
kono
parents: 67
diff changeset
809
145
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
810 ; For ltgt/uneq/ordered/unordered:
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
811 ; ltgt: gt(a,b) | gt(b,a)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
812 ; uneq: ~(gt(a,b) | gt(b,a))
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
813 ; ordered: ge(a,b) | ge(b,a)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
814 ; unordered: ~(ge(a,b) | ge(b,a))
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
815 (define_insn_and_split "vector_<code><mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
816 [(set (match_operand:VEC_F 0 "vfloat_operand")
145
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
817 (vector_fp_comparison_complex:VEC_F
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
818 (match_operand:VEC_F 1 "vfloat_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
819 (match_operand:VEC_F 2 "vfloat_operand")))]
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
820 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
111
kono
parents: 67
diff changeset
821 "#"
145
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
822 "&& can_create_pseudo_p ()"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
823 [(pc)]
111
kono
parents: 67
diff changeset
824 {
145
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
825 enum rtx_code cond = <CODE>;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
826 bool need_invert = false;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
827
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
828 if (cond == UNORDERED || cond == UNEQ)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
829 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
830 cond = reverse_condition_maybe_unordered (cond);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
831 need_invert = true;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
832 }
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
833
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
834 if (cond == LTGT)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
835 cond = GT;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
836 else if (cond == ORDERED)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
837 cond = GE;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
838 else
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
839 gcc_unreachable ();
111
kono
parents: 67
diff changeset
840
145
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
841 rtx comp1 = gen_rtx_fmt_ee (cond, <MODE>mode, operands[1], operands[2]);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
842 rtx res1 = gen_reg_rtx (<MODE>mode);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
843 emit_insn (gen_rtx_SET (res1, comp1));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
844 rtx comp2 = gen_rtx_fmt_ee (cond, <MODE>mode, operands[2], operands[1]);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
845 rtx res2 = gen_reg_rtx (<MODE>mode);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
846 emit_insn (gen_rtx_SET (res2, comp2));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
847
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
848 if (need_invert)
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
849 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
850 rtx not1 = gen_rtx_fmt_e (NOT, <MODE>mode, res1);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
851 rtx not2 = gen_rtx_fmt_e (NOT, <MODE>mode, res2);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
852 rtx comp3 = gen_rtx_fmt_ee (AND, <MODE>mode, not1, not2);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
853 emit_insn (gen_rtx_SET (operands[0], comp3));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
854 }
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
855 else
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
856 emit_insn (gen_ior<mode>3 (operands[0], res1, res2));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
857
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
858 DONE;
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
859 })
111
kono
parents: 67
diff changeset
860
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
861 ;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
862 ;; which is in the reverse order that we want
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
863 (define_expand "vector_select_<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
864 [(set (match_operand:VEC_L 0 "vlogical_operand")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
865 (if_then_else:VEC_L
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
866 (ne:CC (match_operand:VEC_L 3 "vlogical_operand")
111
kono
parents: 67
diff changeset
867 (match_dup 4))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
868 (match_operand:VEC_L 2 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
869 (match_operand:VEC_L 1 "vlogical_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
870 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
111
kono
parents: 67
diff changeset
871 "operands[4] = CONST0_RTX (<MODE>mode);")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
872
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
873 (define_expand "vector_select_<mode>_uns"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
874 [(set (match_operand:VEC_L 0 "vlogical_operand")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
875 (if_then_else:VEC_L
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
876 (ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand")
111
kono
parents: 67
diff changeset
877 (match_dup 4))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
878 (match_operand:VEC_L 2 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
879 (match_operand:VEC_L 1 "vlogical_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
880 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
111
kono
parents: 67
diff changeset
881 "operands[4] = CONST0_RTX (<MODE>mode);")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
882
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
883 ;; Expansions that compare vectors producing a vector result and a predicate,
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
884 ;; setting CR6 to indicate a combined status
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
885 (define_expand "vector_eq_<mode>_p"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
886 [(parallel
111
kono
parents: 67
diff changeset
887 [(set (reg:CC CR6_REGNO)
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
888 (unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
889 (match_operand:VEC_A 2 "vlogical_operand"))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
890 UNSPEC_PREDICATE))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
891 (set (match_operand:VEC_A 0 "vlogical_operand")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
892 (eq:VEC_A (match_dup 1)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
893 (match_dup 2)))])]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
894 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
895 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
896
111
kono
parents: 67
diff changeset
897 ;; This expansion handles the V16QI, V8HI, and V4SI modes in the
kono
parents: 67
diff changeset
898 ;; implementation of the vec_all_ne built-in functions on Power9.
kono
parents: 67
diff changeset
899 (define_expand "vector_ne_<mode>_p"
kono
parents: 67
diff changeset
900 [(parallel
kono
parents: 67
diff changeset
901 [(set (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
902 (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand")
kono
parents: 67
diff changeset
903 (match_operand:VI 2 "vlogical_operand"))]
kono
parents: 67
diff changeset
904 UNSPEC_PREDICATE))
kono
parents: 67
diff changeset
905 (set (match_dup 3)
kono
parents: 67
diff changeset
906 (ne:VI (match_dup 1)
kono
parents: 67
diff changeset
907 (match_dup 2)))])
kono
parents: 67
diff changeset
908 (set (match_operand:SI 0 "register_operand" "=r")
kono
parents: 67
diff changeset
909 (lt:SI (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
910 (const_int 0)))]
kono
parents: 67
diff changeset
911 "TARGET_P9_VECTOR"
kono
parents: 67
diff changeset
912 {
kono
parents: 67
diff changeset
913 operands[3] = gen_reg_rtx (<MODE>mode);
kono
parents: 67
diff changeset
914 })
kono
parents: 67
diff changeset
915
kono
parents: 67
diff changeset
916 ;; This expansion handles the V16QI, V8HI, and V4SI modes in the
kono
parents: 67
diff changeset
917 ;; implementation of the vec_any_eq built-in functions on Power9.
kono
parents: 67
diff changeset
918 (define_expand "vector_ae_<mode>_p"
kono
parents: 67
diff changeset
919 [(parallel
kono
parents: 67
diff changeset
920 [(set (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
921 (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand")
kono
parents: 67
diff changeset
922 (match_operand:VI 2 "vlogical_operand"))]
kono
parents: 67
diff changeset
923 UNSPEC_PREDICATE))
kono
parents: 67
diff changeset
924 (set (match_dup 3)
kono
parents: 67
diff changeset
925 (ne:VI (match_dup 1)
kono
parents: 67
diff changeset
926 (match_dup 2)))])
kono
parents: 67
diff changeset
927 (set (match_operand:SI 0 "register_operand" "=r")
kono
parents: 67
diff changeset
928 (lt:SI (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
929 (const_int 0)))
kono
parents: 67
diff changeset
930 (set (match_dup 0)
kono
parents: 67
diff changeset
931 (xor:SI (match_dup 0)
kono
parents: 67
diff changeset
932 (const_int 1)))]
kono
parents: 67
diff changeset
933 "TARGET_P9_VECTOR"
kono
parents: 67
diff changeset
934 {
kono
parents: 67
diff changeset
935 operands[3] = gen_reg_rtx (<MODE>mode);
kono
parents: 67
diff changeset
936 })
kono
parents: 67
diff changeset
937
kono
parents: 67
diff changeset
938 ;; This expansion handles the V16QI, V8HI, and V4SI modes in the
kono
parents: 67
diff changeset
939 ;; implementation of the vec_all_nez and vec_any_eqz built-in
kono
parents: 67
diff changeset
940 ;; functions on Power9.
kono
parents: 67
diff changeset
941 (define_expand "vector_nez_<mode>_p"
kono
parents: 67
diff changeset
942 [(parallel
kono
parents: 67
diff changeset
943 [(set (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
944 (unspec:CC [(unspec:VI
kono
parents: 67
diff changeset
945 [(match_operand:VI 1 "vlogical_operand")
kono
parents: 67
diff changeset
946 (match_operand:VI 2 "vlogical_operand")]
kono
parents: 67
diff changeset
947 UNSPEC_NEZ_P)]
kono
parents: 67
diff changeset
948 UNSPEC_PREDICATE))
kono
parents: 67
diff changeset
949 (set (match_operand:VI 0 "vlogical_operand")
kono
parents: 67
diff changeset
950 (unspec:VI [(match_dup 1)
kono
parents: 67
diff changeset
951 (match_dup 2)]
kono
parents: 67
diff changeset
952 UNSPEC_NEZ_P))])]
kono
parents: 67
diff changeset
953 "TARGET_P9_VECTOR"
kono
parents: 67
diff changeset
954 "")
kono
parents: 67
diff changeset
955
kono
parents: 67
diff changeset
956 ;; This expansion handles the V2DI mode in the implementation of the
kono
parents: 67
diff changeset
957 ;; vec_all_ne built-in function on Power9.
kono
parents: 67
diff changeset
958 ;;
kono
parents: 67
diff changeset
959 ;; Since the Power9 "xvcmpne<mode>." instruction does not support DImode,
kono
parents: 67
diff changeset
960 ;; this expands into the same rtl that would be used for the Power8
kono
parents: 67
diff changeset
961 ;; architecture.
kono
parents: 67
diff changeset
962 (define_expand "vector_ne_v2di_p"
kono
parents: 67
diff changeset
963 [(parallel
kono
parents: 67
diff changeset
964 [(set (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
965 (unspec:CC [(eq:CC (match_operand:V2DI 1 "vlogical_operand")
kono
parents: 67
diff changeset
966 (match_operand:V2DI 2 "vlogical_operand"))]
kono
parents: 67
diff changeset
967 UNSPEC_PREDICATE))
kono
parents: 67
diff changeset
968 (set (match_dup 3)
kono
parents: 67
diff changeset
969 (eq:V2DI (match_dup 1)
kono
parents: 67
diff changeset
970 (match_dup 2)))])
kono
parents: 67
diff changeset
971 (set (match_operand:SI 0 "register_operand" "=r")
kono
parents: 67
diff changeset
972 (eq:SI (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
973 (const_int 0)))]
kono
parents: 67
diff changeset
974 "TARGET_P9_VECTOR"
kono
parents: 67
diff changeset
975 {
kono
parents: 67
diff changeset
976 operands[3] = gen_reg_rtx (V2DImode);
kono
parents: 67
diff changeset
977 })
kono
parents: 67
diff changeset
978
kono
parents: 67
diff changeset
979 ;; This expansion handles the V2DI mode in the implementation of the
kono
parents: 67
diff changeset
980 ;; vec_any_eq built-in function on Power9.
kono
parents: 67
diff changeset
981 ;;
kono
parents: 67
diff changeset
982 ;; Since the Power9 "xvcmpne<mode>." instruction does not support DImode,
kono
parents: 67
diff changeset
983 ;; this expands into the same rtl that would be used for the Power8
kono
parents: 67
diff changeset
984 ;; architecture.
kono
parents: 67
diff changeset
985 (define_expand "vector_ae_v2di_p"
kono
parents: 67
diff changeset
986 [(parallel
kono
parents: 67
diff changeset
987 [(set (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
988 (unspec:CC [(eq:CC (match_operand:V2DI 1 "vlogical_operand")
kono
parents: 67
diff changeset
989 (match_operand:V2DI 2 "vlogical_operand"))]
kono
parents: 67
diff changeset
990 UNSPEC_PREDICATE))
kono
parents: 67
diff changeset
991 (set (match_dup 3)
kono
parents: 67
diff changeset
992 (eq:V2DI (match_dup 1)
kono
parents: 67
diff changeset
993 (match_dup 2)))])
kono
parents: 67
diff changeset
994 (set (match_operand:SI 0 "register_operand" "=r")
kono
parents: 67
diff changeset
995 (eq:SI (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
996 (const_int 0)))
kono
parents: 67
diff changeset
997 (set (match_dup 0)
kono
parents: 67
diff changeset
998 (xor:SI (match_dup 0)
kono
parents: 67
diff changeset
999 (const_int 1)))]
kono
parents: 67
diff changeset
1000 "TARGET_P9_VECTOR"
kono
parents: 67
diff changeset
1001 {
kono
parents: 67
diff changeset
1002 operands[3] = gen_reg_rtx (V2DImode);
kono
parents: 67
diff changeset
1003 })
kono
parents: 67
diff changeset
1004
kono
parents: 67
diff changeset
1005 ;; This expansion handles the V4SF and V2DF modes in the Power9
kono
parents: 67
diff changeset
1006 ;; implementation of the vec_all_ne built-in functions. Note that the
kono
parents: 67
diff changeset
1007 ;; expansions for this pattern with these modes makes no use of power9-
kono
parents: 67
diff changeset
1008 ;; specific instructions since there are no new power9 instructions
kono
parents: 67
diff changeset
1009 ;; for vector compare not equal with floating point arguments.
kono
parents: 67
diff changeset
1010 (define_expand "vector_ne_<mode>_p"
kono
parents: 67
diff changeset
1011 [(parallel
kono
parents: 67
diff changeset
1012 [(set (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
1013 (unspec:CC [(eq:CC (match_operand:VEC_F 1 "vlogical_operand")
kono
parents: 67
diff changeset
1014 (match_operand:VEC_F 2 "vlogical_operand"))]
kono
parents: 67
diff changeset
1015 UNSPEC_PREDICATE))
kono
parents: 67
diff changeset
1016 (set (match_dup 3)
kono
parents: 67
diff changeset
1017 (eq:VEC_F (match_dup 1)
kono
parents: 67
diff changeset
1018 (match_dup 2)))])
kono
parents: 67
diff changeset
1019 (set (match_operand:SI 0 "register_operand" "=r")
kono
parents: 67
diff changeset
1020 (eq:SI (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
1021 (const_int 0)))]
kono
parents: 67
diff changeset
1022 "TARGET_P9_VECTOR"
kono
parents: 67
diff changeset
1023 {
kono
parents: 67
diff changeset
1024 operands[3] = gen_reg_rtx (<MODE>mode);
kono
parents: 67
diff changeset
1025 })
kono
parents: 67
diff changeset
1026
kono
parents: 67
diff changeset
1027 ;; This expansion handles the V4SF and V2DF modes in the Power9
kono
parents: 67
diff changeset
1028 ;; implementation of the vec_any_eq built-in functions. Note that the
kono
parents: 67
diff changeset
1029 ;; expansions for this pattern with these modes makes no use of power9-
kono
parents: 67
diff changeset
1030 ;; specific instructions since there are no new power9 instructions
kono
parents: 67
diff changeset
1031 ;; for vector compare not equal with floating point arguments.
kono
parents: 67
diff changeset
1032 (define_expand "vector_ae_<mode>_p"
kono
parents: 67
diff changeset
1033 [(parallel
kono
parents: 67
diff changeset
1034 [(set (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
1035 (unspec:CC [(eq:CC (match_operand:VEC_F 1 "vlogical_operand")
kono
parents: 67
diff changeset
1036 (match_operand:VEC_F 2 "vlogical_operand"))]
kono
parents: 67
diff changeset
1037 UNSPEC_PREDICATE))
kono
parents: 67
diff changeset
1038 (set (match_dup 3)
kono
parents: 67
diff changeset
1039 (eq:VEC_F (match_dup 1)
kono
parents: 67
diff changeset
1040 (match_dup 2)))])
kono
parents: 67
diff changeset
1041 (set (match_operand:SI 0 "register_operand" "=r")
kono
parents: 67
diff changeset
1042 (eq:SI (reg:CC CR6_REGNO)
kono
parents: 67
diff changeset
1043 (const_int 0)))
kono
parents: 67
diff changeset
1044 (set (match_dup 0)
kono
parents: 67
diff changeset
1045 (xor:SI (match_dup 0)
kono
parents: 67
diff changeset
1046 (const_int 1)))]
kono
parents: 67
diff changeset
1047 "TARGET_P9_VECTOR"
kono
parents: 67
diff changeset
1048 {
kono
parents: 67
diff changeset
1049 operands[3] = gen_reg_rtx (<MODE>mode);
kono
parents: 67
diff changeset
1050 })
kono
parents: 67
diff changeset
1051
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1052 (define_expand "vector_gt_<mode>_p"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1053 [(parallel
111
kono
parents: 67
diff changeset
1054 [(set (reg:CC CR6_REGNO)
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1055 (unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1056 (match_operand:VEC_A 2 "vlogical_operand"))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1057 UNSPEC_PREDICATE))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1058 (set (match_operand:VEC_A 0 "vlogical_operand")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1059 (gt:VEC_A (match_dup 1)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1060 (match_dup 2)))])]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1061 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1062 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1063
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1064 (define_expand "vector_ge_<mode>_p"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1065 [(parallel
111
kono
parents: 67
diff changeset
1066 [(set (reg:CC CR6_REGNO)
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1067 (unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1068 (match_operand:VEC_F 2 "vfloat_operand"))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1069 UNSPEC_PREDICATE))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1070 (set (match_operand:VEC_F 0 "vfloat_operand")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1071 (ge:VEC_F (match_dup 1)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1072 (match_dup 2)))])]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1073 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1074 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1075
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1076 (define_expand "vector_gtu_<mode>_p"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1077 [(parallel
111
kono
parents: 67
diff changeset
1078 [(set (reg:CC CR6_REGNO)
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1079 (unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1080 (match_operand:VEC_I 2 "vint_operand"))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1081 UNSPEC_PREDICATE))
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1082 (set (match_operand:VEC_I 0 "vlogical_operand")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1083 (gtu:VEC_I (match_dup 1)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1084 (match_dup 2)))])]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1085 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1086 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1087
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1088 ;; AltiVec/VSX predicates.
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1089
111
kono
parents: 67
diff changeset
1090 ;; This expansion is triggered during expansion of predicate built-in
kono
parents: 67
diff changeset
1091 ;; functions (built-ins defined with the RS6000_BUILTIN_P macro) by the
kono
parents: 67
diff changeset
1092 ;; altivec_expand_predicate_builtin() function when the value of the
kono
parents: 67
diff changeset
1093 ;; integer constant first argument equals zero (aka __CR6_EQ in altivec.h).
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1094 (define_expand "cr6_test_for_zero"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1095 [(set (match_operand:SI 0 "register_operand" "=r")
111
kono
parents: 67
diff changeset
1096 (eq:SI (reg:CC CR6_REGNO)
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1097 (const_int 0)))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1098 "TARGET_ALTIVEC || TARGET_VSX"
63
b7f97abdc517 update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
1099 "")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1100
111
kono
parents: 67
diff changeset
1101 ;; This expansion is triggered during expansion of predicate built-in
kono
parents: 67
diff changeset
1102 ;; functions (built-ins defined with the RS6000_BUILTIN_P macro) by the
kono
parents: 67
diff changeset
1103 ;; altivec_expand_predicate_builtin() function when the value of the
kono
parents: 67
diff changeset
1104 ;; integer constant first argument equals one (aka __CR6_EQ_REV in altivec.h).
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1105 (define_expand "cr6_test_for_zero_reverse"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1106 [(set (match_operand:SI 0 "register_operand" "=r")
111
kono
parents: 67
diff changeset
1107 (eq:SI (reg:CC CR6_REGNO)
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1108 (const_int 0)))
111
kono
parents: 67
diff changeset
1109 (set (match_dup 0)
kono
parents: 67
diff changeset
1110 (xor:SI (match_dup 0)
kono
parents: 67
diff changeset
1111 (const_int 1)))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1112 "TARGET_ALTIVEC || TARGET_VSX"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1113 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1114
111
kono
parents: 67
diff changeset
1115 ;; This expansion is triggered during expansion of predicate built-in
kono
parents: 67
diff changeset
1116 ;; functions (built-ins defined with the RS6000_BUILTIN_P macro) by the
kono
parents: 67
diff changeset
1117 ;; altivec_expand_predicate_builtin() function when the value of the
kono
parents: 67
diff changeset
1118 ;; integer constant first argument equals two (aka __CR6_LT in altivec.h).
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1119 (define_expand "cr6_test_for_lt"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1120 [(set (match_operand:SI 0 "register_operand" "=r")
111
kono
parents: 67
diff changeset
1121 (lt:SI (reg:CC CR6_REGNO)
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1122 (const_int 0)))]
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1123 "TARGET_ALTIVEC || TARGET_VSX"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1124 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1125
111
kono
parents: 67
diff changeset
1126 ;; This expansion is triggered during expansion of predicate built-in
kono
parents: 67
diff changeset
1127 ;; functions (built-ins defined with the RS6000_BUILTIN_P macro) by the
kono
parents: 67
diff changeset
1128 ;; altivec_expand_predicate_builtin() function when the value of the
kono
parents: 67
diff changeset
1129 ;; integer constant first argument equals three
kono
parents: 67
diff changeset
1130 ;; (aka __CR6_LT_REV in altivec.h).
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1131 (define_expand "cr6_test_for_lt_reverse"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1132 [(set (match_operand:SI 0 "register_operand" "=r")
111
kono
parents: 67
diff changeset
1133 (lt:SI (reg:CC CR6_REGNO)
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1134 (const_int 0)))
111
kono
parents: 67
diff changeset
1135 (set (match_dup 0)
kono
parents: 67
diff changeset
1136 (xor:SI (match_dup 0)
kono
parents: 67
diff changeset
1137 (const_int 1)))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1138 "TARGET_ALTIVEC || TARGET_VSX"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1139 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1140
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1141
111
kono
parents: 67
diff changeset
1142 ;; Vector count leading zeros
kono
parents: 67
diff changeset
1143 (define_expand "clz<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1144 [(set (match_operand:VEC_I 0 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1145 (clz:VEC_I (match_operand:VEC_I 1 "register_operand")))]
111
kono
parents: 67
diff changeset
1146 "TARGET_P8_VECTOR")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1147
111
kono
parents: 67
diff changeset
1148 ;; Vector count trailing zeros
kono
parents: 67
diff changeset
1149 (define_expand "ctz<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1150 [(set (match_operand:VEC_I 0 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1151 (ctz:VEC_I (match_operand:VEC_I 1 "register_operand")))]
111
kono
parents: 67
diff changeset
1152 "TARGET_P9_VECTOR")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1153
111
kono
parents: 67
diff changeset
1154 ;; Vector population count
kono
parents: 67
diff changeset
1155 (define_expand "popcount<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1156 [(set (match_operand:VEC_I 0 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1157 (popcount:VEC_I (match_operand:VEC_I 1 "register_operand")))]
111
kono
parents: 67
diff changeset
1158 "TARGET_P8_VECTOR")
63
b7f97abdc517 update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
1159
111
kono
parents: 67
diff changeset
1160 ;; Vector parity
kono
parents: 67
diff changeset
1161 (define_expand "parity<mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1162 [(set (match_operand:VEC_IP 0 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1163 (parity:VEC_IP (match_operand:VEC_IP 1 "register_operand")))]
111
kono
parents: 67
diff changeset
1164 "TARGET_P9_VECTOR")
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1165
111
kono
parents: 67
diff changeset
1166
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1167 ;; Same size conversions
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1168 (define_expand "float<VEC_int><mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1169 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1170 (float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1171 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1172 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1173 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1174 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1175 emit_insn (gen_altivec_vcfsx (operands[0], operands[1], const0_rtx));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1176 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1177 }
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1178 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1179
111
kono
parents: 67
diff changeset
1180 (define_expand "floatuns<VEC_int><mode>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1181 [(set (match_operand:VEC_F 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1182 (unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1183 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1184 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1185 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1186 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1187 emit_insn (gen_altivec_vcfux (operands[0], operands[1], const0_rtx));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1188 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1189 }
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1190 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1191
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1192 (define_expand "fix_trunc<mode><VEC_int>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1193 [(set (match_operand:<VEC_INT> 0 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1194 (fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1195 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1196 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1197 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1198 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1199 emit_insn (gen_altivec_vctsxs (operands[0], operands[1], const0_rtx));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1200 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1201 }
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1202 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1203
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1204 (define_expand "fixuns_trunc<mode><VEC_int>2"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1205 [(set (match_operand:<VEC_INT> 0 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1206 (unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand")))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1207 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1208 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1209 if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1210 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1211 emit_insn (gen_altivec_vctuxs (operands[0], operands[1], const0_rtx));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1212 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1213 }
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1214 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1215
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1216
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1217 ;; Vector initialization, set, extract
111
kono
parents: 67
diff changeset
1218 (define_expand "vec_init<mode><VEC_base_l>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1219 [(match_operand:VEC_E 0 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1220 (match_operand:VEC_E 1 "")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1221 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1222 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1223 rs6000_expand_vector_init (operands[0], operands[1]);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1224 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1225 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1226
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1227 (define_expand "vec_set<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1228 [(match_operand:VEC_E 0 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1229 (match_operand:<VEC_base> 1 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1230 (match_operand 2 "const_int_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1231 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1232 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1233 rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1234 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1235 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1236
111
kono
parents: 67
diff changeset
1237 (define_expand "vec_extract<mode><VEC_base_l>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1238 [(match_operand:<VEC_base> 0 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1239 (match_operand:VEC_E 1 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1240 (match_operand 2 "const_int_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1241 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1242 {
111
kono
parents: 67
diff changeset
1243 rs6000_expand_vector_extract (operands[0], operands[1], operands[2]);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1244 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1245 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1246
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1247 ;; Convert double word types to single word types
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1248 (define_expand "vec_pack_trunc_v2df"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1249 [(match_operand:V4SF 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1250 (match_operand:V2DF 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1251 (match_operand:V2DF 2 "vfloat_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1252 "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1253 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1254 rtx r1 = gen_reg_rtx (V4SFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1255 rtx r2 = gen_reg_rtx (V4SFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1256
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1257 emit_insn (gen_vsx_xvcvdpsp (r1, operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1258 emit_insn (gen_vsx_xvcvdpsp (r2, operands[2]));
111
kono
parents: 67
diff changeset
1259 rs6000_expand_extract_even (operands[0], r1, r2);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1260 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1261 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1262
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1263 (define_expand "vec_pack_sfix_trunc_v2df"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1264 [(match_operand:V4SI 0 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1265 (match_operand:V2DF 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1266 (match_operand:V2DF 2 "vfloat_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1267 "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1268 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1269 rtx r1 = gen_reg_rtx (V4SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1270 rtx r2 = gen_reg_rtx (V4SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1271
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1272 emit_insn (gen_vsx_xvcvdpsxws (r1, operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1273 emit_insn (gen_vsx_xvcvdpsxws (r2, operands[2]));
111
kono
parents: 67
diff changeset
1274 rs6000_expand_extract_even (operands[0], r1, r2);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1275 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1276 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1277
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1278 (define_expand "vec_pack_ufix_trunc_v2df"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1279 [(match_operand:V4SI 0 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1280 (match_operand:V2DF 1 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1281 (match_operand:V2DF 2 "vfloat_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1282 "VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1283 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1284 rtx r1 = gen_reg_rtx (V4SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1285 rtx r2 = gen_reg_rtx (V4SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1286
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1287 emit_insn (gen_vsx_xvcvdpuxws (r1, operands[1]));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1288 emit_insn (gen_vsx_xvcvdpuxws (r2, operands[2]));
111
kono
parents: 67
diff changeset
1289 rs6000_expand_extract_even (operands[0], r1, r2);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1290 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1291 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1292
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1293 ;; Convert single word types to double word
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1294 (define_expand "vec_unpacks_hi_v4sf"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1295 [(match_operand:V2DF 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1296 (match_operand:V4SF 1 "vfloat_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1297 "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1298 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1299 rtx reg = gen_reg_rtx (V4SFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1300
111
kono
parents: 67
diff changeset
1301 rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1302 emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1303 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1304 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1305
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1306 (define_expand "vec_unpacks_lo_v4sf"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1307 [(match_operand:V2DF 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1308 (match_operand:V4SF 1 "vfloat_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1309 "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1310 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1311 rtx reg = gen_reg_rtx (V4SFmode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1312
111
kono
parents: 67
diff changeset
1313 rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1314 emit_insn (gen_vsx_xvcvspdp (operands[0], reg));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1315 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1316 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1317
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1318 (define_expand "vec_unpacks_float_hi_v4si"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1319 [(match_operand:V2DF 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1320 (match_operand:V4SI 1 "vint_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1321 "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1322 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1323 rtx reg = gen_reg_rtx (V4SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1324
111
kono
parents: 67
diff changeset
1325 rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1326 emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1327 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1328 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1329
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1330 (define_expand "vec_unpacks_float_lo_v4si"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1331 [(match_operand:V2DF 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1332 (match_operand:V4SI 1 "vint_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1333 "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1334 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1335 rtx reg = gen_reg_rtx (V4SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1336
111
kono
parents: 67
diff changeset
1337 rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1338 emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1339 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1340 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1341
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1342 (define_expand "vec_unpacku_float_hi_v4si"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1343 [(match_operand:V2DF 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1344 (match_operand:V4SI 1 "vint_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1345 "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1346 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1347 rtx reg = gen_reg_rtx (V4SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1348
111
kono
parents: 67
diff changeset
1349 rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1350 emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1351 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1352 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1353
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1354 (define_expand "vec_unpacku_float_lo_v4si"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1355 [(match_operand:V2DF 0 "vfloat_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1356 (match_operand:V4SI 1 "vint_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1357 "VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1358 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1359 rtx reg = gen_reg_rtx (V4SImode);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1360
111
kono
parents: 67
diff changeset
1361 rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1362 emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg));
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1363 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1364 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1365
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1366
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1367 ;; Align vector loads with a permute.
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1368 (define_expand "vec_realign_load_<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1369 [(match_operand:VEC_K 0 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1370 (match_operand:VEC_K 1 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1371 (match_operand:VEC_K 2 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1372 (match_operand:V16QI 3 "vlogical_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1373 "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1374 {
111
kono
parents: 67
diff changeset
1375 if (BYTES_BIG_ENDIAN)
kono
parents: 67
diff changeset
1376 emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1],
kono
parents: 67
diff changeset
1377 operands[2], operands[3]));
kono
parents: 67
diff changeset
1378 else
kono
parents: 67
diff changeset
1379 {
kono
parents: 67
diff changeset
1380 /* We have changed lvsr to lvsl, so to complete the transformation
kono
parents: 67
diff changeset
1381 of vperm for LE, we must swap the inputs. */
kono
parents: 67
diff changeset
1382 rtx unspec = gen_rtx_UNSPEC (<MODE>mode,
kono
parents: 67
diff changeset
1383 gen_rtvec (3, operands[2],
kono
parents: 67
diff changeset
1384 operands[1], operands[3]),
kono
parents: 67
diff changeset
1385 UNSPEC_VPERM);
kono
parents: 67
diff changeset
1386 emit_move_insn (operands[0], unspec);
kono
parents: 67
diff changeset
1387 }
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1388 DONE;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1389 })
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1390
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1391 ;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1392 ;; since the load already handles it.
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1393 (define_expand "movmisalign<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1394 [(set (match_operand:VEC_N 0 "nonimmediate_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1395 (match_operand:VEC_N 1 "any_operand"))]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1396 "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1397 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1398
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1399 ;; Vector shift right in bits. Currently supported ony for shift
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1400 ;; amounts that can be expressed as byte shifts (divisible by 8).
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1401 ;; General shift amounts can be supported using vsro + vsr. We're
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1402 ;; not expecting to see these yet (the vectorizer currently
111
kono
parents: 67
diff changeset
1403 ;; generates only shifts by a whole number of vector elements).
kono
parents: 67
diff changeset
1404 ;; Note that the vec_shr operation is actually defined as
kono
parents: 67
diff changeset
1405 ;; 'shift toward element 0' so is a shr for LE and shl for BE.
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1406 (define_expand "vec_shr_<mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1407 [(match_operand:VEC_L 0 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1408 (match_operand:VEC_L 1 "vlogical_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1409 (match_operand:QI 2 "reg_or_short_operand")]
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1410 "TARGET_ALTIVEC"
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1411 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1412 rtx bitshift = operands[2];
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1413 rtx shift;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1414 rtx insn;
111
kono
parents: 67
diff changeset
1415 rtx zero_reg, op1, op2;
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1416 HOST_WIDE_INT bitshift_val;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1417 HOST_WIDE_INT byteshift_val;
63
b7f97abdc517 update gcc from gcc-4.5.0 to gcc-4.6
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents: 55
diff changeset
1418
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1419 if (! CONSTANT_P (bitshift))
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1420 FAIL;
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1421 bitshift_val = INTVAL (bitshift);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1422 if (bitshift_val & 0x7)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1423 FAIL;
111
kono
parents: 67
diff changeset
1424 byteshift_val = (bitshift_val >> 3);
kono
parents: 67
diff changeset
1425 zero_reg = gen_reg_rtx (<MODE>mode);
kono
parents: 67
diff changeset
1426 emit_move_insn (zero_reg, CONST0_RTX (<MODE>mode));
kono
parents: 67
diff changeset
1427 if (!BYTES_BIG_ENDIAN)
kono
parents: 67
diff changeset
1428 {
kono
parents: 67
diff changeset
1429 byteshift_val = 16 - byteshift_val;
kono
parents: 67
diff changeset
1430 op1 = zero_reg;
kono
parents: 67
diff changeset
1431 op2 = operands[1];
kono
parents: 67
diff changeset
1432 }
kono
parents: 67
diff changeset
1433 else
kono
parents: 67
diff changeset
1434 {
kono
parents: 67
diff changeset
1435 op1 = operands[1];
kono
parents: 67
diff changeset
1436 op2 = zero_reg;
kono
parents: 67
diff changeset
1437 }
kono
parents: 67
diff changeset
1438
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1439 if (TARGET_VSX && (byteshift_val & 0x3) == 0)
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1440 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1441 shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
111
kono
parents: 67
diff changeset
1442 insn = gen_vsx_xxsldwi_<mode> (operands[0], op1, op2, shift);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1443 }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1444 else
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1445 {
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1446 shift = gen_rtx_CONST_INT (QImode, byteshift_val);
111
kono
parents: 67
diff changeset
1447 insn = gen_altivec_vsldoi_<mode> (operands[0], op1, op2, shift);
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1448 }
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1449
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1450 emit_insn (insn);
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1451 DONE;
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1452 })
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1453
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1454 ;; Expanders for rotate each element in a vector
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1455 (define_expand "vrotl<mode>3"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1456 [(set (match_operand:VEC_I 0 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1457 (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1458 (match_operand:VEC_I 2 "vint_operand")))]
111
kono
parents: 67
diff changeset
1459 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1460 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1461
145
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1462 ;; Expanders for rotatert to make use of vrotl
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1463 (define_expand "vrotr<mode>3"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1464 [(set (match_operand:VEC_I 0 "vint_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1465 (rotatert:VEC_I (match_operand:VEC_I 1 "vint_operand")
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1466 (match_operand:VEC_I 2 "vint_operand")))]
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1467 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1468 {
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1469 rtx rot_count = gen_reg_rtx (<MODE>mode);
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1470 emit_insn (gen_neg<mode>2 (rot_count, operands[2]));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1471 emit_insn (gen_vrotl<mode>3 (operands[0], operands[1], rot_count));
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1472 DONE;
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1473 })
1830386684a0 gcc-9.2.0
anatofuz
parents: 131
diff changeset
1474
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1475 ;; Expanders for arithmetic shift left on each vector element
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1476 (define_expand "vashl<mode>3"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1477 [(set (match_operand:VEC_I 0 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1478 (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1479 (match_operand:VEC_I 2 "vint_operand")))]
111
kono
parents: 67
diff changeset
1480 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1481 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1482
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1483 ;; Expanders for logical shift right on each vector element
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1484 (define_expand "vlshr<mode>3"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1485 [(set (match_operand:VEC_I 0 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1486 (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1487 (match_operand:VEC_I 2 "vint_operand")))]
111
kono
parents: 67
diff changeset
1488 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1489 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1490
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1491 ;; Expanders for arithmetic shift right on each vector element
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1492 (define_expand "vashr<mode>3"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1493 [(set (match_operand:VEC_I 0 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1494 (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1495 (match_operand:VEC_I 2 "vint_operand")))]
111
kono
parents: 67
diff changeset
1496 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1497 "")
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1498
111
kono
parents: 67
diff changeset
1499 ;; Vector reduction expanders for VSX
kono
parents: 67
diff changeset
1500 ; The (VEC_reduc:...
kono
parents: 67
diff changeset
1501 ; (op1)
kono
parents: 67
diff changeset
1502 ; (unspec:... [(const_int 0)] UNSPEC_REDUC))
kono
parents: 67
diff changeset
1503 ;
kono
parents: 67
diff changeset
1504 ; is to allow us to use a code iterator, but not completely list all of the
kono
parents: 67
diff changeset
1505 ; vector rotates, etc. to prevent canonicalization
55
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1506
77e2b8dfacca update it from 4.4.3 to 4.5.0
ryoma <e075725@ie.u-ryukyu.ac.jp>
parents:
diff changeset
1507
111
kono
parents: 67
diff changeset
1508 (define_expand "reduc_<VEC_reduc:VEC_reduc_name>_scal_<VEC_F:mode>"
131
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1509 [(match_operand:<VEC_base> 0 "register_operand")
84e7813d76e9 gcc-8.2
mir3636
parents: 111
diff changeset
1510 (VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
111
kono
parents: 67
diff changeset
1511 (unspec:VEC_F [(const_int 0)] UNSPEC_REDUC))]
kono
parents: 67
diff changeset
1512 "VECTOR_UNIT_VSX_P (<VEC_F:MODE>mode)"
kono
parents: 67
diff changeset
1513 {
kono
parents: 67
diff changeset
1514 rtx vec = gen_reg_rtx (<VEC_F:MODE>mode);
kono
parents: 67
diff changeset
1515 rtx elt = BYTES_BIG_ENDIAN
kono
parents: 67
diff changeset
1516 ? gen_int_mode (GET_MODE_NUNITS (<VEC_F:MODE>mode) - 1, QImode)
kono
parents: 67
diff changeset
1517 : const0_rtx;
kono
parents: 67
diff changeset
1518 emit_insn (gen_vsx_reduc_<VEC_reduc:VEC_reduc_name>_<VEC_F:mode> (vec,
kono
parents: 67
diff changeset
1519 operand1));
kono
parents: 67
diff changeset
1520 emit_insn (gen_vsx_extract_<VEC_F:mode> (operand0, vec, elt));
kono
parents: 67
diff changeset
1521 DONE;
kono
parents: 67
diff changeset
1522 })