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1 ;; Scheduling description for Niagara.
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2 ;; Copyright (C) 2006-2020 Free Software Foundation, Inc.
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3 ;;
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4 ;; This file is part of GCC.
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5 ;;
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6 ;; GCC is free software; you can redistribute it and/or modify
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7 ;; it under the terms of the GNU General Public License as published by
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8 ;; the Free Software Foundation; either version 3, or (at your option)
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9 ;; any later version.
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10 ;;
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11 ;; GCC is distributed in the hope that it will be useful,
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12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 ;; GNU General Public License for more details.
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15 ;;
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16 ;; You should have received a copy of the GNU General Public License
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17 ;; along with GCC; see the file COPYING3. If not see
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18 ;; <http://www.gnu.org/licenses/>.
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19
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20 ;; Niagara is a single-issue processor.
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21
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22 (define_automaton "niagara_0")
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23
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24 (define_cpu_unit "niag_pipe" "niagara_0")
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25
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26 (define_insn_reservation "niag_5cycle" 5
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27 (and (eq_attr "cpu" "niagara")
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28 (eq_attr "type" "multi,flushw,iflush,trap"))
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29 "niag_pipe*5")
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30
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31 (define_insn_reservation "niag_4cycle" 4
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32 (and (eq_attr "cpu" "niagara")
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33 (eq_attr "type" "savew"))
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34 "niag_pipe*4")
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35
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36 /* Most basic operations are single-cycle. */
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37 (define_insn_reservation "niag_ialu" 1
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38 (and (eq_attr "cpu" "niagara")
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39 (eq_attr "type" "ialu,shift,compare,cmove"))
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40 "niag_pipe")
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41
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42 (define_insn_reservation "niag_imul" 11
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43 (and (eq_attr "cpu" "niagara")
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44 (eq_attr "type" "imul"))
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45 "niag_pipe*11")
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46
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47 (define_insn_reservation "niag_idiv" 72
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48 (and (eq_attr "cpu" "niagara")
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49 (eq_attr "type" "idiv"))
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50 "niag_pipe*72")
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51
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52 (define_insn_reservation "niag_branch" 3
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53 (and (eq_attr "cpu" "niagara")
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54 (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch"))
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55 "niag_pipe*3")
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56
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57 (define_insn_reservation "niag_3cycle_load" 3
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58 (and (eq_attr "cpu" "niagara")
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59 (eq_attr "type" "load"))
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60 "niag_pipe*3")
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61
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62 (define_insn_reservation "niag_9cycle_load" 9
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63 (and (eq_attr "cpu" "niagara")
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64 (eq_attr "type" "fpload"))
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65 "niag_pipe*9")
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66
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67 (define_insn_reservation "niag_1cycle_store" 1
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68 (and (eq_attr "cpu" "niagara")
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69 (eq_attr "type" "store"))
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70 "niag_pipe")
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71
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72 (define_insn_reservation "niag_8cycle_store" 8
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73 (and (eq_attr "cpu" "niagara")
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74 (eq_attr "type" "fpstore"))
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75 "niag_pipe*8")
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76
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77 /* Things incorrectly modelled here:
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78 * FPADD{s,d}: 26 cycles
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79 * FPSUB{s,d}: 26 cycles
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80 * FABSD: 26 cycles
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81 * F{s,d}TO{s,d}: 26 cycles
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82 * F{s,d}TO{i,x}: 26 cycles
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83 * FSMULD: 29 cycles
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84 */
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85 (define_insn_reservation "niag_fmov" 8
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86 (and (eq_attr "cpu" "niagara")
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87 (eq_attr "type" "fpmove,fpcmove,fpcrmove"))
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88 "niag_pipe*8")
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89
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90 (define_insn_reservation "niag_fpcmp" 26
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91 (and (eq_attr "cpu" "niagara")
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92 (eq_attr "type" "fpcmp"))
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93 "niag_pipe*26")
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94
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95 (define_insn_reservation "niag_fmult" 29
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96 (and (eq_attr "cpu" "niagara")
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97 (eq_attr "type" "fpmul"))
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98 "niag_pipe*29")
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99
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100 (define_insn_reservation "niag_fdivs" 54
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101 (and (eq_attr "cpu" "niagara")
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102 (eq_attr "type" "fpdivs"))
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103 "niag_pipe*54")
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104
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105 (define_insn_reservation "niag_fdivd" 83
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106 (and (eq_attr "cpu" "niagara")
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107 (eq_attr "type" "fpdivd"))
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108 "niag_pipe*83")
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109
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110 /* Things incorrectly modelled here:
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111 * FPADD{16,32}: 10 cycles
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112 * FPSUB{16,32}: 10 cycles
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113 * FALIGNDATA: 10 cycles
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114 */
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115 (define_insn_reservation "niag_vis" 8
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116 (and (eq_attr "cpu" "niagara")
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111
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117 (eq_attr "type" "fga,visl,viscmp,vismv,fgm_pack,fgm_mul,pdist,edge,edgen,gsr,array,bmask"))
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118 "niag_pipe*8")
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