|
111
|
1 /* Definitions for option handling for SPARC.
|
|
145
|
2 Copyright (C) 1996-2020 Free Software Foundation, Inc.
|
|
111
|
3
|
|
|
4 This file is part of GCC.
|
|
|
5
|
|
|
6 GCC is free software; you can redistribute it and/or modify
|
|
|
7 it under the terms of the GNU General Public License as published by
|
|
|
8 the Free Software Foundation; either version 3, or (at your option)
|
|
|
9 any later version.
|
|
|
10
|
|
|
11 GCC is distributed in the hope that it will be useful,
|
|
|
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
14 GNU General Public License for more details.
|
|
|
15
|
|
|
16 You should have received a copy of the GNU General Public License
|
|
|
17 along with GCC; see the file COPYING3. If not see
|
|
|
18 <http://www.gnu.org/licenses/>. */
|
|
|
19
|
|
|
20 #ifndef SPARC_OPTS_H
|
|
|
21 #define SPARC_OPTS_H
|
|
|
22
|
|
145
|
23 /* SPARC processor type.
|
|
111
|
24 These must match the values for the cpu attribute in sparc.md and
|
|
|
25 the table in sparc_option_override. */
|
|
145
|
26 enum sparc_processor_type {
|
|
111
|
27 PROCESSOR_V7,
|
|
|
28 PROCESSOR_CYPRESS,
|
|
|
29 PROCESSOR_V8,
|
|
|
30 PROCESSOR_SUPERSPARC,
|
|
|
31 PROCESSOR_HYPERSPARC,
|
|
|
32 PROCESSOR_LEON,
|
|
|
33 PROCESSOR_LEON3,
|
|
|
34 PROCESSOR_LEON3V7,
|
|
|
35 PROCESSOR_SPARCLITE,
|
|
|
36 PROCESSOR_F930,
|
|
|
37 PROCESSOR_F934,
|
|
|
38 PROCESSOR_SPARCLITE86X,
|
|
|
39 PROCESSOR_SPARCLET,
|
|
|
40 PROCESSOR_TSC701,
|
|
|
41 PROCESSOR_V9,
|
|
|
42 PROCESSOR_ULTRASPARC,
|
|
|
43 PROCESSOR_ULTRASPARC3,
|
|
|
44 PROCESSOR_NIAGARA,
|
|
|
45 PROCESSOR_NIAGARA2,
|
|
|
46 PROCESSOR_NIAGARA3,
|
|
|
47 PROCESSOR_NIAGARA4,
|
|
|
48 PROCESSOR_NIAGARA7,
|
|
|
49 PROCESSOR_M8,
|
|
|
50 PROCESSOR_NATIVE
|
|
|
51 };
|
|
|
52
|
|
145
|
53 /* SPARC-V9 code model type. See sparc.h for the full description. */
|
|
|
54 enum sparc_code_model_type {
|
|
|
55 CM_32, /* 32-bit address space. */
|
|
|
56 CM_MEDLOW, /* 32-bit address space. */
|
|
|
57 CM_MEDMID, /* 44-bit address space. */
|
|
|
58 CM_MEDANY, /* 64-bit address space. */
|
|
|
59 CM_EMBMEDANY /* 64-bit address space. */
|
|
|
60 };
|
|
|
61
|
|
|
62 /* SPARC memory model type. See Appendix D in the SPARC-V9 manual
|
|
|
63 for formal specification and Appendix J for more discussion. */
|
|
111
|
64 enum sparc_memory_model_type {
|
|
145
|
65 SMM_DEFAULT, /* Processor default. */
|
|
111
|
66 SMM_RMO, /* Relaxed Memory Order. */
|
|
|
67 SMM_PSO, /* Partial Store Order. */
|
|
|
68 SMM_TSO, /* Total Store Order. */
|
|
|
69 SMM_SC /* Sequential Consistency. */
|
|
|
70 };
|
|
|
71
|
|
|
72 #endif
|
