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111
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1 /* IR-agnostic target query functions relating to optabs
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145
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2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
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111
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3
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4 This file is part of GCC.
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5
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6 GCC is free software; you can redistribute it and/or modify it under
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7 the terms of the GNU General Public License as published by the Free
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8 Software Foundation; either version 3, or (at your option) any later
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9 version.
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10
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11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
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13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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14 for more details.
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15
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16 You should have received a copy of the GNU General Public License
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17 along with GCC; see the file COPYING3. If not see
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18 <http://www.gnu.org/licenses/>. */
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19
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20
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21 #include "config.h"
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22 #include "system.h"
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23 #include "coretypes.h"
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24 #include "target.h"
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25 #include "insn-codes.h"
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26 #include "optabs-query.h"
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27 #include "optabs-libfuncs.h"
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28 #include "insn-config.h"
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29 #include "rtl.h"
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30 #include "recog.h"
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131
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31 #include "vec-perm-indices.h"
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111
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32
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33 struct target_optabs default_target_optabs;
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34 struct target_optabs *this_fn_optabs = &default_target_optabs;
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35 #if SWITCHABLE_TARGET
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36 struct target_optabs *this_target_optabs = &default_target_optabs;
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37 #endif
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38
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39 /* Return the insn used to perform conversion OP from mode FROM_MODE
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40 to mode TO_MODE; return CODE_FOR_nothing if the target does not have
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41 such an insn, or if it is unsuitable for optimization type OPT_TYPE. */
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42
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43 insn_code
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44 convert_optab_handler (convert_optab optab, machine_mode to_mode,
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45 machine_mode from_mode, optimization_type opt_type)
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46 {
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47 insn_code icode = convert_optab_handler (optab, to_mode, from_mode);
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48 if (icode == CODE_FOR_nothing
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49 || !targetm.optab_supported_p (optab, to_mode, from_mode, opt_type))
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50 return CODE_FOR_nothing;
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51 return icode;
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52 }
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53
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54 /* Return the insn used to implement mode MODE of OP; return
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55 CODE_FOR_nothing if the target does not have such an insn,
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56 or if it is unsuitable for optimization type OPT_TYPE. */
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57
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58 insn_code
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59 direct_optab_handler (convert_optab optab, machine_mode mode,
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60 optimization_type opt_type)
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61 {
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62 insn_code icode = direct_optab_handler (optab, mode);
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63 if (icode == CODE_FOR_nothing
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64 || !targetm.optab_supported_p (optab, mode, mode, opt_type))
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65 return CODE_FOR_nothing;
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66 return icode;
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67 }
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68
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69 /* Enumerates the possible types of structure operand to an
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70 extraction_insn. */
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71 enum extraction_type { ET_unaligned_mem, ET_reg };
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72
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73 /* Check whether insv, extv or extzv pattern ICODE can be used for an
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74 insertion or extraction of type TYPE on a structure of mode MODE.
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75 Return true if so and fill in *INSN accordingly. STRUCT_OP is the
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76 operand number of the structure (the first sign_extract or zero_extract
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77 operand) and FIELD_OP is the operand number of the field (the other
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78 side of the set from the sign_extract or zero_extract). */
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79
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80 static bool
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81 get_traditional_extraction_insn (extraction_insn *insn,
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82 enum extraction_type type,
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83 machine_mode mode,
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84 enum insn_code icode,
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85 int struct_op, int field_op)
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86 {
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87 const struct insn_data_d *data = &insn_data[icode];
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88
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89 machine_mode struct_mode = data->operand[struct_op].mode;
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90 if (struct_mode == VOIDmode)
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91 struct_mode = word_mode;
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92 if (mode != struct_mode)
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93 return false;
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94
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95 machine_mode field_mode = data->operand[field_op].mode;
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96 if (field_mode == VOIDmode)
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97 field_mode = word_mode;
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98
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99 machine_mode pos_mode = data->operand[struct_op + 2].mode;
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100 if (pos_mode == VOIDmode)
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101 pos_mode = word_mode;
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102
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103 insn->icode = icode;
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104 insn->field_mode = as_a <scalar_int_mode> (field_mode);
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105 if (type == ET_unaligned_mem)
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106 insn->struct_mode = byte_mode;
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107 else if (struct_mode == BLKmode)
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108 insn->struct_mode = opt_scalar_int_mode ();
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109 else
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110 insn->struct_mode = as_a <scalar_int_mode> (struct_mode);
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111 insn->pos_mode = as_a <scalar_int_mode> (pos_mode);
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112 return true;
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113 }
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114
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115 /* Return true if an optab exists to perform an insertion or extraction
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116 of type TYPE in mode MODE. Describe the instruction in *INSN if so.
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117
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118 REG_OPTAB is the optab to use for register structures and
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119 MISALIGN_OPTAB is the optab to use for misaligned memory structures.
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120 POS_OP is the operand number of the bit position. */
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121
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122 static bool
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145
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123 get_optab_extraction_insn (class extraction_insn *insn,
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124 enum extraction_type type,
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125 machine_mode mode, direct_optab reg_optab,
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126 direct_optab misalign_optab, int pos_op)
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127 {
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128 direct_optab optab = (type == ET_unaligned_mem ? misalign_optab : reg_optab);
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129 enum insn_code icode = direct_optab_handler (optab, mode);
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130 if (icode == CODE_FOR_nothing)
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131 return false;
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132
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133 const struct insn_data_d *data = &insn_data[icode];
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134
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135 machine_mode pos_mode = data->operand[pos_op].mode;
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136 if (pos_mode == VOIDmode)
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137 pos_mode = word_mode;
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138
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139 insn->icode = icode;
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140 insn->field_mode = as_a <scalar_int_mode> (mode);
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141 if (type == ET_unaligned_mem)
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142 insn->struct_mode = opt_scalar_int_mode ();
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143 else
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144 insn->struct_mode = insn->field_mode;
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145 insn->pos_mode = as_a <scalar_int_mode> (pos_mode);
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146 return true;
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147 }
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148
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149 /* Return true if an instruction exists to perform an insertion or
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150 extraction (PATTERN says which) of type TYPE in mode MODE.
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151 Describe the instruction in *INSN if so. */
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152
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153 static bool
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154 get_extraction_insn (extraction_insn *insn,
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155 enum extraction_pattern pattern,
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156 enum extraction_type type,
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157 machine_mode mode)
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158 {
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159 switch (pattern)
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160 {
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161 case EP_insv:
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162 if (targetm.have_insv ()
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163 && get_traditional_extraction_insn (insn, type, mode,
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164 targetm.code_for_insv, 0, 3))
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165 return true;
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166 return get_optab_extraction_insn (insn, type, mode, insv_optab,
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167 insvmisalign_optab, 2);
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168
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169 case EP_extv:
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170 if (targetm.have_extv ()
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171 && get_traditional_extraction_insn (insn, type, mode,
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172 targetm.code_for_extv, 1, 0))
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173 return true;
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174 return get_optab_extraction_insn (insn, type, mode, extv_optab,
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175 extvmisalign_optab, 3);
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176
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177 case EP_extzv:
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178 if (targetm.have_extzv ()
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179 && get_traditional_extraction_insn (insn, type, mode,
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180 targetm.code_for_extzv, 1, 0))
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181 return true;
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182 return get_optab_extraction_insn (insn, type, mode, extzv_optab,
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183 extzvmisalign_optab, 3);
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184
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185 default:
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186 gcc_unreachable ();
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187 }
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188 }
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189
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190 /* Return true if an instruction exists to access a field of mode
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191 FIELDMODE in a structure that has STRUCT_BITS significant bits.
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192 Describe the "best" such instruction in *INSN if so. PATTERN and
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193 TYPE describe the type of insertion or extraction we want to perform.
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194
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195 For an insertion, the number of significant structure bits includes
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196 all bits of the target. For an extraction, it need only include the
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197 most significant bit of the field. Larger widths are acceptable
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198 in both cases. */
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199
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200 static bool
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201 get_best_extraction_insn (extraction_insn *insn,
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202 enum extraction_pattern pattern,
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203 enum extraction_type type,
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204 unsigned HOST_WIDE_INT struct_bits,
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205 machine_mode field_mode)
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206 {
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207 opt_scalar_int_mode mode_iter;
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208 FOR_EACH_MODE_FROM (mode_iter, smallest_int_mode_for_size (struct_bits))
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209 {
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210 scalar_int_mode mode = mode_iter.require ();
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211 if (get_extraction_insn (insn, pattern, type, mode))
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212 {
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213 FOR_EACH_MODE_FROM (mode_iter, mode)
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214 {
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215 mode = mode_iter.require ();
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131
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216 if (maybe_gt (GET_MODE_SIZE (mode), GET_MODE_SIZE (field_mode))
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111
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217 || TRULY_NOOP_TRUNCATION_MODES_P (insn->field_mode,
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218 field_mode))
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219 break;
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220 get_extraction_insn (insn, pattern, type, mode);
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221 }
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222 return true;
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223 }
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224 }
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225 return false;
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226 }
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227
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228 /* Return true if an instruction exists to access a field of mode
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229 FIELDMODE in a register structure that has STRUCT_BITS significant bits.
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230 Describe the "best" such instruction in *INSN if so. PATTERN describes
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231 the type of insertion or extraction we want to perform.
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232
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233 For an insertion, the number of significant structure bits includes
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234 all bits of the target. For an extraction, it need only include the
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235 most significant bit of the field. Larger widths are acceptable
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236 in both cases. */
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237
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238 bool
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239 get_best_reg_extraction_insn (extraction_insn *insn,
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240 enum extraction_pattern pattern,
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241 unsigned HOST_WIDE_INT struct_bits,
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242 machine_mode field_mode)
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243 {
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244 return get_best_extraction_insn (insn, pattern, ET_reg, struct_bits,
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245 field_mode);
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246 }
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247
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248 /* Return true if an instruction exists to access a field of BITSIZE
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249 bits starting BITNUM bits into a memory structure. Describe the
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250 "best" such instruction in *INSN if so. PATTERN describes the type
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251 of insertion or extraction we want to perform and FIELDMODE is the
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252 natural mode of the extracted field.
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253
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254 The instructions considered here only access bytes that overlap
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255 the bitfield; they do not touch any surrounding bytes. */
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256
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257 bool
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258 get_best_mem_extraction_insn (extraction_insn *insn,
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259 enum extraction_pattern pattern,
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260 HOST_WIDE_INT bitsize, HOST_WIDE_INT bitnum,
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261 machine_mode field_mode)
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262 {
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263 unsigned HOST_WIDE_INT struct_bits = (bitnum % BITS_PER_UNIT
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264 + bitsize
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265 + BITS_PER_UNIT - 1);
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266 struct_bits -= struct_bits % BITS_PER_UNIT;
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267 return get_best_extraction_insn (insn, pattern, ET_unaligned_mem,
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268 struct_bits, field_mode);
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269 }
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270
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271 /* Return the insn code used to extend FROM_MODE to TO_MODE.
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272 UNSIGNEDP specifies zero-extension instead of sign-extension. If
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273 no such operation exists, CODE_FOR_nothing will be returned. */
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274
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275 enum insn_code
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276 can_extend_p (machine_mode to_mode, machine_mode from_mode,
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277 int unsignedp)
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278 {
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279 if (unsignedp < 0 && targetm.have_ptr_extend ())
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280 return targetm.code_for_ptr_extend;
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281
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282 convert_optab tab = unsignedp ? zext_optab : sext_optab;
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283 return convert_optab_handler (tab, to_mode, from_mode);
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284 }
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285
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286 /* Return the insn code to convert fixed-point mode FIXMODE to floating-point
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287 mode FLTMODE, or CODE_FOR_nothing if no such instruction exists.
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288 UNSIGNEDP specifies whether FIXMODE is unsigned. */
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289
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290 enum insn_code
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291 can_float_p (machine_mode fltmode, machine_mode fixmode,
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292 int unsignedp)
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293 {
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294 convert_optab tab = unsignedp ? ufloat_optab : sfloat_optab;
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295 return convert_optab_handler (tab, fltmode, fixmode);
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296 }
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297
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298 /* Return the insn code to convert floating-point mode FLTMODE to fixed-point
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299 mode FIXMODE, or CODE_FOR_nothing if no such instruction exists.
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300 UNSIGNEDP specifies whether FIXMODE is unsigned.
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301
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302 On a successful return, set *TRUNCP_PTR to true if it is necessary to
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303 output an explicit FTRUNC before the instruction. */
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304
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305 enum insn_code
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306 can_fix_p (machine_mode fixmode, machine_mode fltmode,
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307 int unsignedp, bool *truncp_ptr)
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308 {
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309 convert_optab tab;
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310 enum insn_code icode;
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311
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312 tab = unsignedp ? ufixtrunc_optab : sfixtrunc_optab;
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313 icode = convert_optab_handler (tab, fixmode, fltmode);
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314 if (icode != CODE_FOR_nothing)
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315 {
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316 *truncp_ptr = false;
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317 return icode;
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318 }
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319
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320 /* FIXME: This requires a port to define both FIX and FTRUNC pattern
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321 for this to work. We need to rework the fix* and ftrunc* patterns
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322 and documentation. */
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323 tab = unsignedp ? ufix_optab : sfix_optab;
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324 icode = convert_optab_handler (tab, fixmode, fltmode);
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325 if (icode != CODE_FOR_nothing
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326 && optab_handler (ftrunc_optab, fltmode) != CODE_FOR_nothing)
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327 {
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328 *truncp_ptr = true;
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329 return icode;
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330 }
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331
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332 return CODE_FOR_nothing;
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333 }
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334
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335 /* Return nonzero if a conditional move of mode MODE is supported.
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336
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337 This function is for combine so it can tell whether an insn that looks
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338 like a conditional move is actually supported by the hardware. If we
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339 guess wrong we lose a bit on optimization, but that's it. */
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340 /* ??? sparc64 supports conditionally moving integers values based on fp
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341 comparisons, and vice versa. How do we handle them? */
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342
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343 bool
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344 can_conditionally_move_p (machine_mode mode)
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345 {
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346 return direct_optab_handler (movcc_optab, mode) != CODE_FOR_nothing;
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347 }
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348
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131
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349 /* If a target doesn't implement a permute on a vector with multibyte
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350 elements, we can try to do the same permute on byte elements.
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351 If this makes sense for vector mode MODE then return the appropriate
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352 byte vector mode. */
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353
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354 opt_machine_mode
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355 qimode_for_vec_perm (machine_mode mode)
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356 {
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145
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357 if (GET_MODE_INNER (mode) != QImode)
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358 return related_vector_mode (mode, QImode, GET_MODE_SIZE (mode));
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131
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359 return opt_machine_mode ();
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360 }
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361
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362 /* Return true if selector SEL can be represented in the integer
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363 equivalent of vector mode MODE. */
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111
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364
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365 bool
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131
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366 selector_fits_mode_p (machine_mode mode, const vec_perm_indices &sel)
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111
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367 {
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131
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368 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (GET_MODE_INNER (mode));
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369 return (mask == HOST_WIDE_INT_M1U
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370 || sel.all_in_range_p (0, mask + 1));
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371 }
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111
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372
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131
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373 /* Return true if VEC_PERM_EXPRs with variable selector operands can be
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374 expanded using SIMD extensions of the CPU. MODE is the mode of the
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375 vectors being permuted. */
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376
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377 bool
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378 can_vec_perm_var_p (machine_mode mode)
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379 {
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111
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380 /* If the target doesn't implement a vector mode for the vector type,
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381 then no operations are supported. */
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382 if (!VECTOR_MODE_P (mode))
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383 return false;
|
|
|
384
|
|
|
385 if (direct_optab_handler (vec_perm_optab, mode) != CODE_FOR_nothing)
|
|
|
386 return true;
|
|
|
387
|
|
|
388 /* We allow fallback to a QI vector mode, and adjust the mask. */
|
|
131
|
389 machine_mode qimode;
|
|
|
390 if (!qimode_for_vec_perm (mode).exists (&qimode)
|
|
|
391 || maybe_gt (GET_MODE_NUNITS (qimode), GET_MODE_MASK (QImode) + 1))
|
|
111
|
392 return false;
|
|
|
393
|
|
|
394 if (direct_optab_handler (vec_perm_optab, qimode) == CODE_FOR_nothing)
|
|
|
395 return false;
|
|
|
396
|
|
|
397 /* In order to support the lowering of variable permutations,
|
|
|
398 we need to support shifts and adds. */
|
|
131
|
399 if (GET_MODE_UNIT_SIZE (mode) > 2
|
|
|
400 && optab_handler (ashl_optab, mode) == CODE_FOR_nothing
|
|
|
401 && optab_handler (vashl_optab, mode) == CODE_FOR_nothing)
|
|
|
402 return false;
|
|
|
403 if (optab_handler (add_optab, qimode) == CODE_FOR_nothing)
|
|
|
404 return false;
|
|
111
|
405
|
|
|
406 return true;
|
|
|
407 }
|
|
|
408
|
|
131
|
409 /* Return true if the target directly supports VEC_PERM_EXPRs on vectors
|
|
|
410 of mode MODE using the selector SEL. ALLOW_VARIABLE_P is true if it
|
|
|
411 is acceptable to force the selector into a register and use a variable
|
|
|
412 permute (if the target supports that).
|
|
111
|
413
|
|
131
|
414 Note that additional permutations representing whole-vector shifts may
|
|
145
|
415 also be handled via the vec_shr or vec_shl optab, but only where the
|
|
|
416 second input vector is entirely constant zeroes; this case is not dealt
|
|
|
417 with here. */
|
|
131
|
418
|
|
|
419 bool
|
|
|
420 can_vec_perm_const_p (machine_mode mode, const vec_perm_indices &sel,
|
|
|
421 bool allow_variable_p)
|
|
111
|
422 {
|
|
131
|
423 /* If the target doesn't implement a vector mode for the vector type,
|
|
|
424 then no operations are supported. */
|
|
|
425 if (!VECTOR_MODE_P (mode))
|
|
|
426 return false;
|
|
|
427
|
|
|
428 /* It's probably cheaper to test for the variable case first. */
|
|
|
429 if (allow_variable_p && selector_fits_mode_p (mode, sel))
|
|
111
|
430 {
|
|
131
|
431 if (direct_optab_handler (vec_perm_optab, mode) != CODE_FOR_nothing)
|
|
|
432 return true;
|
|
|
433
|
|
|
434 /* Unlike can_vec_perm_var_p, we don't need to test for optabs
|
|
|
435 related computing the QImode selector, since that happens at
|
|
|
436 compile time. */
|
|
|
437 machine_mode qimode;
|
|
|
438 if (qimode_for_vec_perm (mode).exists (&qimode))
|
|
|
439 {
|
|
|
440 vec_perm_indices qimode_indices;
|
|
|
441 qimode_indices.new_expanded_vector (sel, GET_MODE_UNIT_SIZE (mode));
|
|
|
442 if (selector_fits_mode_p (qimode, qimode_indices)
|
|
|
443 && (direct_optab_handler (vec_perm_optab, qimode)
|
|
|
444 != CODE_FOR_nothing))
|
|
|
445 return true;
|
|
|
446 }
|
|
111
|
447 }
|
|
131
|
448
|
|
|
449 if (targetm.vectorize.vec_perm_const != NULL)
|
|
|
450 {
|
|
|
451 if (targetm.vectorize.vec_perm_const (mode, NULL_RTX, NULL_RTX,
|
|
|
452 NULL_RTX, sel))
|
|
|
453 return true;
|
|
|
454
|
|
|
455 /* ??? For completeness, we ought to check the QImode version of
|
|
|
456 vec_perm_const_optab. But all users of this implicit lowering
|
|
|
457 feature implement the variable vec_perm_optab, and the ia64
|
|
|
458 port specifically doesn't want us to lower V2SF operations
|
|
|
459 into integer operations. */
|
|
|
460 }
|
|
|
461
|
|
|
462 return false;
|
|
111
|
463 }
|
|
|
464
|
|
|
465 /* Find a widening optab even if it doesn't widen as much as we want.
|
|
|
466 E.g. if from_mode is HImode, and to_mode is DImode, and there is no
|
|
131
|
467 direct HI->SI insn, then return SI->DI, if that exists. */
|
|
111
|
468
|
|
|
469 enum insn_code
|
|
|
470 find_widening_optab_handler_and_mode (optab op, machine_mode to_mode,
|
|
|
471 machine_mode from_mode,
|
|
|
472 machine_mode *found_mode)
|
|
|
473 {
|
|
131
|
474 machine_mode limit_mode = to_mode;
|
|
|
475 if (is_a <scalar_int_mode> (from_mode))
|
|
111
|
476 {
|
|
131
|
477 gcc_checking_assert (is_a <scalar_int_mode> (to_mode)
|
|
|
478 && known_lt (GET_MODE_PRECISION (from_mode),
|
|
|
479 GET_MODE_PRECISION (to_mode)));
|
|
|
480 /* The modes after FROM_MODE are all MODE_INT, so the only
|
|
|
481 MODE_PARTIAL_INT mode we consider is FROM_MODE itself.
|
|
|
482 If LIMIT_MODE is MODE_PARTIAL_INT, stop at the containing
|
|
|
483 MODE_INT. */
|
|
|
484 if (GET_MODE_CLASS (limit_mode) == MODE_PARTIAL_INT)
|
|
|
485 limit_mode = GET_MODE_WIDER_MODE (limit_mode).require ();
|
|
|
486 }
|
|
|
487 else
|
|
|
488 gcc_checking_assert (GET_MODE_CLASS (from_mode) == GET_MODE_CLASS (to_mode)
|
|
|
489 && from_mode < to_mode);
|
|
|
490 FOR_EACH_MODE (from_mode, from_mode, limit_mode)
|
|
|
491 {
|
|
|
492 enum insn_code handler = convert_optab_handler (op, to_mode, from_mode);
|
|
111
|
493
|
|
|
494 if (handler != CODE_FOR_nothing)
|
|
|
495 {
|
|
|
496 if (found_mode)
|
|
|
497 *found_mode = from_mode;
|
|
|
498 return handler;
|
|
|
499 }
|
|
|
500 }
|
|
|
501
|
|
|
502 return CODE_FOR_nothing;
|
|
|
503 }
|
|
|
504
|
|
|
505 /* Return non-zero if a highpart multiply is supported of can be synthisized.
|
|
|
506 For the benefit of expand_mult_highpart, the return value is 1 for direct,
|
|
|
507 2 for even/odd widening, and 3 for hi/lo widening. */
|
|
|
508
|
|
|
509 int
|
|
|
510 can_mult_highpart_p (machine_mode mode, bool uns_p)
|
|
|
511 {
|
|
|
512 optab op;
|
|
|
513
|
|
|
514 op = uns_p ? umul_highpart_optab : smul_highpart_optab;
|
|
|
515 if (optab_handler (op, mode) != CODE_FOR_nothing)
|
|
|
516 return 1;
|
|
|
517
|
|
|
518 /* If the mode is an integral vector, synth from widening operations. */
|
|
|
519 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
|
|
|
520 return 0;
|
|
|
521
|
|
131
|
522 poly_int64 nunits = GET_MODE_NUNITS (mode);
|
|
111
|
523
|
|
|
524 op = uns_p ? vec_widen_umult_even_optab : vec_widen_smult_even_optab;
|
|
|
525 if (optab_handler (op, mode) != CODE_FOR_nothing)
|
|
|
526 {
|
|
|
527 op = uns_p ? vec_widen_umult_odd_optab : vec_widen_smult_odd_optab;
|
|
|
528 if (optab_handler (op, mode) != CODE_FOR_nothing)
|
|
|
529 {
|
|
131
|
530 /* The encoding has 2 interleaved stepped patterns. */
|
|
|
531 vec_perm_builder sel (nunits, 2, 3);
|
|
|
532 for (unsigned int i = 0; i < 6; ++i)
|
|
111
|
533 sel.quick_push (!BYTES_BIG_ENDIAN
|
|
|
534 + (i & ~1)
|
|
|
535 + ((i & 1) ? nunits : 0));
|
|
131
|
536 vec_perm_indices indices (sel, 2, nunits);
|
|
|
537 if (can_vec_perm_const_p (mode, indices))
|
|
111
|
538 return 2;
|
|
|
539 }
|
|
|
540 }
|
|
|
541
|
|
|
542 op = uns_p ? vec_widen_umult_hi_optab : vec_widen_smult_hi_optab;
|
|
|
543 if (optab_handler (op, mode) != CODE_FOR_nothing)
|
|
|
544 {
|
|
|
545 op = uns_p ? vec_widen_umult_lo_optab : vec_widen_smult_lo_optab;
|
|
|
546 if (optab_handler (op, mode) != CODE_FOR_nothing)
|
|
|
547 {
|
|
131
|
548 /* The encoding has a single stepped pattern. */
|
|
|
549 vec_perm_builder sel (nunits, 1, 3);
|
|
|
550 for (unsigned int i = 0; i < 3; ++i)
|
|
111
|
551 sel.quick_push (2 * i + (BYTES_BIG_ENDIAN ? 0 : 1));
|
|
131
|
552 vec_perm_indices indices (sel, 2, nunits);
|
|
|
553 if (can_vec_perm_const_p (mode, indices))
|
|
111
|
554 return 3;
|
|
|
555 }
|
|
|
556 }
|
|
|
557
|
|
|
558 return 0;
|
|
|
559 }
|
|
|
560
|
|
|
561 /* Return true if target supports vector masked load/store for mode. */
|
|
|
562
|
|
|
563 bool
|
|
|
564 can_vec_mask_load_store_p (machine_mode mode,
|
|
|
565 machine_mode mask_mode,
|
|
|
566 bool is_load)
|
|
|
567 {
|
|
|
568 optab op = is_load ? maskload_optab : maskstore_optab;
|
|
|
569 machine_mode vmode;
|
|
|
570
|
|
|
571 /* If mode is vector mode, check it directly. */
|
|
|
572 if (VECTOR_MODE_P (mode))
|
|
|
573 return convert_optab_handler (op, mode, mask_mode) != CODE_FOR_nothing;
|
|
|
574
|
|
|
575 /* Otherwise, return true if there is some vector mode with
|
|
|
576 the mask load/store supported. */
|
|
|
577
|
|
|
578 /* See if there is any chance the mask load or store might be
|
|
|
579 vectorized. If not, punt. */
|
|
|
580 scalar_mode smode;
|
|
|
581 if (!is_a <scalar_mode> (mode, &smode))
|
|
|
582 return false;
|
|
|
583
|
|
|
584 vmode = targetm.vectorize.preferred_simd_mode (smode);
|
|
|
585 if (!VECTOR_MODE_P (vmode))
|
|
|
586 return false;
|
|
|
587
|
|
145
|
588 if (targetm.vectorize.get_mask_mode (vmode).exists (&mask_mode)
|
|
111
|
589 && convert_optab_handler (op, vmode, mask_mode) != CODE_FOR_nothing)
|
|
|
590 return true;
|
|
|
591
|
|
145
|
592 auto_vector_modes vector_modes;
|
|
|
593 targetm.vectorize.autovectorize_vector_modes (&vector_modes, true);
|
|
|
594 for (unsigned int i = 0; i < vector_modes.length (); ++i)
|
|
111
|
595 {
|
|
145
|
596 poly_uint64 cur = GET_MODE_SIZE (vector_modes[i]);
|
|
131
|
597 poly_uint64 nunits;
|
|
|
598 if (!multiple_p (cur, GET_MODE_SIZE (smode), &nunits))
|
|
111
|
599 continue;
|
|
|
600 if (mode_for_vector (smode, nunits).exists (&vmode)
|
|
|
601 && VECTOR_MODE_P (vmode)
|
|
145
|
602 && targetm.vectorize.get_mask_mode (vmode).exists (&mask_mode)
|
|
111
|
603 && convert_optab_handler (op, vmode, mask_mode) != CODE_FOR_nothing)
|
|
|
604 return true;
|
|
|
605 }
|
|
|
606 return false;
|
|
|
607 }
|
|
|
608
|
|
|
609 /* Return true if there is a compare_and_swap pattern. */
|
|
|
610
|
|
|
611 bool
|
|
|
612 can_compare_and_swap_p (machine_mode mode, bool allow_libcall)
|
|
|
613 {
|
|
|
614 enum insn_code icode;
|
|
|
615
|
|
|
616 /* Check for __atomic_compare_and_swap. */
|
|
|
617 icode = direct_optab_handler (atomic_compare_and_swap_optab, mode);
|
|
|
618 if (icode != CODE_FOR_nothing)
|
|
|
619 return true;
|
|
|
620
|
|
|
621 /* Check for __sync_compare_and_swap. */
|
|
|
622 icode = optab_handler (sync_compare_and_swap_optab, mode);
|
|
|
623 if (icode != CODE_FOR_nothing)
|
|
|
624 return true;
|
|
|
625 if (allow_libcall && optab_libfunc (sync_compare_and_swap_optab, mode))
|
|
|
626 return true;
|
|
|
627
|
|
|
628 /* No inline compare and swap. */
|
|
|
629 return false;
|
|
|
630 }
|
|
|
631
|
|
|
632 /* Return true if an atomic exchange can be performed. */
|
|
|
633
|
|
|
634 bool
|
|
|
635 can_atomic_exchange_p (machine_mode mode, bool allow_libcall)
|
|
|
636 {
|
|
|
637 enum insn_code icode;
|
|
|
638
|
|
|
639 /* Check for __atomic_exchange. */
|
|
|
640 icode = direct_optab_handler (atomic_exchange_optab, mode);
|
|
|
641 if (icode != CODE_FOR_nothing)
|
|
|
642 return true;
|
|
|
643
|
|
|
644 /* Don't check __sync_test_and_set, as on some platforms that
|
|
|
645 has reduced functionality. Targets that really do support
|
|
|
646 a proper exchange should simply be updated to the __atomics. */
|
|
|
647
|
|
|
648 return can_compare_and_swap_p (mode, allow_libcall);
|
|
|
649 }
|
|
|
650
|
|
|
651 /* Return true if an atomic load can be performed without falling back to
|
|
|
652 a compare-and-swap. */
|
|
|
653
|
|
|
654 bool
|
|
|
655 can_atomic_load_p (machine_mode mode)
|
|
|
656 {
|
|
|
657 enum insn_code icode;
|
|
|
658
|
|
|
659 /* Does the target supports the load directly? */
|
|
|
660 icode = direct_optab_handler (atomic_load_optab, mode);
|
|
|
661 if (icode != CODE_FOR_nothing)
|
|
|
662 return true;
|
|
|
663
|
|
|
664 /* If the size of the object is greater than word size on this target,
|
|
|
665 then we assume that a load will not be atomic. Also see
|
|
|
666 expand_atomic_load. */
|
|
131
|
667 return known_le (GET_MODE_PRECISION (mode), BITS_PER_WORD);
|
|
111
|
668 }
|
|
|
669
|
|
|
670 /* Determine whether "1 << x" is relatively cheap in word_mode. */
|
|
|
671
|
|
|
672 bool
|
|
|
673 lshift_cheap_p (bool speed_p)
|
|
|
674 {
|
|
|
675 /* FIXME: This should be made target dependent via this "this_target"
|
|
|
676 mechanism, similar to e.g. can_copy_init_p in gcse.c. */
|
|
|
677 static bool init[2] = { false, false };
|
|
|
678 static bool cheap[2] = { true, true };
|
|
|
679
|
|
|
680 /* If the targer has no lshift in word_mode, the operation will most
|
|
|
681 probably not be cheap. ??? Does GCC even work for such targets? */
|
|
|
682 if (optab_handler (ashl_optab, word_mode) == CODE_FOR_nothing)
|
|
|
683 return false;
|
|
|
684
|
|
|
685 if (!init[speed_p])
|
|
|
686 {
|
|
|
687 rtx reg = gen_raw_REG (word_mode, 10000);
|
|
|
688 int cost = set_src_cost (gen_rtx_ASHIFT (word_mode, const1_rtx, reg),
|
|
|
689 word_mode, speed_p);
|
|
|
690 cheap[speed_p] = cost < COSTS_N_INSNS (3);
|
|
|
691 init[speed_p] = true;
|
|
|
692 }
|
|
|
693
|
|
|
694 return cheap[speed_p];
|
|
|
695 }
|
|
131
|
696
|
|
145
|
697 /* Return true if vector conversion optab OP supports at least one mode,
|
|
|
698 given that the second mode is always an integer vector. */
|
|
131
|
699
|
|
|
700 static bool
|
|
145
|
701 supports_vec_convert_optab_p (optab op)
|
|
131
|
702 {
|
|
|
703 for (int i = 0; i < NUM_MACHINE_MODES; ++i)
|
|
145
|
704 if (VECTOR_MODE_P ((machine_mode) i))
|
|
|
705 for (int j = MIN_MODE_VECTOR_INT; j < MAX_MODE_VECTOR_INT; ++j)
|
|
|
706 if (convert_optab_handler (op, (machine_mode) i,
|
|
|
707 (machine_mode) j) != CODE_FOR_nothing)
|
|
|
708 return true;
|
|
131
|
709
|
|
|
710 return false;
|
|
|
711 }
|
|
|
712
|
|
|
713 /* Return true if vec_gather_load is available for at least one vector
|
|
|
714 mode. */
|
|
|
715
|
|
|
716 bool
|
|
|
717 supports_vec_gather_load_p ()
|
|
|
718 {
|
|
|
719 if (this_fn_optabs->supports_vec_gather_load_cached)
|
|
|
720 return this_fn_optabs->supports_vec_gather_load;
|
|
|
721
|
|
|
722 this_fn_optabs->supports_vec_gather_load_cached = true;
|
|
|
723
|
|
|
724 this_fn_optabs->supports_vec_gather_load
|
|
145
|
725 = supports_vec_convert_optab_p (gather_load_optab);
|
|
131
|
726
|
|
|
727 return this_fn_optabs->supports_vec_gather_load;
|
|
|
728 }
|
|
|
729
|
|
|
730 /* Return true if vec_scatter_store is available for at least one vector
|
|
|
731 mode. */
|
|
|
732
|
|
|
733 bool
|
|
|
734 supports_vec_scatter_store_p ()
|
|
|
735 {
|
|
|
736 if (this_fn_optabs->supports_vec_scatter_store_cached)
|
|
|
737 return this_fn_optabs->supports_vec_scatter_store;
|
|
|
738
|
|
|
739 this_fn_optabs->supports_vec_scatter_store_cached = true;
|
|
|
740
|
|
|
741 this_fn_optabs->supports_vec_scatter_store
|
|
145
|
742 = supports_vec_convert_optab_p (scatter_store_optab);
|
|
131
|
743
|
|
|
744 return this_fn_optabs->supports_vec_scatter_store;
|
|
|
745 }
|
|
|
746
|
