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1 /* Target instruction definitions.
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2 Copyright (C) 2015-2020 Free Software Foundation, Inc.
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3
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4 This program is free software; you can redistribute it and/or modify it
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5 under the terms of the GNU General Public License as published by the
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6 Free Software Foundation; either version 3, or (at your option) any
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7 later version.
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8
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9 This program is distributed in the hope that it will be useful,
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10 but WITHOUT ANY WARRANTY; without even the implied warranty of
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11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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12 GNU General Public License for more details.
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13
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14 You should have received a copy of the GNU General Public License
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15 along with this program; see the file COPYING3. If not see
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16 <http://www.gnu.org/licenses/>. */
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17
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18 /* This file has one entry for each public pattern name that the target
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19 can provide. It is only used if no distinction between operand modes
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20 is necessary. If separate patterns are needed for different modes
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21 (so as to distinguish addition of QImode values from addition of
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22 HImode values, for example) then an optab should be used instead.
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23
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24 Each entry has the form:
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25
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26 DEF_TARGET_INSN (name, prototype)
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27
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28 where NAME is the name of the pattern and PROTOTYPE is its C prototype.
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29 The prototype should use parameter names of the form "x0", "x1", etc.
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30 for the operands that the .md pattern is required to have, followed by
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31 parameter names of the form "optN" for operands that the .md pattern
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32 may choose to ignore. Patterns that never take operands should have
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33 a prototype "(void)".
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34
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35 Pattern names should be documented in md.texi rather than here. */
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36 DEF_TARGET_INSN (allocate_stack, (rtx x0, rtx x1))
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37 DEF_TARGET_INSN (atomic_test_and_set, (rtx x0, rtx x1, rtx x2))
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38 DEF_TARGET_INSN (builtin_longjmp, (rtx x0))
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39 DEF_TARGET_INSN (builtin_setjmp_receiver, (rtx x0))
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40 DEF_TARGET_INSN (builtin_setjmp_setup, (rtx x0))
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41 DEF_TARGET_INSN (canonicalize_funcptr_for_compare, (rtx x0, rtx x1))
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42 DEF_TARGET_INSN (call, (rtx x0, rtx opt1, rtx opt2, rtx opt3))
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43 DEF_TARGET_INSN (call_pop, (rtx x0, rtx opt1, rtx opt2, rtx opt3))
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44 DEF_TARGET_INSN (call_value, (rtx x0, rtx x1, rtx opt2, rtx opt3, rtx opt4))
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45 DEF_TARGET_INSN (call_value_pop, (rtx x0, rtx x1, rtx opt2, rtx opt3,
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46 rtx opt4))
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47 DEF_TARGET_INSN (casesi, (rtx x0, rtx x1, rtx x2, rtx x3, rtx x4))
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48 DEF_TARGET_INSN (check_stack, (rtx x0))
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49 DEF_TARGET_INSN (clear_cache, (rtx x0, rtx x1))
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50 DEF_TARGET_INSN (doloop_begin, (rtx x0, rtx x1))
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51 DEF_TARGET_INSN (doloop_end, (rtx x0, rtx x1))
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52 DEF_TARGET_INSN (eh_return, (rtx x0))
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53 DEF_TARGET_INSN (epilogue, (void))
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54 DEF_TARGET_INSN (exception_receiver, (void))
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55 DEF_TARGET_INSN (extv, (rtx x0, rtx x1, rtx x2, rtx x3))
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56 DEF_TARGET_INSN (extzv, (rtx x0, rtx x1, rtx x2, rtx x3))
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57 DEF_TARGET_INSN (indirect_jump, (rtx x0))
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58 DEF_TARGET_INSN (insv, (rtx x0, rtx x1, rtx x2, rtx x3))
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59 DEF_TARGET_INSN (jump, (rtx x0))
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60 DEF_TARGET_INSN (load_multiple, (rtx x0, rtx x1, rtx x2))
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61 DEF_TARGET_INSN (mem_thread_fence, (rtx x0))
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62 DEF_TARGET_INSN (memory_barrier, (void))
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63 DEF_TARGET_INSN (memory_blockage, (void))
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64 DEF_TARGET_INSN (movstr, (rtx x0, rtx x1, rtx x2))
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65 DEF_TARGET_INSN (nonlocal_goto, (rtx x0, rtx x1, rtx x2, rtx x3))
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66 DEF_TARGET_INSN (nonlocal_goto_receiver, (void))
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67 DEF_TARGET_INSN (oacc_dim_pos, (rtx x0, rtx x1))
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68 DEF_TARGET_INSN (oacc_dim_size, (rtx x0, rtx x1))
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69 DEF_TARGET_INSN (oacc_fork, (rtx x0, rtx x1, rtx x2))
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70 DEF_TARGET_INSN (oacc_join, (rtx x0, rtx x1, rtx x2))
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71 DEF_TARGET_INSN (omp_simt_enter, (rtx x0, rtx x1, rtx x2))
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72 DEF_TARGET_INSN (omp_simt_exit, (rtx x0))
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73 DEF_TARGET_INSN (omp_simt_lane, (rtx x0))
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74 DEF_TARGET_INSN (omp_simt_last_lane, (rtx x0, rtx x1))
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75 DEF_TARGET_INSN (omp_simt_ordered, (rtx x0, rtx x1))
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76 DEF_TARGET_INSN (omp_simt_vote_any, (rtx x0, rtx x1))
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77 DEF_TARGET_INSN (omp_simt_xchg_bfly, (rtx x0, rtx x1, rtx x2))
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78 DEF_TARGET_INSN (omp_simt_xchg_idx, (rtx x0, rtx x1, rtx x2))
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79 DEF_TARGET_INSN (prefetch, (rtx x0, rtx x1, rtx x2))
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80 DEF_TARGET_INSN (probe_stack, (rtx x0))
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81 DEF_TARGET_INSN (probe_stack_address, (rtx x0))
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82 DEF_TARGET_INSN (prologue, (void))
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83 DEF_TARGET_INSN (ptr_extend, (rtx x0, rtx x1))
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84 DEF_TARGET_INSN (reload_load_address, (rtx x0, rtx x1))
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85 DEF_TARGET_INSN (restore_stack_block, (rtx x0, rtx x1))
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86 DEF_TARGET_INSN (restore_stack_function, (rtx x0, rtx x1))
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87 DEF_TARGET_INSN (restore_stack_nonlocal, (rtx x0, rtx x1))
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88 DEF_TARGET_INSN (return, (void))
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89 DEF_TARGET_INSN (save_stack_block, (rtx x0, rtx x1))
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90 DEF_TARGET_INSN (save_stack_function, (rtx x0, rtx x1))
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91 DEF_TARGET_INSN (save_stack_nonlocal, (rtx x0, rtx x1))
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92 DEF_TARGET_INSN (sibcall, (rtx x0, rtx opt1, rtx opt2, rtx opt3))
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93 DEF_TARGET_INSN (sibcall_epilogue, (void))
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94 DEF_TARGET_INSN (sibcall_value, (rtx x0, rtx x1, rtx opt2, rtx opt3,
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95 rtx opt4))
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96 DEF_TARGET_INSN (simple_return, (void))
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97 DEF_TARGET_INSN (split_stack_prologue, (void))
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98 DEF_TARGET_INSN (split_stack_space_check, (rtx x0, rtx x1))
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99 DEF_TARGET_INSN (stack_protect_combined_set, (rtx x0, rtx x1))
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100 DEF_TARGET_INSN (stack_protect_set, (rtx x0, rtx x1))
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101 DEF_TARGET_INSN (stack_protect_combined_test, (rtx x0, rtx x1, rtx x2))
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102 DEF_TARGET_INSN (stack_protect_test, (rtx x0, rtx x1, rtx x2))
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103 DEF_TARGET_INSN (store_multiple, (rtx x0, rtx x1, rtx x2))
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104 DEF_TARGET_INSN (tablejump, (rtx x0, rtx x1))
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105 DEF_TARGET_INSN (trap, (void))
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106 DEF_TARGET_INSN (unique, (void))
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107 DEF_TARGET_INSN (untyped_call, (rtx x0, rtx x1, rtx x2))
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108 DEF_TARGET_INSN (untyped_return, (rtx x0, rtx x1))
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