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1 /* Copyright (C) 2009-2020 Free Software Foundation, Inc.
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111
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2 Contributed by ARM Ltd.
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3
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4 This file is free software; you can redistribute it and/or modify it
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5 under the terms of the GNU General Public License as published by the
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6 Free Software Foundation; either version 3, or (at your option) any
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7 later version.
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8
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9 This file is distributed in the hope that it will be useful, but
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10 WITHOUT ANY WARRANTY; without even the implied warranty of
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11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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12 General Public License for more details.
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13
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14 Under Section 7 of GPL version 3, you are granted additional
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15 permissions described in the GCC Runtime Library Exception, version
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16 3.1, as published by the Free Software Foundation.
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17
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18 You should have received a copy of the GNU General Public License and
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19 a copy of the GCC Runtime Library Exception along with this program;
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20 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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21 <http://www.gnu.org/licenses/>. */
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22
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23 /* Always include AArch64 unwinder header file. */
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24 #include "config/aarch64/aarch64-unwind.h"
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25
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26 #ifndef inhibit_libc
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27
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28 #include <signal.h>
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29 #include <sys/ucontext.h>
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30
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31
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32 /* Since insns are always stored LE, on a BE system the opcodes will
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33 be loaded byte-reversed. Therefore, define two sets of opcodes,
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34 one for LE and one for BE. */
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35
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36 #if __AARCH64EB__
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37 #define MOVZ_X8_8B 0x681180d2
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38 #define SVC_0 0x010000d4
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39 #else
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40 #define MOVZ_X8_8B 0xd2801168
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41 #define SVC_0 0xd4000001
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42 #endif
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43
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44 #define MD_FALLBACK_FRAME_STATE_FOR aarch64_fallback_frame_state
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45
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46 static _Unwind_Reason_Code
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47 aarch64_fallback_frame_state (struct _Unwind_Context *context,
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48 _Unwind_FrameState * fs)
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49 {
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50 /* The kernel creates an rt_sigframe on the stack immediately prior
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51 to delivering a signal.
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52
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53 This structure must have the same shape as the linux kernel
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54 equivalent. */
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55 struct rt_sigframe
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56 {
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57 siginfo_t info;
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58 ucontext_t uc;
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59 };
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60
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61 struct rt_sigframe *rt_;
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62 _Unwind_Ptr new_cfa;
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63 unsigned *pc = context->ra;
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64 struct sigcontext *sc;
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65 struct _aarch64_ctx *extension_marker;
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66 int i;
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67
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68 /* A signal frame will have a return address pointing to
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69 __default_sa_restorer. This code is hardwired as:
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70
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71 0xd2801168 movz x8, #0x8b
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72 0xd4000001 svc 0x0
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73 */
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74 if (pc[0] != MOVZ_X8_8B || pc[1] != SVC_0)
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75 {
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76 return _URC_END_OF_STACK;
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77 }
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78
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79 rt_ = context->cfa;
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80 sc = &rt_->uc.uc_mcontext;
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81
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82 /* This define duplicates the definition in aarch64.md */
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83 #define SP_REGNUM 31
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84
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85 new_cfa = (_Unwind_Ptr) sc;
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86 fs->regs.cfa_how = CFA_REG_OFFSET;
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87 fs->regs.cfa_reg = __LIBGCC_STACK_POINTER_REGNUM__;
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88 fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa;
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89
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90 for (i = 0; i < AARCH64_DWARF_NUMBER_R; i++)
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91 {
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92 fs->regs.reg[AARCH64_DWARF_R0 + i].how = REG_SAVED_OFFSET;
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93 fs->regs.reg[AARCH64_DWARF_R0 + i].loc.offset =
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94 (_Unwind_Ptr) & (sc->regs[i]) - new_cfa;
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95 }
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96
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97 /* The core context may be extended with an arbitrary set of
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98 additional contexts appended sequentially. Each additional
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99 context contains a magic identifier and size in bytes. The size
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100 field can be used to skip over unrecognized context extensions.
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101 The end of the context sequence is marked by a context with magic
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102 0 or size 0. */
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103 for (extension_marker = (struct _aarch64_ctx *) &sc->__reserved;
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104 extension_marker->magic;
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105 extension_marker = (struct _aarch64_ctx *)
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106 ((unsigned char *) extension_marker + extension_marker->size))
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107 {
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108 if (extension_marker->magic == FPSIMD_MAGIC)
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109 {
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110 struct fpsimd_context *ctx =
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111 (struct fpsimd_context *) extension_marker;
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112 int i;
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113
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114 for (i = 0; i < AARCH64_DWARF_NUMBER_V; i++)
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115 {
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116 _Unwind_Sword offset;
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117
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118 fs->regs.reg[AARCH64_DWARF_V0 + i].how = REG_SAVED_OFFSET;
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119
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120 /* sigcontext contains 32 128bit registers for V0 to
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121 V31. The kernel will have saved the contents of the
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122 V registers. We want to unwind the callee save D
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123 registers. Each D register comprises the least
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124 significant half of the corresponding V register. We
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125 need to offset into the saved V register dependent on
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126 our endianness to find the saved D register. */
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127
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128 offset = (_Unwind_Ptr) & (ctx->vregs[i]) - new_cfa;
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129
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130 /* The endianness adjustment code below expects that a
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131 saved V register is 16 bytes. */
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132 gcc_assert (sizeof (ctx->vregs[0]) == 16);
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133 #if defined (__AARCH64EB__)
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134 offset = offset + 8;
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135 #endif
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136 fs->regs.reg[AARCH64_DWARF_V0 + i].loc.offset = offset;
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137 }
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138 }
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139 else
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140 {
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141 /* There is context provided that we do not recognize! */
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142 }
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143 }
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144
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145 fs->regs.reg[31].how = REG_SAVED_OFFSET;
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146 fs->regs.reg[31].loc.offset = (_Unwind_Ptr) & (sc->sp) - new_cfa;
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147
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148 fs->signal_frame = 1;
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149
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150 fs->regs.reg[__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__].how =
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151 REG_SAVED_VAL_OFFSET;
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152 fs->regs.reg[__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__].loc.offset =
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153 (_Unwind_Ptr) (sc->pc) - new_cfa;
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154
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155 fs->retaddr_column = __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__;
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156
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157 return _URC_NO_REASON;
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158 }
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159
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160 #endif
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