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111
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1 /* FPU-related code for x86 and x86_64 processors.
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145
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2 Copyright (C) 2005-2020 Free Software Foundation, Inc.
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111
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3 Contributed by Francois-Xavier Coudert <coudert@clipper.ens.fr>
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4
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5 This file is part of the GNU Fortran 95 runtime library (libgfortran).
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6
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7 Libgfortran is free software; you can redistribute it and/or
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8 modify it under the terms of the GNU General Public
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9 License as published by the Free Software Foundation; either
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10 version 3 of the License, or (at your option) any later version.
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11
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12 Libgfortran is distributed in the hope that it will be useful,
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13 but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 GNU General Public License for more details.
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16
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17 Under Section 7 of GPL version 3, you are granted additional
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18 permissions described in the GCC Runtime Library Exception, version
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19 3.1, as published by the Free Software Foundation.
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20
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21 You should have received a copy of the GNU General Public License and
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22 a copy of the GCC Runtime Library Exception along with this program;
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23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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24 <http://www.gnu.org/licenses/>. */
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25
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26 #ifndef __SSE_MATH__
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27 #include "cpuid.h"
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28 #endif
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29
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30 static int
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31 has_sse (void)
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32 {
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33 #ifndef __SSE_MATH__
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34 unsigned int eax, ebx, ecx, edx;
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35
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36 if (!__get_cpuid (1, &eax, &ebx, &ecx, &edx))
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37 return 0;
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38
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39 return edx & bit_SSE;
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40 #else
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41 return 1;
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42 #endif
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43 }
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44
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45 /* i387 exceptions -- see linux <fpu_control.h> header file for details. */
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46 #define _FPU_MASK_IM 0x01
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47 #define _FPU_MASK_DM 0x02
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48 #define _FPU_MASK_ZM 0x04
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49 #define _FPU_MASK_OM 0x08
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50 #define _FPU_MASK_UM 0x10
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51 #define _FPU_MASK_PM 0x20
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52 #define _FPU_MASK_ALL 0x3f
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53
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54 #define _FPU_EX_ALL 0x3f
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55
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56 /* i387 rounding modes. */
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57
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58 #define _FPU_RC_NEAREST 0x0
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59 #define _FPU_RC_DOWN 0x1
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60 #define _FPU_RC_UP 0x2
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61 #define _FPU_RC_ZERO 0x3
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62
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63 #define _FPU_RC_MASK 0x3
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64
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65 /* Enable flush to zero mode. */
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66
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67 #define MXCSR_FTZ (1 << 15)
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68
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69
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70 /* This structure corresponds to the layout of the block
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71 written by FSTENV. */
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72 typedef struct
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73 {
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74 unsigned short int __control_word;
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75 unsigned short int __unused1;
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76 unsigned short int __status_word;
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77 unsigned short int __unused2;
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78 unsigned short int __tags;
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79 unsigned short int __unused3;
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80 unsigned int __eip;
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81 unsigned short int __cs_selector;
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82 unsigned short int __opcode;
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83 unsigned int __data_offset;
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84 unsigned short int __data_selector;
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85 unsigned short int __unused5;
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86 unsigned int __mxcsr;
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87 }
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88 my_fenv_t;
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89
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90 /* Check we can actually store the FPU state in the allocated size. */
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91 _Static_assert (sizeof(my_fenv_t) <= (size_t) GFC_FPE_STATE_BUFFER_SIZE,
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92 "GFC_FPE_STATE_BUFFER_SIZE is too small");
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93
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94
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95 /* Raise the supported floating-point exceptions from EXCEPTS. Other
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96 bits in EXCEPTS are ignored. Code originally borrowed from
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97 libatomic/config/x86/fenv.c. */
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98
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99 static void
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100 local_feraiseexcept (int excepts)
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101 {
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102 if (excepts & _FPU_MASK_IM)
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103 {
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104 float f = 0.0f;
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105 #ifdef __SSE_MATH__
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106 volatile float r __attribute__ ((unused));
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107 __asm__ __volatile__ ("%vdivss\t{%0, %d0|%d0, %0}" : "+x" (f));
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108 r = f; /* Needed to trigger exception. */
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109 #else
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110 __asm__ __volatile__ ("fdiv\t{%y0, %0|%0, %y0}" : "+t" (f));
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111 /* No need for fwait, exception is triggered by emitted fstp. */
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112 #endif
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113 }
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114 if (excepts & _FPU_MASK_DM)
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115 {
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116 my_fenv_t temp;
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117 __asm__ __volatile__ ("fnstenv\t%0" : "=m" (temp));
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118 temp.__status_word |= _FPU_MASK_DM;
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119 __asm__ __volatile__ ("fldenv\t%0" : : "m" (temp));
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120 __asm__ __volatile__ ("fwait");
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121 }
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122 if (excepts & _FPU_MASK_ZM)
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123 {
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124 float f = 1.0f, g = 0.0f;
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125 #ifdef __SSE_MATH__
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126 volatile float r __attribute__ ((unused));
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127 __asm__ __volatile__ ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));
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128 r = f; /* Needed to trigger exception. */
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129 #else
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130 __asm__ __volatile__ ("fdivs\t%1" : "+t" (f) : "m" (g));
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131 /* No need for fwait, exception is triggered by emitted fstp. */
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132 #endif
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133 }
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134 if (excepts & _FPU_MASK_OM)
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135 {
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136 my_fenv_t temp;
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137 __asm__ __volatile__ ("fnstenv\t%0" : "=m" (temp));
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138 temp.__status_word |= _FPU_MASK_OM;
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139 __asm__ __volatile__ ("fldenv\t%0" : : "m" (temp));
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140 __asm__ __volatile__ ("fwait");
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141 }
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142 if (excepts & _FPU_MASK_UM)
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143 {
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144 my_fenv_t temp;
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145 __asm__ __volatile__ ("fnstenv\t%0" : "=m" (temp));
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146 temp.__status_word |= _FPU_MASK_UM;
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147 __asm__ __volatile__ ("fldenv\t%0" : : "m" (temp));
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148 __asm__ __volatile__ ("fwait");
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149 }
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150 if (excepts & _FPU_MASK_PM)
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151 {
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152 float f = 1.0f, g = 3.0f;
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153 #ifdef __SSE_MATH__
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154 volatile float r __attribute__ ((unused));
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155 __asm__ __volatile__ ("%vdivss\t{%1, %d0|%d0, %1}" : "+x" (f) : "xm" (g));
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156 r = f; /* Needed to trigger exception. */
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157 #else
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158 __asm__ __volatile__ ("fdivs\t%1" : "+t" (f) : "m" (g));
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159 /* No need for fwait, exception is triggered by emitted fstp. */
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160 #endif
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161 }
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162 }
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163
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164
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165 void
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166 set_fpu_trap_exceptions (int trap, int notrap)
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167 {
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168 int exc_set = 0, exc_clr = 0;
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169 unsigned short cw;
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170
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171 if (trap & GFC_FPE_INVALID) exc_set |= _FPU_MASK_IM;
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172 if (trap & GFC_FPE_DENORMAL) exc_set |= _FPU_MASK_DM;
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173 if (trap & GFC_FPE_ZERO) exc_set |= _FPU_MASK_ZM;
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174 if (trap & GFC_FPE_OVERFLOW) exc_set |= _FPU_MASK_OM;
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175 if (trap & GFC_FPE_UNDERFLOW) exc_set |= _FPU_MASK_UM;
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176 if (trap & GFC_FPE_INEXACT) exc_set |= _FPU_MASK_PM;
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177
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178 if (notrap & GFC_FPE_INVALID) exc_clr |= _FPU_MASK_IM;
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179 if (notrap & GFC_FPE_DENORMAL) exc_clr |= _FPU_MASK_DM;
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180 if (notrap & GFC_FPE_ZERO) exc_clr |= _FPU_MASK_ZM;
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181 if (notrap & GFC_FPE_OVERFLOW) exc_clr |= _FPU_MASK_OM;
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182 if (notrap & GFC_FPE_UNDERFLOW) exc_clr |= _FPU_MASK_UM;
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183 if (notrap & GFC_FPE_INEXACT) exc_clr |= _FPU_MASK_PM;
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184
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185 __asm__ __volatile__ ("fstcw\t%0" : "=m" (cw));
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186
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187 cw |= exc_clr;
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188 cw &= ~exc_set;
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189
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190 __asm__ __volatile__ ("fnclex\n\tfldcw\t%0" : : "m" (cw));
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191
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192 if (has_sse())
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193 {
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194 unsigned int cw_sse;
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195
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196 __asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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197
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198 /* The SSE exception masks are shifted by 7 bits. */
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199 cw_sse |= (exc_clr << 7);
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200 cw_sse &= ~(exc_set << 7);
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201
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202 /* Clear stalled exception flags. */
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203 cw_sse &= ~_FPU_EX_ALL;
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204
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205 __asm__ __volatile__ ("%vldmxcsr\t%0" : : "m" (cw_sse));
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206 }
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207 }
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208
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209 void
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210 set_fpu (void)
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211 {
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212 set_fpu_trap_exceptions (options.fpe, 0);
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213 }
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214
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215 int
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216 get_fpu_trap_exceptions (void)
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217 {
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218 unsigned short cw;
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219 int mask;
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220 int res = 0;
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221
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222 __asm__ __volatile__ ("fstcw\t%0" : "=m" (cw));
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223 mask = cw;
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224
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225 if (has_sse())
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226 {
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227 unsigned int cw_sse;
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228
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229 __asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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230
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231 /* The SSE exception masks are shifted by 7 bits. */
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232 mask |= (cw_sse >> 7);
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233 }
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234
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235 mask = ~mask & _FPU_MASK_ALL;
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236
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237 if (mask & _FPU_MASK_IM) res |= GFC_FPE_INVALID;
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238 if (mask & _FPU_MASK_DM) res |= GFC_FPE_DENORMAL;
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239 if (mask & _FPU_MASK_ZM) res |= GFC_FPE_ZERO;
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240 if (mask & _FPU_MASK_OM) res |= GFC_FPE_OVERFLOW;
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241 if (mask & _FPU_MASK_UM) res |= GFC_FPE_UNDERFLOW;
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242 if (mask & _FPU_MASK_PM) res |= GFC_FPE_INEXACT;
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243
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244 return res;
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245 }
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246
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247 int
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248 support_fpu_trap (int flag __attribute__((unused)))
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249 {
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250 return 1;
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251 }
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252
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253 int
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254 get_fpu_except_flags (void)
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255 {
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256 unsigned short cw;
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257 int excepts;
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258 int res = 0;
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259
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260 __asm__ __volatile__ ("fnstsw\t%0" : "=am" (cw));
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261 excepts = cw;
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262
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263 if (has_sse())
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264 {
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265 unsigned int cw_sse;
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266
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267 __asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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268 excepts |= cw_sse;
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269 }
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270
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271 excepts &= _FPU_EX_ALL;
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272
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273 if (excepts & _FPU_MASK_IM) res |= GFC_FPE_INVALID;
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274 if (excepts & _FPU_MASK_DM) res |= GFC_FPE_DENORMAL;
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275 if (excepts & _FPU_MASK_ZM) res |= GFC_FPE_ZERO;
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276 if (excepts & _FPU_MASK_OM) res |= GFC_FPE_OVERFLOW;
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277 if (excepts & _FPU_MASK_UM) res |= GFC_FPE_UNDERFLOW;
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278 if (excepts & _FPU_MASK_PM) res |= GFC_FPE_INEXACT;
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279
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280 return res;
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281 }
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282
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283 void
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284 set_fpu_except_flags (int set, int clear)
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285 {
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286 my_fenv_t temp;
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287 int exc_set = 0, exc_clr = 0;
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288
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289 /* Translate from GFC_PE_* values to _FPU_MASK_* values. */
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290 if (set & GFC_FPE_INVALID)
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291 exc_set |= _FPU_MASK_IM;
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292 if (clear & GFC_FPE_INVALID)
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293 exc_clr |= _FPU_MASK_IM;
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294
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295 if (set & GFC_FPE_DENORMAL)
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296 exc_set |= _FPU_MASK_DM;
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297 if (clear & GFC_FPE_DENORMAL)
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298 exc_clr |= _FPU_MASK_DM;
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299
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300 if (set & GFC_FPE_ZERO)
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301 exc_set |= _FPU_MASK_ZM;
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302 if (clear & GFC_FPE_ZERO)
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303 exc_clr |= _FPU_MASK_ZM;
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304
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305 if (set & GFC_FPE_OVERFLOW)
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306 exc_set |= _FPU_MASK_OM;
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307 if (clear & GFC_FPE_OVERFLOW)
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308 exc_clr |= _FPU_MASK_OM;
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309
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310 if (set & GFC_FPE_UNDERFLOW)
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311 exc_set |= _FPU_MASK_UM;
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312 if (clear & GFC_FPE_UNDERFLOW)
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313 exc_clr |= _FPU_MASK_UM;
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314
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315 if (set & GFC_FPE_INEXACT)
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316 exc_set |= _FPU_MASK_PM;
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317 if (clear & GFC_FPE_INEXACT)
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318 exc_clr |= _FPU_MASK_PM;
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319
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320
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321 /* Change the flags. This is tricky on 387 (unlike SSE), because we have
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322 FNSTSW but no FLDSW instruction. */
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323 __asm__ __volatile__ ("fnstenv\t%0" : "=m" (temp));
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324 temp.__status_word &= ~exc_clr;
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325 __asm__ __volatile__ ("fldenv\t%0" : : "m" (temp));
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326
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327 /* Change the flags on SSE. */
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328
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329 if (has_sse())
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330 {
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331 unsigned int cw_sse;
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332
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333 __asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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334 cw_sse &= ~exc_clr;
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335 __asm__ __volatile__ ("%vldmxcsr\t%0" : : "m" (cw_sse));
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336 }
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337
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338 local_feraiseexcept (exc_set);
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339 }
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340
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341 int
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342 support_fpu_flag (int flag __attribute__((unused)))
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343 {
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344 return 1;
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345 }
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346
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347 void
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348 set_fpu_rounding_mode (int round)
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349 {
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350 int round_mode;
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351 unsigned short cw;
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352
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353 switch (round)
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354 {
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355 case GFC_FPE_TONEAREST:
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356 round_mode = _FPU_RC_NEAREST;
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357 break;
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358 case GFC_FPE_UPWARD:
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359 round_mode = _FPU_RC_UP;
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360 break;
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361 case GFC_FPE_DOWNWARD:
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362 round_mode = _FPU_RC_DOWN;
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363 break;
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364 case GFC_FPE_TOWARDZERO:
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365 round_mode = _FPU_RC_ZERO;
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366 break;
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367 default:
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368 return; /* Should be unreachable. */
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369 }
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370
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371 __asm__ __volatile__ ("fnstcw\t%0" : "=m" (cw));
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372
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373 /* The x87 round control bits are shifted by 10 bits. */
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374 cw &= ~(_FPU_RC_MASK << 10);
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375 cw |= round_mode << 10;
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376
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377 __asm__ __volatile__ ("fldcw\t%0" : : "m" (cw));
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378
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379 if (has_sse())
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380 {
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381 unsigned int cw_sse;
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382
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383 __asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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384
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385 /* The SSE round control bits are shifted by 13 bits. */
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386 cw_sse &= ~(_FPU_RC_MASK << 13);
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387 cw_sse |= round_mode << 13;
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388
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389 __asm__ __volatile__ ("%vldmxcsr\t%0" : : "m" (cw_sse));
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390 }
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391 }
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392
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393 int
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394 get_fpu_rounding_mode (void)
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395 {
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396 int round_mode;
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397
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398 #ifdef __SSE_MATH__
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399 unsigned int cw;
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400
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401 __asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw));
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402
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403 /* The SSE round control bits are shifted by 13 bits. */
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404 round_mode = cw >> 13;
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405 #else
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406 unsigned short cw;
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407
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408 __asm__ __volatile__ ("fnstcw\t%0" : "=m" (cw));
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409
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410 /* The x87 round control bits are shifted by 10 bits. */
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411 round_mode = cw >> 10;
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412 #endif
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413
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414 round_mode &= _FPU_RC_MASK;
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415
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416 switch (round_mode)
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417 {
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418 case _FPU_RC_NEAREST:
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419 return GFC_FPE_TONEAREST;
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420 case _FPU_RC_UP:
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421 return GFC_FPE_UPWARD;
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422 case _FPU_RC_DOWN:
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423 return GFC_FPE_DOWNWARD;
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424 case _FPU_RC_ZERO:
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425 return GFC_FPE_TOWARDZERO;
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426 default:
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427 return 0; /* Should be unreachable. */
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428 }
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429 }
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430
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431 int
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432 support_fpu_rounding_mode (int mode __attribute__((unused)))
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433 {
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434 return 1;
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435 }
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436
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437 void
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438 get_fpu_state (void *state)
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439 {
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440 my_fenv_t *envp = state;
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441
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442 __asm__ __volatile__ ("fnstenv\t%0" : "=m" (*envp));
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443
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444 /* fnstenv has the side effect of masking all exceptions, so we need
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445 to restore the control word after that. */
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446 __asm__ __volatile__ ("fldcw\t%0" : : "m" (envp->__control_word));
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447
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448 if (has_sse())
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449 __asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (envp->__mxcsr));
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450 }
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451
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452 void
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453 set_fpu_state (void *state)
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454 {
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455 my_fenv_t *envp = state;
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456
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457 /* glibc sources (sysdeps/x86_64/fpu/fesetenv.c) do something more
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458 complex than this, but I think it suffices in our case. */
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459 __asm__ __volatile__ ("fldenv\t%0" : : "m" (*envp));
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460
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461 if (has_sse())
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462 __asm__ __volatile__ ("%vldmxcsr\t%0" : : "m" (envp->__mxcsr));
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463 }
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464
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465
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466 int
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467 support_fpu_underflow_control (int kind)
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468 {
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469 if (!has_sse())
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470 return 0;
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471
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472 return (kind == 4 || kind == 8) ? 1 : 0;
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473 }
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474
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475
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476 int
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477 get_fpu_underflow_mode (void)
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478 {
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479 unsigned int cw_sse;
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480
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481 if (!has_sse())
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482 return 1;
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483
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484 __asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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485
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486 /* Return 0 for abrupt underflow (flush to zero), 1 for gradual underflow. */
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487 return (cw_sse & MXCSR_FTZ) ? 0 : 1;
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488 }
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489
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490
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491 void
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492 set_fpu_underflow_mode (int gradual)
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493 {
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494 unsigned int cw_sse;
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495
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496 if (!has_sse())
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497 return;
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498
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499 __asm__ __volatile__ ("%vstmxcsr\t%0" : "=m" (cw_sse));
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500
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|
|
501 if (gradual)
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502 cw_sse &= ~MXCSR_FTZ;
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503 else
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|
|
504 cw_sse |= MXCSR_FTZ;
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505
|
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|
506 __asm__ __volatile__ ("%vldmxcsr\t%0" : : "m" (cw_sse));
|
|
|
507 }
|
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508
|
