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1 //===-- sanitizer_atomic_clang_x86.h ----------------------------*- C++ -*-===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // This file is a part of ThreadSanitizer/AddressSanitizer runtime.
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10 // Not intended for direct inclusion. Include sanitizer_atomic.h.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef SANITIZER_ATOMIC_CLANG_X86_H
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15 #define SANITIZER_ATOMIC_CLANG_X86_H
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16
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17 namespace __sanitizer {
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18
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19 INLINE void proc_yield(int cnt) {
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20 __asm__ __volatile__("" ::: "memory");
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21 for (int i = 0; i < cnt; i++)
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22 __asm__ __volatile__("pause");
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23 __asm__ __volatile__("" ::: "memory");
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24 }
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25
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26 template<typename T>
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27 INLINE typename T::Type atomic_load(
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28 const volatile T *a, memory_order mo) {
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29 DCHECK(mo & (memory_order_relaxed | memory_order_consume
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30 | memory_order_acquire | memory_order_seq_cst));
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31 DCHECK(!((uptr)a % sizeof(*a)));
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32 typename T::Type v;
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33
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34 if (sizeof(*a) < 8 || sizeof(void*) == 8) {
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35 // Assume that aligned loads are atomic.
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36 if (mo == memory_order_relaxed) {
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37 v = a->val_dont_use;
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38 } else if (mo == memory_order_consume) {
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39 // Assume that processor respects data dependencies
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40 // (and that compiler won't break them).
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41 __asm__ __volatile__("" ::: "memory");
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42 v = a->val_dont_use;
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43 __asm__ __volatile__("" ::: "memory");
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44 } else if (mo == memory_order_acquire) {
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45 __asm__ __volatile__("" ::: "memory");
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46 v = a->val_dont_use;
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47 // On x86 loads are implicitly acquire.
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48 __asm__ __volatile__("" ::: "memory");
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49 } else { // seq_cst
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50 // On x86 plain MOV is enough for seq_cst store.
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51 __asm__ __volatile__("" ::: "memory");
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52 v = a->val_dont_use;
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53 __asm__ __volatile__("" ::: "memory");
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54 }
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55 } else {
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56 // 64-bit load on 32-bit platform.
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57 __asm__ __volatile__(
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58 "movq %1, %%mm0;" // Use mmx reg for 64-bit atomic moves
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59 "movq %%mm0, %0;" // (ptr could be read-only)
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60 "emms;" // Empty mmx state/Reset FP regs
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61 : "=m" (v)
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62 : "m" (a->val_dont_use)
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63 : // mark the mmx registers as clobbered
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64 #ifdef __MMX__
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65 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
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66 #endif // #ifdef __MMX__
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67 "memory");
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68 }
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69 return v;
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70 }
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71
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72 template<typename T>
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73 INLINE void atomic_store(volatile T *a, typename T::Type v, memory_order mo) {
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74 DCHECK(mo & (memory_order_relaxed | memory_order_release
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75 | memory_order_seq_cst));
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76 DCHECK(!((uptr)a % sizeof(*a)));
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77
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78 if (sizeof(*a) < 8 || sizeof(void*) == 8) {
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79 // Assume that aligned loads are atomic.
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80 if (mo == memory_order_relaxed) {
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81 a->val_dont_use = v;
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82 } else if (mo == memory_order_release) {
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83 // On x86 stores are implicitly release.
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84 __asm__ __volatile__("" ::: "memory");
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85 a->val_dont_use = v;
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86 __asm__ __volatile__("" ::: "memory");
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87 } else { // seq_cst
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88 // On x86 stores are implicitly release.
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89 __asm__ __volatile__("" ::: "memory");
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90 a->val_dont_use = v;
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91 __sync_synchronize();
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92 }
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93 } else {
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94 // 64-bit store on 32-bit platform.
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95 __asm__ __volatile__(
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96 "movq %1, %%mm0;" // Use mmx reg for 64-bit atomic moves
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97 "movq %%mm0, %0;"
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98 "emms;" // Empty mmx state/Reset FP regs
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99 : "=m" (a->val_dont_use)
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100 : "m" (v)
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101 : // mark the mmx registers as clobbered
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102 #ifdef __MMX__
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103 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
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104 #endif // #ifdef __MMX__
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105 "memory");
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106 if (mo == memory_order_seq_cst)
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107 __sync_synchronize();
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108 }
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109 }
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110
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111 } // namespace __sanitizer
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112
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113 #endif // #ifndef SANITIZER_ATOMIC_CLANG_X86_H
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