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comparison gcc/config/aarch64/iterators.md @ 111:04ced10e8804

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author kono
date Fri, 27 Oct 2017 22:46:09 +0900
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68:561a7518be6b 111:04ced10e8804
1 ;; Machine description for AArch64 architecture.
2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
20
21 ;; -------------------------------------------------------------------
22 ;; Mode Iterators
23 ;; -------------------------------------------------------------------
24
25
26 ;; Iterator for General Purpose Integer registers (32- and 64-bit modes)
27 (define_mode_iterator GPI [SI DI])
28
29 ;; Iterator for HI, SI, DI, some instructions can only work on these modes.
30 (define_mode_iterator GPI_I16 [(HI "AARCH64_ISA_F16") SI DI])
31
32 ;; Iterator for QI and HI modes
33 (define_mode_iterator SHORT [QI HI])
34
35 ;; Iterator for all integer modes (up to 64-bit)
36 (define_mode_iterator ALLI [QI HI SI DI])
37
38 ;; Iterator for all integer modes that can be extended (up to 64-bit)
39 (define_mode_iterator ALLX [QI HI SI])
40
41 ;; Iterator for General Purpose Floating-point registers (32- and 64-bit modes)
42 (define_mode_iterator GPF [SF DF])
43
44 ;; Iterator for all scalar floating point modes (HF, SF, DF)
45 (define_mode_iterator GPF_F16 [(HF "AARCH64_ISA_F16") SF DF])
46
47 ;; Iterator for all scalar floating point modes (HF, SF, DF)
48 (define_mode_iterator GPF_HF [HF SF DF])
49
50 ;; Iterator for all scalar floating point modes (HF, SF, DF and TF)
51 (define_mode_iterator GPF_TF_F16 [HF SF DF TF])
52
53 ;; Double vector modes.
54 (define_mode_iterator VDF [V2SF V4HF])
55
56 ;; Iterator for all scalar floating point modes (SF, DF and TF)
57 (define_mode_iterator GPF_TF [SF DF TF])
58
59 ;; Integer vector modes.
60 (define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
61
62 ;; vector and scalar, 64 & 128-bit container, all integer modes
63 (define_mode_iterator VSDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI DI])
64
65 ;; vector and scalar, 64 & 128-bit container: all vector integer modes;
66 ;; 64-bit scalar integer mode
67 (define_mode_iterator VSDQ_I_DI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI DI])
68
69 ;; Double vector modes.
70 (define_mode_iterator VD [V8QI V4HI V4HF V2SI V2SF])
71
72 ;; vector, 64-bit container, all integer modes
73 (define_mode_iterator VD_BHSI [V8QI V4HI V2SI])
74
75 ;; 128 and 64-bit container; 8, 16, 32-bit vector integer modes
76 (define_mode_iterator VDQ_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI])
77
78 ;; Quad vector modes.
79 (define_mode_iterator VQ [V16QI V8HI V4SI V2DI V8HF V4SF V2DF])
80
81 ;; VQ without 2 element modes.
82 (define_mode_iterator VQ_NO2E [V16QI V8HI V4SI V8HF V4SF])
83
84 ;; Quad vector with only 2 element modes.
85 (define_mode_iterator VQ_2E [V2DI V2DF])
86
87 ;; This mode iterator allows :P to be used for patterns that operate on
88 ;; addresses in different modes. In LP64, only DI will match, while in
89 ;; ILP32, either can match.
90 (define_mode_iterator P [(SI "ptr_mode == SImode || Pmode == SImode")
91 (DI "ptr_mode == DImode || Pmode == DImode")])
92
93 ;; This mode iterator allows :PTR to be used for patterns that operate on
94 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
95 (define_mode_iterator PTR [(SI "ptr_mode == SImode") (DI "ptr_mode == DImode")])
96
97 ;; Vector Float modes suitable for moving, loading and storing.
98 (define_mode_iterator VDQF_F16 [V4HF V8HF V2SF V4SF V2DF])
99
100 ;; Vector Float modes.
101 (define_mode_iterator VDQF [V2SF V4SF V2DF])
102 (define_mode_iterator VHSDF [(V4HF "TARGET_SIMD_F16INST")
103 (V8HF "TARGET_SIMD_F16INST")
104 V2SF V4SF V2DF])
105
106 ;; Vector Float modes, and DF.
107 (define_mode_iterator VHSDF_DF [(V4HF "TARGET_SIMD_F16INST")
108 (V8HF "TARGET_SIMD_F16INST")
109 V2SF V4SF V2DF DF])
110 (define_mode_iterator VHSDF_HSDF [(V4HF "TARGET_SIMD_F16INST")
111 (V8HF "TARGET_SIMD_F16INST")
112 V2SF V4SF V2DF
113 (HF "TARGET_SIMD_F16INST")
114 SF DF])
115
116 ;; Vector single Float modes.
117 (define_mode_iterator VDQSF [V2SF V4SF])
118
119 ;; Quad vector Float modes with half/single elements.
120 (define_mode_iterator VQ_HSF [V8HF V4SF])
121
122 ;; Modes suitable to use as the return type of a vcond expression.
123 (define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
124
125 ;; All Float modes.
126 (define_mode_iterator VALLF [V2SF V4SF V2DF SF DF])
127
128 ;; Vector Float modes with 2 elements.
129 (define_mode_iterator V2F [V2SF V2DF])
130
131 ;; All vector modes on which we support any arithmetic operations.
132 (define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
133
134 ;; All vector modes suitable for moving, loading, and storing.
135 (define_mode_iterator VALL_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
136 V4HF V8HF V2SF V4SF V2DF])
137
138 ;; The VALL_F16 modes except the 128-bit 2-element ones.
139 (define_mode_iterator VALL_F16_NO_V2Q [V8QI V16QI V4HI V8HI V2SI V4SI
140 V4HF V8HF V2SF V4SF])
141
142 ;; All vector modes barring HF modes, plus DI.
143 (define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
144
145 ;; All vector modes and DI.
146 (define_mode_iterator VALLDI_F16 [V8QI V16QI V4HI V8HI V2SI V4SI V2DI
147 V4HF V8HF V2SF V4SF V2DF DI])
148
149 ;; All vector modes, plus DI and DF.
150 (define_mode_iterator VALLDIF [V8QI V16QI V4HI V8HI V2SI V4SI
151 V2DI V4HF V8HF V2SF V4SF V2DF DI DF])
152
153 ;; Vector modes for Integer reduction across lanes.
154 (define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI V2DI])
155
156 ;; Vector modes(except V2DI) for Integer reduction across lanes.
157 (define_mode_iterator VDQV_S [V8QI V16QI V4HI V8HI V4SI])
158
159 ;; All double integer narrow-able modes.
160 (define_mode_iterator VDN [V4HI V2SI DI])
161
162 ;; All quad integer narrow-able modes.
163 (define_mode_iterator VQN [V8HI V4SI V2DI])
164
165 ;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes
166 (define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
167
168 ;; All quad integer widen-able modes.
169 (define_mode_iterator VQW [V16QI V8HI V4SI])
170
171 ;; Double vector modes for combines.
172 (define_mode_iterator VDC [V8QI V4HI V4HF V2SI V2SF DI DF])
173
174 ;; Vector modes except double int.
175 (define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
176 (define_mode_iterator VDQIF_F16 [V8QI V16QI V4HI V8HI V2SI V4SI
177 V4HF V8HF V2SF V4SF V2DF])
178
179 ;; Vector modes for S type.
180 (define_mode_iterator VDQ_SI [V2SI V4SI])
181
182 ;; Vector modes for S and D
183 (define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
184
185 ;; Vector modes for H, S and D
186 (define_mode_iterator VDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
187 (V8HI "TARGET_SIMD_F16INST")
188 V2SI V4SI V2DI])
189
190 ;; Scalar and Vector modes for S and D
191 (define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
192
193 ;; Scalar and Vector modes for S and D, Vector modes for H.
194 (define_mode_iterator VSDQ_HSDI [(V4HI "TARGET_SIMD_F16INST")
195 (V8HI "TARGET_SIMD_F16INST")
196 V2SI V4SI V2DI
197 (HI "TARGET_SIMD_F16INST")
198 SI DI])
199
200 ;; Vector modes for Q and H types.
201 (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
202
203 ;; Vector modes for H and S types.
204 (define_mode_iterator VDQHS [V4HI V8HI V2SI V4SI])
205
206 ;; Vector modes for H, S and D types.
207 (define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
208
209 ;; Vector and scalar integer modes for H and S
210 (define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
211
212 ;; Vector and scalar 64-bit container: 16, 32-bit integer modes
213 (define_mode_iterator VSD_HSI [V4HI V2SI HI SI])
214
215 ;; Vector 64-bit container: 16, 32-bit integer modes
216 (define_mode_iterator VD_HSI [V4HI V2SI])
217
218 ;; Scalar 64-bit container: 16, 32-bit integer modes
219 (define_mode_iterator SD_HSI [HI SI])
220
221 ;; Vector 64-bit container: 16, 32-bit integer modes
222 (define_mode_iterator VQ_HSI [V8HI V4SI])
223
224 ;; All byte modes.
225 (define_mode_iterator VB [V8QI V16QI])
226
227 ;; 2 and 4 lane SI modes.
228 (define_mode_iterator VS [V2SI V4SI])
229
230 (define_mode_iterator TX [TI TF])
231
232 ;; Opaque structure modes.
233 (define_mode_iterator VSTRUCT [OI CI XI])
234
235 ;; Double scalar modes
236 (define_mode_iterator DX [DI DF])
237
238 ;; Modes available for <f>mul lane operations.
239 (define_mode_iterator VMUL [V4HI V8HI V2SI V4SI
240 (V4HF "TARGET_SIMD_F16INST")
241 (V8HF "TARGET_SIMD_F16INST")
242 V2SF V4SF V2DF])
243
244 ;; Modes available for <f>mul lane operations changing lane count.
245 (define_mode_iterator VMUL_CHANGE_NLANES [V4HI V8HI V2SI V4SI V2SF V4SF])
246
247 ;; ------------------------------------------------------------------
248 ;; Unspec enumerations for Advance SIMD. These could well go into
249 ;; aarch64.md but for their use in int_iterators here.
250 ;; ------------------------------------------------------------------
251
252 (define_c_enum "unspec"
253 [
254 UNSPEC_ASHIFT_SIGNED ; Used in aarch-simd.md.
255 UNSPEC_ASHIFT_UNSIGNED ; Used in aarch64-simd.md.
256 UNSPEC_ABS ; Used in aarch64-simd.md.
257 UNSPEC_FMAX ; Used in aarch64-simd.md.
258 UNSPEC_FMAXNMV ; Used in aarch64-simd.md.
259 UNSPEC_FMAXV ; Used in aarch64-simd.md.
260 UNSPEC_FMIN ; Used in aarch64-simd.md.
261 UNSPEC_FMINNMV ; Used in aarch64-simd.md.
262 UNSPEC_FMINV ; Used in aarch64-simd.md.
263 UNSPEC_FADDV ; Used in aarch64-simd.md.
264 UNSPEC_ADDV ; Used in aarch64-simd.md.
265 UNSPEC_SMAXV ; Used in aarch64-simd.md.
266 UNSPEC_SMINV ; Used in aarch64-simd.md.
267 UNSPEC_UMAXV ; Used in aarch64-simd.md.
268 UNSPEC_UMINV ; Used in aarch64-simd.md.
269 UNSPEC_SHADD ; Used in aarch64-simd.md.
270 UNSPEC_UHADD ; Used in aarch64-simd.md.
271 UNSPEC_SRHADD ; Used in aarch64-simd.md.
272 UNSPEC_URHADD ; Used in aarch64-simd.md.
273 UNSPEC_SHSUB ; Used in aarch64-simd.md.
274 UNSPEC_UHSUB ; Used in aarch64-simd.md.
275 UNSPEC_SRHSUB ; Used in aarch64-simd.md.
276 UNSPEC_URHSUB ; Used in aarch64-simd.md.
277 UNSPEC_ADDHN ; Used in aarch64-simd.md.
278 UNSPEC_RADDHN ; Used in aarch64-simd.md.
279 UNSPEC_SUBHN ; Used in aarch64-simd.md.
280 UNSPEC_RSUBHN ; Used in aarch64-simd.md.
281 UNSPEC_ADDHN2 ; Used in aarch64-simd.md.
282 UNSPEC_RADDHN2 ; Used in aarch64-simd.md.
283 UNSPEC_SUBHN2 ; Used in aarch64-simd.md.
284 UNSPEC_RSUBHN2 ; Used in aarch64-simd.md.
285 UNSPEC_SQDMULH ; Used in aarch64-simd.md.
286 UNSPEC_SQRDMULH ; Used in aarch64-simd.md.
287 UNSPEC_PMUL ; Used in aarch64-simd.md.
288 UNSPEC_FMULX ; Used in aarch64-simd.md.
289 UNSPEC_USQADD ; Used in aarch64-simd.md.
290 UNSPEC_SUQADD ; Used in aarch64-simd.md.
291 UNSPEC_SQXTUN ; Used in aarch64-simd.md.
292 UNSPEC_SQXTN ; Used in aarch64-simd.md.
293 UNSPEC_UQXTN ; Used in aarch64-simd.md.
294 UNSPEC_SSRA ; Used in aarch64-simd.md.
295 UNSPEC_USRA ; Used in aarch64-simd.md.
296 UNSPEC_SRSRA ; Used in aarch64-simd.md.
297 UNSPEC_URSRA ; Used in aarch64-simd.md.
298 UNSPEC_SRSHR ; Used in aarch64-simd.md.
299 UNSPEC_URSHR ; Used in aarch64-simd.md.
300 UNSPEC_SQSHLU ; Used in aarch64-simd.md.
301 UNSPEC_SQSHL ; Used in aarch64-simd.md.
302 UNSPEC_UQSHL ; Used in aarch64-simd.md.
303 UNSPEC_SQSHRUN ; Used in aarch64-simd.md.
304 UNSPEC_SQRSHRUN ; Used in aarch64-simd.md.
305 UNSPEC_SQSHRN ; Used in aarch64-simd.md.
306 UNSPEC_UQSHRN ; Used in aarch64-simd.md.
307 UNSPEC_SQRSHRN ; Used in aarch64-simd.md.
308 UNSPEC_UQRSHRN ; Used in aarch64-simd.md.
309 UNSPEC_SSHL ; Used in aarch64-simd.md.
310 UNSPEC_USHL ; Used in aarch64-simd.md.
311 UNSPEC_SRSHL ; Used in aarch64-simd.md.
312 UNSPEC_URSHL ; Used in aarch64-simd.md.
313 UNSPEC_SQRSHL ; Used in aarch64-simd.md.
314 UNSPEC_UQRSHL ; Used in aarch64-simd.md.
315 UNSPEC_SSLI ; Used in aarch64-simd.md.
316 UNSPEC_USLI ; Used in aarch64-simd.md.
317 UNSPEC_SSRI ; Used in aarch64-simd.md.
318 UNSPEC_USRI ; Used in aarch64-simd.md.
319 UNSPEC_SSHLL ; Used in aarch64-simd.md.
320 UNSPEC_USHLL ; Used in aarch64-simd.md.
321 UNSPEC_ADDP ; Used in aarch64-simd.md.
322 UNSPEC_TBL ; Used in vector permute patterns.
323 UNSPEC_TBX ; Used in vector permute patterns.
324 UNSPEC_CONCAT ; Used in vector permute patterns.
325 UNSPEC_ZIP1 ; Used in vector permute patterns.
326 UNSPEC_ZIP2 ; Used in vector permute patterns.
327 UNSPEC_UZP1 ; Used in vector permute patterns.
328 UNSPEC_UZP2 ; Used in vector permute patterns.
329 UNSPEC_TRN1 ; Used in vector permute patterns.
330 UNSPEC_TRN2 ; Used in vector permute patterns.
331 UNSPEC_EXT ; Used in aarch64-simd.md.
332 UNSPEC_REV64 ; Used in vector reverse patterns (permute).
333 UNSPEC_REV32 ; Used in vector reverse patterns (permute).
334 UNSPEC_REV16 ; Used in vector reverse patterns (permute).
335 UNSPEC_AESE ; Used in aarch64-simd.md.
336 UNSPEC_AESD ; Used in aarch64-simd.md.
337 UNSPEC_AESMC ; Used in aarch64-simd.md.
338 UNSPEC_AESIMC ; Used in aarch64-simd.md.
339 UNSPEC_SHA1C ; Used in aarch64-simd.md.
340 UNSPEC_SHA1M ; Used in aarch64-simd.md.
341 UNSPEC_SHA1P ; Used in aarch64-simd.md.
342 UNSPEC_SHA1H ; Used in aarch64-simd.md.
343 UNSPEC_SHA1SU0 ; Used in aarch64-simd.md.
344 UNSPEC_SHA1SU1 ; Used in aarch64-simd.md.
345 UNSPEC_SHA256H ; Used in aarch64-simd.md.
346 UNSPEC_SHA256H2 ; Used in aarch64-simd.md.
347 UNSPEC_SHA256SU0 ; Used in aarch64-simd.md.
348 UNSPEC_SHA256SU1 ; Used in aarch64-simd.md.
349 UNSPEC_PMULL ; Used in aarch64-simd.md.
350 UNSPEC_PMULL2 ; Used in aarch64-simd.md.
351 UNSPEC_REV_REGLIST ; Used in aarch64-simd.md.
352 UNSPEC_VEC_SHR ; Used in aarch64-simd.md.
353 UNSPEC_SQRDMLAH ; Used in aarch64-simd.md.
354 UNSPEC_SQRDMLSH ; Used in aarch64-simd.md.
355 UNSPEC_FMAXNM ; Used in aarch64-simd.md.
356 UNSPEC_FMINNM ; Used in aarch64-simd.md.
357 UNSPEC_SDOT ; Used in aarch64-simd.md.
358 UNSPEC_UDOT ; Used in aarch64-simd.md.
359 ])
360
361 ;; ------------------------------------------------------------------
362 ;; Unspec enumerations for Atomics. They are here so that they can be
363 ;; used in the int_iterators for atomic operations.
364 ;; ------------------------------------------------------------------
365
366 (define_c_enum "unspecv"
367 [
368 UNSPECV_LX ; Represent a load-exclusive.
369 UNSPECV_SX ; Represent a store-exclusive.
370 UNSPECV_LDA ; Represent an atomic load or load-acquire.
371 UNSPECV_STL ; Represent an atomic store or store-release.
372 UNSPECV_ATOMIC_CMPSW ; Represent an atomic compare swap.
373 UNSPECV_ATOMIC_EXCHG ; Represent an atomic exchange.
374 UNSPECV_ATOMIC_CAS ; Represent an atomic CAS.
375 UNSPECV_ATOMIC_SWP ; Represent an atomic SWP.
376 UNSPECV_ATOMIC_OP ; Represent an atomic operation.
377 UNSPECV_ATOMIC_LDOP ; Represent an atomic load-operation
378 UNSPECV_ATOMIC_LDOP_OR ; Represent an atomic load-or
379 UNSPECV_ATOMIC_LDOP_BIC ; Represent an atomic load-bic
380 UNSPECV_ATOMIC_LDOP_XOR ; Represent an atomic load-xor
381 UNSPECV_ATOMIC_LDOP_PLUS ; Represent an atomic load-add
382 ])
383
384 ;; -------------------------------------------------------------------
385 ;; Mode attributes
386 ;; -------------------------------------------------------------------
387
388 ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
389 ;; 32-bit version and "%x0" in the 64-bit version.
390 (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")])
391
392 ;; The size of access, in bytes.
393 (define_mode_attr ldst_sz [(SI "4") (DI "8")])
394 ;; Likewise for load/store pair.
395 (define_mode_attr ldpstp_sz [(SI "8") (DI "16")])
396
397 ;; For inequal width int to float conversion
398 (define_mode_attr w1 [(HF "w") (SF "w") (DF "x")])
399 (define_mode_attr w2 [(HF "x") (SF "x") (DF "w")])
400
401 (define_mode_attr short_mask [(HI "65535") (QI "255")])
402
403 ;; For constraints used in scalar immediate vector moves
404 (define_mode_attr hq [(HI "h") (QI "q")])
405
406 ;; For doubling width of an integer mode
407 (define_mode_attr DWI [(QI "HI") (HI "SI") (SI "DI") (DI "TI")])
408
409 ;; For scalar usage of vector/FP registers
410 (define_mode_attr v [(QI "b") (HI "h") (SI "s") (DI "d")
411 (HF "h") (SF "s") (DF "d")
412 (V8QI "") (V16QI "")
413 (V4HI "") (V8HI "")
414 (V2SI "") (V4SI "")
415 (V2DI "") (V2SF "")
416 (V4SF "") (V4HF "")
417 (V8HF "") (V2DF "")])
418
419 ;; For scalar usage of vector/FP registers, narrowing
420 (define_mode_attr vn2 [(QI "") (HI "b") (SI "h") (DI "s")
421 (V8QI "") (V16QI "")
422 (V4HI "") (V8HI "")
423 (V2SI "") (V4SI "")
424 (V2DI "") (V2SF "")
425 (V4SF "") (V2DF "")])
426
427 ;; For scalar usage of vector/FP registers, widening
428 (define_mode_attr vw2 [(DI "") (QI "h") (HI "s") (SI "d")
429 (V8QI "") (V16QI "")
430 (V4HI "") (V8HI "")
431 (V2SI "") (V4SI "")
432 (V2DI "") (V2SF "")
433 (V4SF "") (V2DF "")])
434
435 ;; Register Type Name and Vector Arrangement Specifier for when
436 ;; we are doing scalar for DI and SIMD for SI (ignoring all but
437 ;; lane 0).
438 (define_mode_attr rtn [(DI "d") (SI "")])
439 (define_mode_attr vas [(DI "") (SI ".2s")])
440
441 ;; Map a floating point mode to the appropriate register name prefix
442 (define_mode_attr s [(HF "h") (SF "s") (DF "d")])
443
444 ;; Give the length suffix letter for a sign- or zero-extension.
445 (define_mode_attr size [(QI "b") (HI "h") (SI "w")])
446
447 ;; Give the number of bits in the mode
448 (define_mode_attr sizen [(QI "8") (HI "16") (SI "32") (DI "64")])
449
450 ;; Give the ordinal of the MSB in the mode
451 (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63")])
452
453 ;; Attribute to describe constants acceptable in logical operations
454 (define_mode_attr lconst [(SI "K") (DI "L")])
455
456 ;; Attribute to describe constants acceptable in logical and operations
457 (define_mode_attr lconst2 [(SI "UsO") (DI "UsP")])
458
459 ;; Map a mode to a specific constraint character.
460 (define_mode_attr cmode [(QI "q") (HI "h") (SI "s") (DI "d")])
461
462 (define_mode_attr Vtype [(V8QI "8b") (V16QI "16b")
463 (V4HI "4h") (V8HI "8h")
464 (V2SI "2s") (V4SI "4s")
465 (DI "1d") (DF "1d")
466 (V2DI "2d") (V2SF "2s")
467 (V4SF "4s") (V2DF "2d")
468 (V4HF "4h") (V8HF "8h")])
469
470 (define_mode_attr Vrevsuff [(V4HI "16") (V8HI "16") (V2SI "32")
471 (V4SI "32") (V2DI "64")])
472
473 (define_mode_attr Vmtype [(V8QI ".8b") (V16QI ".16b")
474 (V4HI ".4h") (V8HI ".8h")
475 (V2SI ".2s") (V4SI ".4s")
476 (V2DI ".2d") (V4HF ".4h")
477 (V8HF ".8h") (V2SF ".2s")
478 (V4SF ".4s") (V2DF ".2d")
479 (DI "") (SI "")
480 (HI "") (QI "")
481 (TI "") (HF "")
482 (SF "") (DF "")])
483
484 ;; Register suffix narrowed modes for VQN.
485 (define_mode_attr Vmntype [(V8HI ".8b") (V4SI ".4h")
486 (V2DI ".2s")
487 (DI "") (SI "")
488 (HI "")])
489
490 ;; Mode-to-individual element type mapping.
491 (define_mode_attr Vetype [(V8QI "b") (V16QI "b")
492 (V4HI "h") (V8HI "h")
493 (V2SI "s") (V4SI "s")
494 (V2DI "d") (V4HF "h")
495 (V8HF "h") (V2SF "s")
496 (V4SF "s") (V2DF "d")
497 (HF "h")
498 (SF "s") (DF "d")
499 (QI "b") (HI "h")
500 (SI "s") (DI "d")])
501
502 ;; Vetype is used everywhere in scheduling type and assembly output,
503 ;; sometimes they are not the same, for example HF modes on some
504 ;; instructions. stype is defined to represent scheduling type
505 ;; more accurately.
506 (define_mode_attr stype [(V8QI "b") (V16QI "b") (V4HI "s") (V8HI "s")
507 (V2SI "s") (V4SI "s") (V2DI "d") (V4HF "s")
508 (V8HF "s") (V2SF "s") (V4SF "s") (V2DF "d")
509 (HF "s") (SF "s") (DF "d") (QI "b") (HI "s")
510 (SI "s") (DI "d")])
511
512 ;; Mode-to-bitwise operation type mapping.
513 (define_mode_attr Vbtype [(V8QI "8b") (V16QI "16b")
514 (V4HI "8b") (V8HI "16b")
515 (V2SI "8b") (V4SI "16b")
516 (V2DI "16b") (V4HF "8b")
517 (V8HF "16b") (V2SF "8b")
518 (V4SF "16b") (V2DF "16b")
519 (DI "8b") (DF "8b")
520 (SI "8b")])
521
522 ;; Define element mode for each vector mode.
523 (define_mode_attr VEL [(V8QI "QI") (V16QI "QI")
524 (V4HI "HI") (V8HI "HI")
525 (V2SI "SI") (V4SI "SI")
526 (DI "DI") (V2DI "DI")
527 (V4HF "HF") (V8HF "HF")
528 (V2SF "SF") (V4SF "SF")
529 (V2DF "DF") (DF "DF")
530 (SI "SI") (HI "HI")
531 (QI "QI")])
532
533 ;; Define element mode for each vector mode (lower case).
534 (define_mode_attr Vel [(V8QI "qi") (V16QI "qi")
535 (V4HI "hi") (V8HI "hi")
536 (V2SI "si") (V4SI "si")
537 (DI "di") (V2DI "di")
538 (V4HF "hf") (V8HF "hf")
539 (V2SF "sf") (V4SF "sf")
540 (V2DF "df") (DF "df")
541 (SI "si") (HI "hi")
542 (QI "qi")])
543
544 ;; 64-bit container modes the inner or scalar source mode.
545 (define_mode_attr VCOND [(HI "V4HI") (SI "V2SI")
546 (V4HI "V4HI") (V8HI "V4HI")
547 (V2SI "V2SI") (V4SI "V2SI")
548 (DI "DI") (V2DI "DI")
549 (V2SF "V2SF") (V4SF "V2SF")
550 (V2DF "DF")])
551
552 ;; 128-bit container modes the inner or scalar source mode.
553 (define_mode_attr VCONQ [(V8QI "V16QI") (V16QI "V16QI")
554 (V4HI "V8HI") (V8HI "V8HI")
555 (V2SI "V4SI") (V4SI "V4SI")
556 (DI "V2DI") (V2DI "V2DI")
557 (V4HF "V8HF") (V8HF "V8HF")
558 (V2SF "V2SF") (V4SF "V4SF")
559 (V2DF "V2DF") (SI "V4SI")
560 (HI "V8HI") (QI "V16QI")])
561
562 ;; Half modes of all vector modes.
563 (define_mode_attr VHALF [(V8QI "V4QI") (V16QI "V8QI")
564 (V4HI "V2HI") (V8HI "V4HI")
565 (V2SI "SI") (V4SI "V2SI")
566 (V2DI "DI") (V2SF "SF")
567 (V4SF "V2SF") (V4HF "V2HF")
568 (V8HF "V4HF") (V2DF "DF")])
569
570 ;; Half modes of all vector modes, in lower-case.
571 (define_mode_attr Vhalf [(V8QI "v4qi") (V16QI "v8qi")
572 (V4HI "v2hi") (V8HI "v4hi")
573 (V2SI "si") (V4SI "v2si")
574 (V2DI "di") (V2SF "sf")
575 (V4SF "v2sf") (V2DF "df")])
576
577 ;; Double modes of vector modes.
578 (define_mode_attr VDBL [(V8QI "V16QI") (V4HI "V8HI")
579 (V4HF "V8HF")
580 (V2SI "V4SI") (V2SF "V4SF")
581 (SI "V2SI") (DI "V2DI")
582 (DF "V2DF")])
583
584 ;; Register suffix for double-length mode.
585 (define_mode_attr Vdtype [(V4HF "8h") (V2SF "4s")])
586
587 ;; Double modes of vector modes (lower case).
588 (define_mode_attr Vdbl [(V8QI "v16qi") (V4HI "v8hi")
589 (V4HF "v8hf")
590 (V2SI "v4si") (V2SF "v4sf")
591 (SI "v2si") (DI "v2di")
592 (DF "v2df")])
593
594 ;; Modes with double-width elements.
595 (define_mode_attr VDBLW [(V8QI "V4HI") (V16QI "V8HI")
596 (V4HI "V2SI") (V8HI "V4SI")
597 (V2SI "DI") (V4SI "V2DI")])
598
599 ;; Narrowed modes for VDN.
600 (define_mode_attr VNARROWD [(V4HI "V8QI") (V2SI "V4HI")
601 (DI "V2SI")])
602
603 ;; Narrowed double-modes for VQN (Used for XTN).
604 (define_mode_attr VNARROWQ [(V8HI "V8QI") (V4SI "V4HI")
605 (V2DI "V2SI")
606 (DI "SI") (SI "HI")
607 (HI "QI")])
608
609 ;; Narrowed quad-modes for VQN (Used for XTN2).
610 (define_mode_attr VNARROWQ2 [(V8HI "V16QI") (V4SI "V8HI")
611 (V2DI "V4SI")])
612
613 ;; Register suffix narrowed modes for VQN.
614 (define_mode_attr Vntype [(V8HI "8b") (V4SI "4h")
615 (V2DI "2s")])
616
617 ;; Register suffix narrowed modes for VQN.
618 (define_mode_attr V2ntype [(V8HI "16b") (V4SI "8h")
619 (V2DI "4s")])
620
621 ;; Widened modes of vector modes.
622 (define_mode_attr VWIDE [(V8QI "V8HI") (V4HI "V4SI")
623 (V2SI "V2DI") (V16QI "V8HI")
624 (V8HI "V4SI") (V4SI "V2DI")
625 (HI "SI") (SI "DI")
626 (V8HF "V4SF") (V4SF "V2DF")
627 (V4HF "V4SF") (V2SF "V2DF")]
628 )
629
630 ;; Widened modes of vector modes, lowercase
631 (define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")])
632
633 ;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
634 (define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
635 (V2SI "2d") (V16QI "8h")
636 (V8HI "4s") (V4SI "2d")
637 (V8HF "4s") (V4SF "2d")])
638
639 ;; Widened mode register suffixes for VDW/VQW.
640 (define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
641 (V2SI ".2d") (V16QI ".8h")
642 (V8HI ".4s") (V4SI ".2d")
643 (V4HF ".4s") (V2SF ".2d")
644 (SI "") (HI "")])
645
646 ;; Lower part register suffixes for VQW/VQ_HSF.
647 (define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
648 (V4SI "2s") (V8HF "4h")
649 (V4SF "2s")])
650
651 ;; Define corresponding core/FP element mode for each vector mode.
652 (define_mode_attr vw [(V8QI "w") (V16QI "w")
653 (V4HI "w") (V8HI "w")
654 (V2SI "w") (V4SI "w")
655 (DI "x") (V2DI "x")
656 (V2SF "s") (V4SF "s")
657 (V2DF "d")])
658
659 ;; Corresponding core element mode for each vector mode. This is a
660 ;; variation on <vw> mapping FP modes to GP regs.
661 (define_mode_attr vwcore [(V8QI "w") (V16QI "w")
662 (V4HI "w") (V8HI "w")
663 (V2SI "w") (V4SI "w")
664 (DI "x") (V2DI "x")
665 (V4HF "w") (V8HF "w")
666 (V2SF "w") (V4SF "w")
667 (V2DF "x")])
668
669 ;; Double vector types for ALLX.
670 (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")])
671
672 ;; Mode with floating-point values replaced by like-sized integers.
673 (define_mode_attr V_INT_EQUIV [(V8QI "V8QI") (V16QI "V16QI")
674 (V4HI "V4HI") (V8HI "V8HI")
675 (V2SI "V2SI") (V4SI "V4SI")
676 (DI "DI") (V2DI "V2DI")
677 (V4HF "V4HI") (V8HF "V8HI")
678 (V2SF "V2SI") (V4SF "V4SI")
679 (V2DF "V2DI") (DF "DI")
680 (SF "SI") (HF "HI")])
681
682 ;; Lower case mode with floating-point values replaced by like-sized integers.
683 (define_mode_attr v_int_equiv [(V8QI "v8qi") (V16QI "v16qi")
684 (V4HI "v4hi") (V8HI "v8hi")
685 (V2SI "v2si") (V4SI "v4si")
686 (DI "di") (V2DI "v2di")
687 (V4HF "v4hi") (V8HF "v8hi")
688 (V2SF "v2si") (V4SF "v4si")
689 (V2DF "v2di") (DF "di")
690 (SF "si")])
691
692 ;; Mode for vector conditional operations where the comparison has
693 ;; different type from the lhs.
694 (define_mode_attr V_cmp_mixed [(V2SI "V2SF") (V4SI "V4SF")
695 (V2DI "V2DF") (V2SF "V2SI")
696 (V4SF "V4SI") (V2DF "V2DI")])
697
698 (define_mode_attr v_cmp_mixed [(V2SI "v2sf") (V4SI "v4sf")
699 (V2DI "v2df") (V2SF "v2si")
700 (V4SF "v4si") (V2DF "v2di")])
701
702 ;; Lower case element modes (as used in shift immediate patterns).
703 (define_mode_attr ve_mode [(V8QI "qi") (V16QI "qi")
704 (V4HI "hi") (V8HI "hi")
705 (V2SI "si") (V4SI "si")
706 (DI "di") (V2DI "di")
707 (QI "qi") (HI "hi")
708 (SI "si")])
709
710 ;; Vm for lane instructions is restricted to FP_LO_REGS.
711 (define_mode_attr vwx [(V4HI "x") (V8HI "x") (HI "x")
712 (V2SI "w") (V4SI "w") (SI "w")])
713
714 (define_mode_attr Vendreg [(OI "T") (CI "U") (XI "V")])
715
716 ;; This is both the number of Q-Registers needed to hold the corresponding
717 ;; opaque large integer mode, and the number of elements touched by the
718 ;; ld..._lane and st..._lane operations.
719 (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")])
720
721 ;; Mode for atomic operation suffixes
722 (define_mode_attr atomic_sfx
723 [(QI "b") (HI "h") (SI "") (DI "")])
724
725 (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
726 (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
727 (SF "si") (DF "di") (SI "sf") (DI "df")
728 (V4HF "v4hi") (V8HF "v8hi") (V4HI "v4hf")
729 (V8HI "v8hf") (HF "hi") (HI "hf")])
730 (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
731 (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
732 (SF "SI") (DF "DI") (SI "SF") (DI "DF")
733 (V4HF "V4HI") (V8HF "V8HI") (V4HI "V4HF")
734 (V8HI "V8HF") (HF "HI") (HI "HF")])
735
736
737 ;; for the inequal width integer to fp conversions
738 (define_mode_attr fcvt_iesize [(HF "di") (SF "di") (DF "si")])
739 (define_mode_attr FCVT_IESIZE [(HF "DI") (SF "DI") (DF "SI")])
740
741 (define_mode_attr VSWAP_WIDTH [(V8QI "V16QI") (V16QI "V8QI")
742 (V4HI "V8HI") (V8HI "V4HI")
743 (V2SI "V4SI") (V4SI "V2SI")
744 (DI "V2DI") (V2DI "DI")
745 (V2SF "V4SF") (V4SF "V2SF")
746 (V4HF "V8HF") (V8HF "V4HF")
747 (DF "V2DF") (V2DF "DF")])
748
749 (define_mode_attr vswap_width_name [(V8QI "to_128") (V16QI "to_64")
750 (V4HI "to_128") (V8HI "to_64")
751 (V2SI "to_128") (V4SI "to_64")
752 (DI "to_128") (V2DI "to_64")
753 (V4HF "to_128") (V8HF "to_64")
754 (V2SF "to_128") (V4SF "to_64")
755 (DF "to_128") (V2DF "to_64")])
756
757 ;; For certain vector-by-element multiplication instructions we must
758 ;; constrain the 16-bit cases to use only V0-V15. This is covered by
759 ;; the 'x' constraint. All other modes may use the 'w' constraint.
760 (define_mode_attr h_con [(V2SI "w") (V4SI "w")
761 (V4HI "x") (V8HI "x")
762 (V4HF "x") (V8HF "x")
763 (V2SF "w") (V4SF "w")
764 (V2DF "w") (DF "w")])
765
766 ;; Defined to 'f' for types whose element type is a float type.
767 (define_mode_attr f [(V8QI "") (V16QI "")
768 (V4HI "") (V8HI "")
769 (V2SI "") (V4SI "")
770 (DI "") (V2DI "")
771 (V4HF "f") (V8HF "f")
772 (V2SF "f") (V4SF "f")
773 (V2DF "f") (DF "f")])
774
775 ;; Defined to '_fp' for types whose element type is a float type.
776 (define_mode_attr fp [(V8QI "") (V16QI "")
777 (V4HI "") (V8HI "")
778 (V2SI "") (V4SI "")
779 (DI "") (V2DI "")
780 (V4HF "_fp") (V8HF "_fp")
781 (V2SF "_fp") (V4SF "_fp")
782 (V2DF "_fp") (DF "_fp")
783 (SF "_fp")])
784
785 ;; Defined to '_q' for 128-bit types.
786 (define_mode_attr q [(V8QI "") (V16QI "_q")
787 (V4HI "") (V8HI "_q")
788 (V2SI "") (V4SI "_q")
789 (DI "") (V2DI "_q")
790 (V4HF "") (V8HF "_q")
791 (V2SF "") (V4SF "_q")
792 (V2DF "_q")
793 (QI "") (HI "") (SI "") (DI "") (HF "") (SF "") (DF "")])
794
795 (define_mode_attr vp [(V8QI "v") (V16QI "v")
796 (V4HI "v") (V8HI "v")
797 (V2SI "p") (V4SI "v")
798 (V2DI "p") (V2DF "p")
799 (V2SF "p") (V4SF "v")
800 (V4HF "v") (V8HF "v")])
801
802 (define_mode_attr vsi2qi [(V2SI "v8qi") (V4SI "v16qi")])
803 (define_mode_attr VSI2QI [(V2SI "V8QI") (V4SI "V16QI")])
804
805
806 ;; Register suffix for DOTPROD input types from the return type.
807 (define_mode_attr Vdottype [(V2SI "8b") (V4SI "16b")])
808
809 ;; Sum of lengths of instructions needed to move vector registers of a mode.
810 (define_mode_attr insn_count [(OI "8") (CI "12") (XI "16")])
811
812 ;; -fpic small model GOT reloc modifers: gotpage_lo15/lo14 for ILP64/32.
813 ;; No need of iterator for -fPIC as it use got_lo12 for both modes.
814 (define_mode_attr got_modifier [(SI "gotpage_lo14") (DI "gotpage_lo15")])
815
816 ;; -------------------------------------------------------------------
817 ;; Code Iterators
818 ;; -------------------------------------------------------------------
819
820 ;; This code iterator allows the various shifts supported on the core
821 (define_code_iterator SHIFT [ashift ashiftrt lshiftrt rotatert])
822
823 ;; This code iterator allows the shifts supported in arithmetic instructions
824 (define_code_iterator ASHIFT [ashift ashiftrt lshiftrt])
825
826 ;; Code iterator for logical operations
827 (define_code_iterator LOGICAL [and ior xor])
828
829 ;; Code iterator for logical operations whose :nlogical works on SIMD registers.
830 (define_code_iterator NLOGICAL [and ior])
831
832 ;; Code iterator for unary negate and bitwise complement.
833 (define_code_iterator NEG_NOT [neg not])
834
835 ;; Code iterator for sign/zero extension
836 (define_code_iterator ANY_EXTEND [sign_extend zero_extend])
837
838 ;; All division operations (signed/unsigned)
839 (define_code_iterator ANY_DIV [div udiv])
840
841 ;; Code iterator for sign/zero extraction
842 (define_code_iterator ANY_EXTRACT [sign_extract zero_extract])
843
844 ;; Code iterator for equality comparisons
845 (define_code_iterator EQL [eq ne])
846
847 ;; Code iterator for less-than and greater/equal-to
848 (define_code_iterator LTGE [lt ge])
849
850 ;; Iterator for __sync_<op> operations that where the operation can be
851 ;; represented directly RTL. This is all of the sync operations bar
852 ;; nand.
853 (define_code_iterator atomic_op [plus minus ior xor and])
854
855 ;; Iterator for integer conversions
856 (define_code_iterator FIXUORS [fix unsigned_fix])
857
858 ;; Iterator for float conversions
859 (define_code_iterator FLOATUORS [float unsigned_float])
860
861 ;; Code iterator for variants of vector max and min.
862 (define_code_iterator MAXMIN [smax smin umax umin])
863
864 (define_code_iterator FMAXMIN [smax smin])
865
866 ;; Code iterator for variants of vector max and min.
867 (define_code_iterator ADDSUB [plus minus])
868
869 ;; Code iterator for variants of vector saturating binary ops.
870 (define_code_iterator BINQOPS [ss_plus us_plus ss_minus us_minus])
871
872 ;; Code iterator for variants of vector saturating unary ops.
873 (define_code_iterator UNQOPS [ss_neg ss_abs])
874
875 ;; Code iterator for signed variants of vector saturating binary ops.
876 (define_code_iterator SBINQOPS [ss_plus ss_minus])
877
878 ;; Comparison operators for <F>CM.
879 (define_code_iterator COMPARISONS [lt le eq ge gt])
880
881 ;; Unsigned comparison operators.
882 (define_code_iterator UCOMPARISONS [ltu leu geu gtu])
883
884 ;; Unsigned comparison operators.
885 (define_code_iterator FAC_COMPARISONS [lt le ge gt])
886
887 ;; -------------------------------------------------------------------
888 ;; Code Attributes
889 ;; -------------------------------------------------------------------
890 ;; Map rtl objects to optab names
891 (define_code_attr optab [(ashift "ashl")
892 (ashiftrt "ashr")
893 (lshiftrt "lshr")
894 (rotatert "rotr")
895 (sign_extend "extend")
896 (zero_extend "zero_extend")
897 (sign_extract "extv")
898 (zero_extract "extzv")
899 (fix "fix")
900 (unsigned_fix "fixuns")
901 (float "float")
902 (unsigned_float "floatuns")
903 (and "and")
904 (ior "ior")
905 (xor "xor")
906 (not "one_cmpl")
907 (neg "neg")
908 (plus "add")
909 (minus "sub")
910 (ss_plus "qadd")
911 (us_plus "qadd")
912 (ss_minus "qsub")
913 (us_minus "qsub")
914 (ss_neg "qneg")
915 (ss_abs "qabs")
916 (eq "eq")
917 (ne "ne")
918 (lt "lt")
919 (ge "ge")
920 (le "le")
921 (gt "gt")
922 (ltu "ltu")
923 (leu "leu")
924 (geu "geu")
925 (gtu "gtu")])
926
927 ;; For comparison operators we use the FCM* and CM* instructions.
928 ;; As there are no CMLE or CMLT instructions which act on 3 vector
929 ;; operands, we must use CMGE or CMGT and swap the order of the
930 ;; source operands.
931
932 (define_code_attr n_optab [(lt "gt") (le "ge") (eq "eq") (ge "ge") (gt "gt")
933 (ltu "hi") (leu "hs") (geu "hs") (gtu "hi")])
934 (define_code_attr cmp_1 [(lt "2") (le "2") (eq "1") (ge "1") (gt "1")
935 (ltu "2") (leu "2") (geu "1") (gtu "1")])
936 (define_code_attr cmp_2 [(lt "1") (le "1") (eq "2") (ge "2") (gt "2")
937 (ltu "1") (leu "1") (geu "2") (gtu "2")])
938
939 (define_code_attr CMP [(lt "LT") (le "LE") (eq "EQ") (ge "GE") (gt "GT")
940 (ltu "LTU") (leu "LEU") (ne "NE") (geu "GEU")
941 (gtu "GTU")])
942
943 (define_code_attr fix_trunc_optab [(fix "fix_trunc")
944 (unsigned_fix "fixuns_trunc")])
945
946 ;; Optab prefix for sign/zero-extending operations
947 (define_code_attr su_optab [(sign_extend "") (zero_extend "u")
948 (div "") (udiv "u")
949 (fix "") (unsigned_fix "u")
950 (float "s") (unsigned_float "u")
951 (ss_plus "s") (us_plus "u")
952 (ss_minus "s") (us_minus "u")])
953
954 ;; Similar for the instruction mnemonics
955 (define_code_attr shift [(ashift "lsl") (ashiftrt "asr")
956 (lshiftrt "lsr") (rotatert "ror")])
957
958 ;; Map shift operators onto underlying bit-field instructions
959 (define_code_attr bfshift [(ashift "ubfiz") (ashiftrt "sbfx")
960 (lshiftrt "ubfx") (rotatert "extr")])
961
962 ;; Logical operator instruction mnemonics
963 (define_code_attr logical [(and "and") (ior "orr") (xor "eor")])
964
965 ;; Operation names for negate and bitwise complement.
966 (define_code_attr neg_not_op [(neg "neg") (not "not")])
967
968 ;; Similar, but when not(op)
969 (define_code_attr nlogical [(and "bic") (ior "orn") (xor "eon")])
970
971 ;; Sign- or zero-extending data-op
972 (define_code_attr su [(sign_extend "s") (zero_extend "u")
973 (sign_extract "s") (zero_extract "u")
974 (fix "s") (unsigned_fix "u")
975 (div "s") (udiv "u")
976 (smax "s") (umax "u")
977 (smin "s") (umin "u")])
978
979 ;; Emit conditional branch instructions.
980 (define_code_attr bcond [(eq "beq") (ne "bne") (lt "bne") (ge "beq")])
981
982 ;; Emit cbz/cbnz depending on comparison type.
983 (define_code_attr cbz [(eq "cbz") (ne "cbnz") (lt "cbnz") (ge "cbz")])
984
985 ;; Emit inverted cbz/cbnz depending on comparison type.
986 (define_code_attr inv_cb [(eq "cbnz") (ne "cbz") (lt "cbz") (ge "cbnz")])
987
988 ;; Emit tbz/tbnz depending on comparison type.
989 (define_code_attr tbz [(eq "tbz") (ne "tbnz") (lt "tbnz") (ge "tbz")])
990
991 ;; Emit inverted tbz/tbnz depending on comparison type.
992 (define_code_attr inv_tb [(eq "tbnz") (ne "tbz") (lt "tbz") (ge "tbnz")])
993
994 ;; Max/min attributes.
995 (define_code_attr maxmin [(smax "max")
996 (smin "min")
997 (umax "max")
998 (umin "min")])
999
1000 ;; MLA/MLS attributes.
1001 (define_code_attr as [(ss_plus "a") (ss_minus "s")])
1002
1003 ;; Atomic operations
1004 (define_code_attr atomic_optab
1005 [(ior "or") (xor "xor") (and "and") (plus "add") (minus "sub")])
1006
1007 (define_code_attr atomic_op_operand
1008 [(ior "aarch64_logical_operand")
1009 (xor "aarch64_logical_operand")
1010 (and "aarch64_logical_operand")
1011 (plus "aarch64_plus_operand")
1012 (minus "aarch64_plus_operand")])
1013
1014 ;; Constants acceptable for atomic operations.
1015 ;; This definition must appear in this file before the iterators it refers to.
1016 (define_code_attr const_atomic
1017 [(plus "IJ") (minus "IJ")
1018 (xor "<lconst_atomic>") (ior "<lconst_atomic>")
1019 (and "<lconst_atomic>")])
1020
1021 ;; Attribute to describe constants acceptable in atomic logical operations
1022 (define_mode_attr lconst_atomic [(QI "K") (HI "K") (SI "K") (DI "L")])
1023
1024 ;; -------------------------------------------------------------------
1025 ;; Int Iterators.
1026 ;; -------------------------------------------------------------------
1027 (define_int_iterator MAXMINV [UNSPEC_UMAXV UNSPEC_UMINV
1028 UNSPEC_SMAXV UNSPEC_SMINV])
1029
1030 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
1031 UNSPEC_FMAXNMV UNSPEC_FMINNMV])
1032
1033 (define_int_iterator HADDSUB [UNSPEC_SHADD UNSPEC_UHADD
1034 UNSPEC_SRHADD UNSPEC_URHADD
1035 UNSPEC_SHSUB UNSPEC_UHSUB
1036 UNSPEC_SRHSUB UNSPEC_URHSUB])
1037
1038 (define_int_iterator DOTPROD [UNSPEC_SDOT UNSPEC_UDOT])
1039
1040 (define_int_iterator ADDSUBHN [UNSPEC_ADDHN UNSPEC_RADDHN
1041 UNSPEC_SUBHN UNSPEC_RSUBHN])
1042
1043 (define_int_iterator ADDSUBHN2 [UNSPEC_ADDHN2 UNSPEC_RADDHN2
1044 UNSPEC_SUBHN2 UNSPEC_RSUBHN2])
1045
1046 (define_int_iterator FMAXMIN_UNS [UNSPEC_FMAX UNSPEC_FMIN
1047 UNSPEC_FMAXNM UNSPEC_FMINNM])
1048
1049 (define_int_iterator PAUTH_LR_SP [UNSPEC_PACISP UNSPEC_AUTISP])
1050
1051 (define_int_iterator PAUTH_17_16 [UNSPEC_PACI1716 UNSPEC_AUTI1716])
1052
1053 (define_int_iterator VQDMULH [UNSPEC_SQDMULH UNSPEC_SQRDMULH])
1054
1055 (define_int_iterator USSUQADD [UNSPEC_SUQADD UNSPEC_USQADD])
1056
1057 (define_int_iterator SUQMOVN [UNSPEC_SQXTN UNSPEC_UQXTN])
1058
1059 (define_int_iterator VSHL [UNSPEC_SSHL UNSPEC_USHL
1060 UNSPEC_SRSHL UNSPEC_URSHL])
1061
1062 (define_int_iterator VSHLL [UNSPEC_SSHLL UNSPEC_USHLL])
1063
1064 (define_int_iterator VQSHL [UNSPEC_SQSHL UNSPEC_UQSHL
1065 UNSPEC_SQRSHL UNSPEC_UQRSHL])
1066
1067 (define_int_iterator VSRA [UNSPEC_SSRA UNSPEC_USRA
1068 UNSPEC_SRSRA UNSPEC_URSRA])
1069
1070 (define_int_iterator VSLRI [UNSPEC_SSLI UNSPEC_USLI
1071 UNSPEC_SSRI UNSPEC_USRI])
1072
1073
1074 (define_int_iterator VRSHR_N [UNSPEC_SRSHR UNSPEC_URSHR])
1075
1076 (define_int_iterator VQSHL_N [UNSPEC_SQSHLU UNSPEC_SQSHL UNSPEC_UQSHL])
1077
1078 (define_int_iterator VQSHRN_N [UNSPEC_SQSHRUN UNSPEC_SQRSHRUN
1079 UNSPEC_SQSHRN UNSPEC_UQSHRN
1080 UNSPEC_SQRSHRN UNSPEC_UQRSHRN])
1081
1082 (define_int_iterator SQRDMLH_AS [UNSPEC_SQRDMLAH UNSPEC_SQRDMLSH])
1083
1084 (define_int_iterator PERMUTE [UNSPEC_ZIP1 UNSPEC_ZIP2
1085 UNSPEC_TRN1 UNSPEC_TRN2
1086 UNSPEC_UZP1 UNSPEC_UZP2])
1087
1088 (define_int_iterator REVERSE [UNSPEC_REV64 UNSPEC_REV32 UNSPEC_REV16])
1089
1090 (define_int_iterator FRINT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
1091 UNSPEC_FRINTN UNSPEC_FRINTI UNSPEC_FRINTX
1092 UNSPEC_FRINTA])
1093
1094 (define_int_iterator FCVT [UNSPEC_FRINTZ UNSPEC_FRINTP UNSPEC_FRINTM
1095 UNSPEC_FRINTA UNSPEC_FRINTN])
1096
1097 (define_int_iterator FCVT_F2FIXED [UNSPEC_FCVTZS UNSPEC_FCVTZU])
1098 (define_int_iterator FCVT_FIXED2F [UNSPEC_SCVTF UNSPEC_UCVTF])
1099
1100 (define_int_iterator FRECP [UNSPEC_FRECPE UNSPEC_FRECPX])
1101
1102 (define_int_iterator CRC [UNSPEC_CRC32B UNSPEC_CRC32H UNSPEC_CRC32W
1103 UNSPEC_CRC32X UNSPEC_CRC32CB UNSPEC_CRC32CH
1104 UNSPEC_CRC32CW UNSPEC_CRC32CX])
1105
1106 (define_int_iterator CRYPTO_AES [UNSPEC_AESE UNSPEC_AESD])
1107 (define_int_iterator CRYPTO_AESMC [UNSPEC_AESMC UNSPEC_AESIMC])
1108
1109 (define_int_iterator CRYPTO_SHA1 [UNSPEC_SHA1C UNSPEC_SHA1M UNSPEC_SHA1P])
1110
1111 (define_int_iterator CRYPTO_SHA256 [UNSPEC_SHA256H UNSPEC_SHA256H2])
1112
1113 ;; Iterators for atomic operations.
1114
1115 (define_int_iterator ATOMIC_LDOP
1116 [UNSPECV_ATOMIC_LDOP_OR UNSPECV_ATOMIC_LDOP_BIC
1117 UNSPECV_ATOMIC_LDOP_XOR UNSPECV_ATOMIC_LDOP_PLUS])
1118
1119 (define_int_attr atomic_ldop
1120 [(UNSPECV_ATOMIC_LDOP_OR "set") (UNSPECV_ATOMIC_LDOP_BIC "clr")
1121 (UNSPECV_ATOMIC_LDOP_XOR "eor") (UNSPECV_ATOMIC_LDOP_PLUS "add")])
1122
1123 ;; -------------------------------------------------------------------
1124 ;; Int Iterators Attributes.
1125 ;; -------------------------------------------------------------------
1126 (define_int_attr maxmin_uns [(UNSPEC_UMAXV "umax")
1127 (UNSPEC_UMINV "umin")
1128 (UNSPEC_SMAXV "smax")
1129 (UNSPEC_SMINV "smin")
1130 (UNSPEC_FMAX "smax_nan")
1131 (UNSPEC_FMAXNMV "smax")
1132 (UNSPEC_FMAXV "smax_nan")
1133 (UNSPEC_FMIN "smin_nan")
1134 (UNSPEC_FMINNMV "smin")
1135 (UNSPEC_FMINV "smin_nan")
1136 (UNSPEC_FMAXNM "fmax")
1137 (UNSPEC_FMINNM "fmin")])
1138
1139 (define_int_attr maxmin_uns_op [(UNSPEC_UMAXV "umax")
1140 (UNSPEC_UMINV "umin")
1141 (UNSPEC_SMAXV "smax")
1142 (UNSPEC_SMINV "smin")
1143 (UNSPEC_FMAX "fmax")
1144 (UNSPEC_FMAXNMV "fmaxnm")
1145 (UNSPEC_FMAXV "fmax")
1146 (UNSPEC_FMIN "fmin")
1147 (UNSPEC_FMINNMV "fminnm")
1148 (UNSPEC_FMINV "fmin")
1149 (UNSPEC_FMAXNM "fmaxnm")
1150 (UNSPEC_FMINNM "fminnm")])
1151
1152 (define_int_attr sur [(UNSPEC_SHADD "s") (UNSPEC_UHADD "u")
1153 (UNSPEC_SRHADD "sr") (UNSPEC_URHADD "ur")
1154 (UNSPEC_SHSUB "s") (UNSPEC_UHSUB "u")
1155 (UNSPEC_SRHSUB "sr") (UNSPEC_URHSUB "ur")
1156 (UNSPEC_ADDHN "") (UNSPEC_RADDHN "r")
1157 (UNSPEC_SUBHN "") (UNSPEC_RSUBHN "r")
1158 (UNSPEC_ADDHN2 "") (UNSPEC_RADDHN2 "r")
1159 (UNSPEC_SUBHN2 "") (UNSPEC_RSUBHN2 "r")
1160 (UNSPEC_SQXTN "s") (UNSPEC_UQXTN "u")
1161 (UNSPEC_USQADD "us") (UNSPEC_SUQADD "su")
1162 (UNSPEC_SSLI "s") (UNSPEC_USLI "u")
1163 (UNSPEC_SSRI "s") (UNSPEC_USRI "u")
1164 (UNSPEC_USRA "u") (UNSPEC_SSRA "s")
1165 (UNSPEC_URSRA "ur") (UNSPEC_SRSRA "sr")
1166 (UNSPEC_URSHR "ur") (UNSPEC_SRSHR "sr")
1167 (UNSPEC_SQSHLU "s") (UNSPEC_SQSHL "s")
1168 (UNSPEC_UQSHL "u")
1169 (UNSPEC_SQSHRUN "s") (UNSPEC_SQRSHRUN "s")
1170 (UNSPEC_SQSHRN "s") (UNSPEC_UQSHRN "u")
1171 (UNSPEC_SQRSHRN "s") (UNSPEC_UQRSHRN "u")
1172 (UNSPEC_USHL "u") (UNSPEC_SSHL "s")
1173 (UNSPEC_USHLL "u") (UNSPEC_SSHLL "s")
1174 (UNSPEC_URSHL "ur") (UNSPEC_SRSHL "sr")
1175 (UNSPEC_UQRSHL "u") (UNSPEC_SQRSHL "s")
1176 (UNSPEC_SDOT "s") (UNSPEC_UDOT "u")
1177 ])
1178
1179 (define_int_attr r [(UNSPEC_SQDMULH "") (UNSPEC_SQRDMULH "r")
1180 (UNSPEC_SQSHRUN "") (UNSPEC_SQRSHRUN "r")
1181 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1182 (UNSPEC_SQRSHRN "r") (UNSPEC_UQRSHRN "r")
1183 (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1184 (UNSPEC_SQRSHL "r")(UNSPEC_UQRSHL "r")
1185 ])
1186
1187 (define_int_attr lr [(UNSPEC_SSLI "l") (UNSPEC_USLI "l")
1188 (UNSPEC_SSRI "r") (UNSPEC_USRI "r")])
1189
1190 (define_int_attr u [(UNSPEC_SQSHLU "u") (UNSPEC_SQSHL "") (UNSPEC_UQSHL "")
1191 (UNSPEC_SQSHRUN "u") (UNSPEC_SQRSHRUN "u")
1192 (UNSPEC_SQSHRN "") (UNSPEC_UQSHRN "")
1193 (UNSPEC_SQRSHRN "") (UNSPEC_UQRSHRN "")])
1194
1195 (define_int_attr addsub [(UNSPEC_SHADD "add")
1196 (UNSPEC_UHADD "add")
1197 (UNSPEC_SRHADD "add")
1198 (UNSPEC_URHADD "add")
1199 (UNSPEC_SHSUB "sub")
1200 (UNSPEC_UHSUB "sub")
1201 (UNSPEC_SRHSUB "sub")
1202 (UNSPEC_URHSUB "sub")
1203 (UNSPEC_ADDHN "add")
1204 (UNSPEC_SUBHN "sub")
1205 (UNSPEC_RADDHN "add")
1206 (UNSPEC_RSUBHN "sub")
1207 (UNSPEC_ADDHN2 "add")
1208 (UNSPEC_SUBHN2 "sub")
1209 (UNSPEC_RADDHN2 "add")
1210 (UNSPEC_RSUBHN2 "sub")])
1211
1212 (define_int_attr offsetlr [(UNSPEC_SSLI "") (UNSPEC_USLI "")
1213 (UNSPEC_SSRI "offset_")
1214 (UNSPEC_USRI "offset_")])
1215
1216 ;; Standard pattern names for floating-point rounding instructions.
1217 (define_int_attr frint_pattern [(UNSPEC_FRINTZ "btrunc")
1218 (UNSPEC_FRINTP "ceil")
1219 (UNSPEC_FRINTM "floor")
1220 (UNSPEC_FRINTI "nearbyint")
1221 (UNSPEC_FRINTX "rint")
1222 (UNSPEC_FRINTA "round")
1223 (UNSPEC_FRINTN "frintn")])
1224
1225 ;; frint suffix for floating-point rounding instructions.
1226 (define_int_attr frint_suffix [(UNSPEC_FRINTZ "z") (UNSPEC_FRINTP "p")
1227 (UNSPEC_FRINTM "m") (UNSPEC_FRINTI "i")
1228 (UNSPEC_FRINTX "x") (UNSPEC_FRINTA "a")
1229 (UNSPEC_FRINTN "n")])
1230
1231 (define_int_attr fcvt_pattern [(UNSPEC_FRINTZ "btrunc") (UNSPEC_FRINTA "round")
1232 (UNSPEC_FRINTP "ceil") (UNSPEC_FRINTM "floor")
1233 (UNSPEC_FRINTN "frintn")])
1234
1235 (define_int_attr fcvt_fixed_insn [(UNSPEC_SCVTF "scvtf")
1236 (UNSPEC_UCVTF "ucvtf")
1237 (UNSPEC_FCVTZS "fcvtzs")
1238 (UNSPEC_FCVTZU "fcvtzu")])
1239
1240 ;; Pointer authentication mnemonic prefix.
1241 (define_int_attr pauth_mnem_prefix [(UNSPEC_PACISP "paci")
1242 (UNSPEC_AUTISP "auti")
1243 (UNSPEC_PACI1716 "paci")
1244 (UNSPEC_AUTI1716 "auti")])
1245
1246 ;; Pointer authentication HINT number for NOP space instructions using A Key.
1247 (define_int_attr pauth_hint_num_a [(UNSPEC_PACISP "25")
1248 (UNSPEC_AUTISP "29")
1249 (UNSPEC_PACI1716 "8")
1250 (UNSPEC_AUTI1716 "12")])
1251
1252 (define_int_attr perm_insn [(UNSPEC_ZIP1 "zip") (UNSPEC_ZIP2 "zip")
1253 (UNSPEC_TRN1 "trn") (UNSPEC_TRN2 "trn")
1254 (UNSPEC_UZP1 "uzp") (UNSPEC_UZP2 "uzp")])
1255
1256 ; op code for REV instructions (size within which elements are reversed).
1257 (define_int_attr rev_op [(UNSPEC_REV64 "64") (UNSPEC_REV32 "32")
1258 (UNSPEC_REV16 "16")])
1259
1260 (define_int_attr perm_hilo [(UNSPEC_ZIP1 "1") (UNSPEC_ZIP2 "2")
1261 (UNSPEC_TRN1 "1") (UNSPEC_TRN2 "2")
1262 (UNSPEC_UZP1 "1") (UNSPEC_UZP2 "2")])
1263
1264 (define_int_attr frecp_suffix [(UNSPEC_FRECPE "e") (UNSPEC_FRECPX "x")])
1265
1266 (define_int_attr crc_variant [(UNSPEC_CRC32B "crc32b") (UNSPEC_CRC32H "crc32h")
1267 (UNSPEC_CRC32W "crc32w") (UNSPEC_CRC32X "crc32x")
1268 (UNSPEC_CRC32CB "crc32cb") (UNSPEC_CRC32CH "crc32ch")
1269 (UNSPEC_CRC32CW "crc32cw") (UNSPEC_CRC32CX "crc32cx")])
1270
1271 (define_int_attr crc_mode [(UNSPEC_CRC32B "QI") (UNSPEC_CRC32H "HI")
1272 (UNSPEC_CRC32W "SI") (UNSPEC_CRC32X "DI")
1273 (UNSPEC_CRC32CB "QI") (UNSPEC_CRC32CH "HI")
1274 (UNSPEC_CRC32CW "SI") (UNSPEC_CRC32CX "DI")])
1275
1276 (define_int_attr aes_op [(UNSPEC_AESE "e") (UNSPEC_AESD "d")])
1277 (define_int_attr aesmc_op [(UNSPEC_AESMC "mc") (UNSPEC_AESIMC "imc")])
1278
1279 (define_int_attr sha1_op [(UNSPEC_SHA1C "c") (UNSPEC_SHA1P "p")
1280 (UNSPEC_SHA1M "m")])
1281
1282 (define_int_attr sha256_op [(UNSPEC_SHA256H "") (UNSPEC_SHA256H2 "2")])
1283
1284 (define_int_attr rdma_as [(UNSPEC_SQRDMLAH "a") (UNSPEC_SQRDMLSH "s")])