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comparison gcc/config/arc/arc700.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
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68:561a7518be6b 111:04ced10e8804
1 ;; DFA scheduling description of the Synopsys DesignWare ARC700 cpu
2 ;; for GNU C compiler
3 ;; Comments and Support For ARC700 instructions added by
4 ;; Saurabh Verma (saurabh.verma@codito.com)
5 ;; Ramana Radhakrishnan(ramana.radhakrishnan@codito.com)
6 ;; Factoring out and improvement of ARC700 Scheduling by
7 ;; Joern Rennecke (joern.rennecke@embecosm.com)
8 ;; Copyright (C) 2006-2017 Free Software Foundation, Inc.
9
10 ;; This file is part of GCC.
11
12 ;; GCC is free software; you can redistribute it and/or modify
13 ;; it under the terms of the GNU General Public License as published by
14 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; any later version.
16
17 ;; GCC is distributed in the hope that it will be useful,
18 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
19 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 ;; GNU General Public License for more details.
21
22 ;; You should have received a copy of the GNU General Public License
23 ;; along with GCC; see the file COPYING3. If not see
24 ;; <http://www.gnu.org/licenses/>.
25
26 (define_automaton "ARC700")
27
28 ;; aux to be added here
29 (define_cpu_unit "core, dmp, write_port, dmp_write_port, multiplier, issue, blockage, simd_unit" "ARC700")
30
31 (define_insn_reservation "core_insn_DI" 2
32 (and (eq_attr "tune_arc700" "true")
33 (eq_attr "type" "unary, move, cmove, binary")
34 (match_operand:DI 0 "" ""))
35 "issue+core, issue+core+write_port, write_port")
36
37 (define_insn_reservation "lr" 2
38 (and (eq_attr "tune_arc700" "true")
39 (eq_attr "type" "lr"))
40 "issue+blockage, blockage*2, write_port")
41
42 (define_insn_reservation "sr" 1
43 (and (eq_attr "tune_arc700" "true")
44 (eq_attr "type" "sr"))
45 "issue+dmp_write_port+blockage, blockage*9")
46
47 (define_insn_reservation "core_insn" 1
48 (and (eq_attr "tune_arc700" "true")
49 (eq_attr "type" "unary, move, binary"))
50 "issue+core, nothing, write_port")
51
52 (define_insn_reservation "cmove" 1
53 (and (eq_attr "tune_arc700" "true")
54 (eq_attr "type" "cmove"))
55 "issue+core, nothing, write_port")
56
57 (define_insn_reservation "cc_arith" 1
58 (and (eq_attr "tune_arc700" "true")
59 (eq_attr "type" "cc_arith"))
60 "issue+core, nothing, write_port")
61
62 (define_insn_reservation "two_cycle_core_insn" 2
63 (and (eq_attr "tune_arc700" "true")
64 (eq_attr "type" "two_cycle_core"))
65 "issue+core, nothing, write_port")
66
67 (define_insn_reservation "divaw_insn" 2
68 (and (eq_attr "tune_arc700" "true")
69 (eq_attr "type" "divaw"))
70 "issue+core, nothing, write_port")
71
72 (define_insn_reservation "shift_insn" 2
73 (and (eq_attr "tune_arc700" "true")
74 (eq_attr "type" "shift"))
75 "issue+core, nothing, write_port")
76
77 ; Latency from flag setters to arithmetic with carry is 3.
78 (define_insn_reservation "compare_700" 3
79 (and (eq_attr "tune_arc700" "true")
80 (eq_attr "type" "compare"))
81 "issue+core, nothing, write_port")
82
83 ; Assume here the branch is predicted correctly and has a delay slot insn
84 ; or is properly unaligned.
85 (define_insn_reservation "branch_700" 1
86 (and (eq_attr "tune_arc700" "true")
87 (eq_attr "type" "compare"))
88 "issue+core, nothing, write_port")
89
90 ; TODOs: is this correct ??
91 (define_insn_reservation "multi_DI" 10
92 (and (eq_attr "tune_arc700" "true")
93 (eq_attr "type" "multi")
94 (match_operand:DI 0 "" ""))
95 "issue+multiplier, multiplier*2,issue+multiplier, multiplier*2,
96 nothing,write_port,nothing*2, write_port")
97
98 (define_insn_reservation "umulti_DI" 9
99 (and (eq_attr "tune_arc700" "true")
100 (eq_attr "type" "umulti")
101 (match_operand:DI 0 "" ""))
102 "issue+multiplier, multiplier,issue+multiplier, multiplier*2,
103 write_port,nothing*3, write_port")
104
105 (define_insn_reservation "umulti_xmac" 5
106 (and (eq_attr "tune_arc700" "true")
107 (eq_attr "type" "umulti"))
108 "issue+multiplier, multiplier, nothing*3, write_port")
109
110 ; latency of mpyu is lower than mpy / mpyh / mpyhu
111 (define_insn_reservation "umulti_std" 6
112 (and (eq_attr "tune_arc700" "true")
113 (eq_attr "type" "umulti"))
114 "issue+multiplier, multiplier*3, nothing*2, write_port")
115
116 ;; arc700 xmac multiplier
117 (define_insn_reservation "multi_xmac" 5
118 (and (eq_attr "tune" "arc700_4_2_xmac")
119 (eq_attr "type" "multi"))
120 "issue+multiplier,multiplier,nothing*3,write_port")
121
122 ; arc700 standard multiplier
123 (define_insn_reservation "multi_std" 7
124 (and (eq_attr "tune" "arc700_4_2_std")
125 (eq_attr "type" "multi"))
126 "issue+multiplier,multiplier*4,nothing*2,write_port")
127
128 ;(define_insn_reservation "multi_SI" 7
129 ; (eq_attr "type" "multi")
130 ; "issue+multiplier, multiplier*2, nothing*4, write_port")
131
132 ; There is no multiplier -> multiplier bypass except for the
133 ; mac -> mac dependency on the accumulator.
134
135 ; divaw -> divaw latency is 1 cycle
136 (define_bypass 1 "divaw_insn" "divaw_insn")
137
138 (define_bypass 1 "compare_700" "branch_700,core_insn,data_store,data_load")
139
140 ; we could shedule the cmove immediately after the compare, but then
141 ; the cmove would have higher latency... so just keep the cmove apart
142 ; from the compare.
143 (define_bypass 2 "compare_700" "cmove")
144
145 ; no functional unit runs when blockage is reserved
146 (exclusion_set "blockage" "core, multiplier")
147
148 (define_insn_reservation "data_load_DI" 4
149 (and (eq_attr "tune_arc700" "true")
150 (eq_attr "type" "load")
151 (match_operand:DI 0 "" ""))
152 "issue+dmp, issue+dmp, dmp_write_port, dmp_write_port")
153
154 (define_insn_reservation "data_load" 3
155 (and (eq_attr "tune_arc700" "true")
156 (eq_attr "type" "load")
157 (not (match_operand:DI 0 "" "")))
158 "issue+dmp, nothing, dmp_write_port")
159
160 (define_insn_reservation "data_store_DI" 2
161 (and (eq_attr "tune_arc700" "true")
162 (eq_attr "type" "store")
163 (match_operand:DI 0 "" ""))
164 "issue+dmp_write_port, issue+dmp_write_port")
165
166 (define_insn_reservation "data_store" 1
167 (and (eq_attr "tune_arc700" "true")
168 (eq_attr "type" "store")
169 (not (match_operand:DI 0 "" "")))
170 "issue+dmp_write_port")
171
172 (define_bypass 3 "data_store" "data_load" "arc_store_addr_hazard_p")