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comparison gcc/config/arm/aout.h @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
comparison
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68:561a7518be6b 111:04ced10e8804
1 /* Definitions of target machine for GNU compiler, for ARM with a.out 1 /* Definitions of target machine for GNU compiler, for ARM with a.out
2 Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2004, 2007, 2008, 2010 2 Copyright (C) 1995-2017 Free Software Foundation, Inc.
3 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rearnsha@armltd.co.uk). 3 Contributed by Richard Earnshaw (rearnsha@armltd.co.uk).
5 4
6 This file is part of GCC. 5 This file is part of GCC.
7 6
8 GCC is free software; you can redistribute it and/or modify it 7 GCC is free software; you can redistribute it and/or modify it
13 GCC is distributed in the hope that it will be useful, but WITHOUT 12 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details. 15 License for more details.
17 16
18 You should have received a copy of the GNU General Public License 17 Under Section 7 of GPL version 3, you are granted additional
19 along with GCC; see the file COPYING3. If not see 18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
20
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
20 <http://www.gnu.org/licenses/>. */ 24 <http://www.gnu.org/licenses/>. */
21 25
22 #ifndef ASM_APP_ON 26 #ifndef ASM_APP_ON
23 #define ASM_APP_ON "" 27 #define ASM_APP_ON ""
24 #endif 28 #endif
49 /* The assembler's names for the registers. Note that the ?xx registers are 53 /* The assembler's names for the registers. Note that the ?xx registers are
50 there so that VFPv3/NEON registers D16-D31 have the same spacing as D0-D15 54 there so that VFPv3/NEON registers D16-D31 have the same spacing as D0-D15
51 (each of which is overlaid on two S registers), although there are no 55 (each of which is overlaid on two S registers), although there are no
52 actual single-precision registers which correspond to D16-D31. */ 56 actual single-precision registers which correspond to D16-D31. */
53 #ifndef REGISTER_NAMES 57 #ifndef REGISTER_NAMES
54 #define REGISTER_NAMES \ 58 #define REGISTER_NAMES \
55 { \ 59 { \
56 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 60 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
57 "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \ 61 "r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc", \
58 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 62 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
59 "cc", "sfp", "afp", \ 63 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", \
60 "mv0", "mv1", "mv2", "mv3", \ 64 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", \
61 "mv4", "mv5", "mv6", "mv7", \ 65 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", \
62 "mv8", "mv9", "mv10", "mv11", \ 66 "d16", "?16", "d17", "?17", "d18", "?18", "d19", "?19", \
63 "mv12", "mv13", "mv14", "mv15", \ 67 "d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23", \
64 "wcgr0", "wcgr1", "wcgr2", "wcgr3", \ 68 "d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27", \
65 "wr0", "wr1", "wr2", "wr3", \ 69 "d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31", \
66 "wr4", "wr5", "wr6", "wr7", \ 70 "wr0", "wr1", "wr2", "wr3", \
67 "wr8", "wr9", "wr10", "wr11", \ 71 "wr4", "wr5", "wr6", "wr7", \
68 "wr12", "wr13", "wr14", "wr15", \ 72 "wr8", "wr9", "wr10", "wr11", \
69 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \ 73 "wr12", "wr13", "wr14", "wr15", \
70 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", \ 74 "wcgr0", "wcgr1", "wcgr2", "wcgr3", \
71 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", \ 75 "cc", "vfpcc", "sfp", "afp" \
72 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", \
73 "d16", "?16", "d17", "?17", "d18", "?18", "d19", "?19", \
74 "d20", "?20", "d21", "?21", "d22", "?22", "d23", "?23", \
75 "d24", "?24", "d25", "?25", "d26", "?26", "d27", "?27", \
76 "d28", "?28", "d29", "?29", "d30", "?30", "d31", "?31", \
77 "vfpcc" \
78 } 76 }
79 #endif 77 #endif
80 78
81 #ifndef ADDITIONAL_REGISTER_NAMES 79 #ifndef ADDITIONAL_REGISTER_NAMES
82 #define ADDITIONAL_REGISTER_NAMES \ 80 #define ADDITIONAL_REGISTER_NAMES \
89 {"v2", 5}, \ 87 {"v2", 5}, \
90 {"v3", 6}, \ 88 {"v3", 6}, \
91 {"v4", 7}, \ 89 {"v4", 7}, \
92 {"v5", 8}, \ 90 {"v5", 8}, \
93 {"v6", 9}, \ 91 {"v6", 9}, \
94 {"rfp", 9}, /* Gcc used to call it this */ \ 92 {"rfp", 9}, /* Historical. */ \
95 {"sb", 9}, \ 93 {"sb", 9}, /* Historical. */ \
96 {"v7", 10}, \ 94 {"v7", 10}, \
97 {"r10", 10}, /* sl */ \ 95 {"sl", 10}, /* Historical. */ \
98 {"r11", 11}, /* fp */ \ 96 {"r11", 11}, /* fp */ \
99 {"r12", 12}, /* ip */ \ 97 {"r12", 12}, /* ip */ \
100 {"r13", 13}, /* sp */ \ 98 {"r13", 13}, /* sp */ \
101 {"r14", 14}, /* lr */ \ 99 {"r14", 14}, /* lr */ \
102 {"r15", 15}, /* pc */ \ 100 {"r15", 15} /* pc */ \
103 {"mvf0", 27}, \
104 {"mvf1", 28}, \
105 {"mvf2", 29}, \
106 {"mvf3", 30}, \
107 {"mvf4", 31}, \
108 {"mvf5", 32}, \
109 {"mvf6", 33}, \
110 {"mvf7", 34}, \
111 {"mvf8", 35}, \
112 {"mvf9", 36}, \
113 {"mvf10", 37}, \
114 {"mvf11", 38}, \
115 {"mvf12", 39}, \
116 {"mvf13", 40}, \
117 {"mvf14", 41}, \
118 {"mvf15", 42}, \
119 {"mvd0", 27}, \
120 {"mvd1", 28}, \
121 {"mvd2", 29}, \
122 {"mvd3", 30}, \
123 {"mvd4", 31}, \
124 {"mvd5", 32}, \
125 {"mvd6", 33}, \
126 {"mvd7", 34}, \
127 {"mvd8", 35}, \
128 {"mvd9", 36}, \
129 {"mvd10", 37}, \
130 {"mvd11", 38}, \
131 {"mvd12", 39}, \
132 {"mvd13", 40}, \
133 {"mvd14", 41}, \
134 {"mvd15", 42}, \
135 {"mvfx0", 27}, \
136 {"mvfx1", 28}, \
137 {"mvfx2", 29}, \
138 {"mvfx3", 30}, \
139 {"mvfx4", 31}, \
140 {"mvfx5", 32}, \
141 {"mvfx6", 33}, \
142 {"mvfx7", 34}, \
143 {"mvfx8", 35}, \
144 {"mvfx9", 36}, \
145 {"mvfx10", 37}, \
146 {"mvfx11", 38}, \
147 {"mvfx12", 39}, \
148 {"mvfx13", 40}, \
149 {"mvfx14", 41}, \
150 {"mvfx15", 42}, \
151 {"mvdx0", 27}, \
152 {"mvdx1", 28}, \
153 {"mvdx2", 29}, \
154 {"mvdx3", 30}, \
155 {"mvdx4", 31}, \
156 {"mvdx5", 32}, \
157 {"mvdx6", 33}, \
158 {"mvdx7", 34}, \
159 {"mvdx8", 35}, \
160 {"mvdx9", 36}, \
161 {"mvdx10", 37}, \
162 {"mvdx11", 38}, \
163 {"mvdx12", 39}, \
164 {"mvdx13", 40}, \
165 {"mvdx14", 41}, \
166 {"mvdx15", 42} \
167 } 101 }
168 #endif 102 #endif
169 103
170 #ifndef OVERLAPPING_REGISTER_NAMES 104 #ifndef OVERLAPPING_REGISTER_NAMES
171 #define OVERLAPPING_REGISTER_NAMES \ 105 #define OVERLAPPING_REGISTER_NAMES \
172 { \ 106 { \
173 {"d0", 63, 2}, \ 107 {"d0", FIRST_VFP_REGNUM + 0, 2}, \
174 {"d1", 65, 2}, \ 108 {"d1", FIRST_VFP_REGNUM + 2, 2}, \
175 {"d2", 67, 2}, \ 109 {"d2", FIRST_VFP_REGNUM + 4, 2}, \
176 {"d3", 69, 2}, \ 110 {"d3", FIRST_VFP_REGNUM + 6, 2}, \
177 {"d4", 71, 2}, \ 111 {"d4", FIRST_VFP_REGNUM + 8, 2}, \
178 {"d5", 73, 2}, \ 112 {"d5", FIRST_VFP_REGNUM + 10, 2}, \
179 {"d6", 75, 2}, \ 113 {"d6", FIRST_VFP_REGNUM + 12, 2}, \
180 {"d7", 77, 2}, \ 114 {"d7", FIRST_VFP_REGNUM + 14, 2}, \
181 {"d8", 79, 2}, \ 115 {"d8", FIRST_VFP_REGNUM + 16, 2}, \
182 {"d9", 81, 2}, \ 116 {"d9", FIRST_VFP_REGNUM + 18, 2}, \
183 {"d10", 83, 2}, \ 117 {"d10", FIRST_VFP_REGNUM + 20, 2}, \
184 {"d11", 85, 2}, \ 118 {"d11", FIRST_VFP_REGNUM + 22, 2}, \
185 {"d12", 87, 2}, \ 119 {"d12", FIRST_VFP_REGNUM + 24, 2}, \
186 {"d13", 89, 2}, \ 120 {"d13", FIRST_VFP_REGNUM + 26, 2}, \
187 {"d14", 91, 2}, \ 121 {"d14", FIRST_VFP_REGNUM + 28, 2}, \
188 {"d15", 93, 2}, \ 122 {"d15", FIRST_VFP_REGNUM + 30, 2}, \
189 {"q0", 63, 4}, \ 123 {"q0", FIRST_VFP_REGNUM + 0, 4}, \
190 {"q1", 67, 4}, \ 124 {"q1", FIRST_VFP_REGNUM + 4, 4}, \
191 {"q2", 71, 4}, \ 125 {"q2", FIRST_VFP_REGNUM + 8, 4}, \
192 {"q3", 75, 4}, \ 126 {"q3", FIRST_VFP_REGNUM + 12, 4}, \
193 {"q4", 79, 4}, \ 127 {"q4", FIRST_VFP_REGNUM + 16, 4}, \
194 {"q5", 83, 4}, \ 128 {"q5", FIRST_VFP_REGNUM + 20, 4}, \
195 {"q6", 87, 4}, \ 129 {"q6", FIRST_VFP_REGNUM + 24, 4}, \
196 {"q7", 91, 4}, \ 130 {"q7", FIRST_VFP_REGNUM + 28, 4}, \
197 {"q8", 95, 4}, \ 131 {"q8", FIRST_VFP_REGNUM + 32, 4}, \
198 {"q9", 99, 4}, \ 132 {"q9", FIRST_VFP_REGNUM + 36, 4}, \
199 {"q10", 103, 4}, \ 133 {"q10", FIRST_VFP_REGNUM + 40, 4}, \
200 {"q11", 107, 4}, \ 134 {"q11", FIRST_VFP_REGNUM + 44, 4}, \
201 {"q12", 111, 4}, \ 135 {"q12", FIRST_VFP_REGNUM + 48, 4}, \
202 {"q13", 115, 4}, \ 136 {"q13", FIRST_VFP_REGNUM + 52, 4}, \
203 {"q14", 119, 4}, \ 137 {"q14", FIRST_VFP_REGNUM + 56, 4}, \
204 {"q15", 123, 4} \ 138 {"q15", FIRST_VFP_REGNUM + 60, 4} \
205 } 139 }
206 #endif 140 #endif
207 141
208 #ifndef NO_DOLLAR_IN_LABEL 142 #ifndef NO_DOLLAR_IN_LABEL
209 #define NO_DOLLAR_IN_LABEL 1 143 #define NO_DOLLAR_IN_LABEL 1
260 { \ 194 { \
261 if (flag_pic || optimize_size) \ 195 if (flag_pic || optimize_size) \
262 { \ 196 { \
263 switch (GET_MODE(body)) \ 197 switch (GET_MODE(body)) \
264 { \ 198 { \
265 case QImode: \ 199 case E_QImode: \
266 asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LL%d)/2\n", \ 200 asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LL%d)/2\n", \
267 VALUE, REL); \ 201 VALUE, REL); \
268 break; \ 202 break; \
269 case HImode: /* TBH */ \ 203 case E_HImode: /* TBH */ \
270 asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LL%d)/2\n", \ 204 asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LL%d)/2\n", \
271 VALUE, REL); \ 205 VALUE, REL); \
272 break; \ 206 break; \
273 case SImode: \ 207 case E_SImode: \
274 asm_fprintf (STREAM, "\t.word\t%LL%d-%LL%d\n", \ 208 asm_fprintf (STREAM, "\t.word\t%LL%d-%LL%d\n", \
275 VALUE, REL); \ 209 VALUE, REL); \
276 break; \ 210 break; \
277 default: \ 211 default: \
278 gcc_unreachable(); \ 212 gcc_unreachable(); \
283 } \ 217 } \
284 else /* Thumb-2 */ \ 218 else /* Thumb-2 */ \
285 { \ 219 { \
286 switch (GET_MODE(body)) \ 220 switch (GET_MODE(body)) \
287 { \ 221 { \
288 case QImode: /* TBB */ \ 222 case E_QImode: /* TBB */ \
289 asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LL%d)/2\n", \ 223 asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LL%d)/2\n", \
290 VALUE, REL); \ 224 VALUE, REL); \
291 break; \ 225 break; \
292 case HImode: /* TBH */ \ 226 case E_HImode: /* TBH */ \
293 asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LL%d)/2\n", \ 227 asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LL%d)/2\n", \
294 VALUE, REL); \ 228 VALUE, REL); \
295 break; \ 229 break; \
296 case SImode: \ 230 case E_SImode: \
297 if (flag_pic) \ 231 if (flag_pic) \
298 asm_fprintf (STREAM, "\t.word\t%LL%d+1-%LL%d\n", VALUE, REL); \ 232 asm_fprintf (STREAM, "\t.word\t%LL%d+1-%LL%d\n", VALUE, REL); \
299 else \ 233 else \
300 asm_fprintf (STREAM, "\t.word\t%LL%d+1\n", VALUE); \ 234 asm_fprintf (STREAM, "\t.word\t%LL%d+1\n", VALUE); \
301 break; \ 235 break; \
364 #ifndef ASM_OUTPUT_ALIGNED_BSS 298 #ifndef ASM_OUTPUT_ALIGNED_BSS
365 #define ASM_OUTPUT_ALIGNED_BSS(STREAM, DECL, NAME, SIZE, ALIGN) \ 299 #define ASM_OUTPUT_ALIGNED_BSS(STREAM, DECL, NAME, SIZE, ALIGN) \
366 asm_output_aligned_bss (STREAM, DECL, NAME, SIZE, ALIGN) 300 asm_output_aligned_bss (STREAM, DECL, NAME, SIZE, ALIGN)
367 #endif 301 #endif
368 302
369 /* Output a #ident directive. */
370 #ifndef ASM_OUTPUT_IDENT
371 #define ASM_OUTPUT_IDENT(STREAM,STRING) \
372 asm_fprintf (STREAM, "%@ - - - ident %s\n", STRING)
373 #endif
374
375 #ifndef ASM_COMMENT_START 303 #ifndef ASM_COMMENT_START
376 #define ASM_COMMENT_START "@" 304 #define ASM_COMMENT_START "@"
377 #endif 305 #endif
378 306
379 /* This works for GAS and some other assemblers. */ 307 /* This works for GAS and some other assemblers. */