CbC/CbC_gcc: gcc/config/arm/arm1020e.md comparison

comparison gcc/config/arm/arm1020e.md @ 111:04ced10e8804

gcc 7

author	kono
date	Fri, 27 Oct 2017 22:46:09 +0900
parents	a06113de4d67
children	84e7813d76e9

comparison

equal deleted inserted replaced

-:561a7518be6b
+:04ced10e8804
 ;; ARM 1020E & ARM 1022E Pipeline Description
-;; Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
+;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
 ;; Contributed by Richard Earnshaw (richard.earnshaw@arm.com)
 ;;
 ;; This file is part of GCC.
 ;;
 ;; GCC is free software; you can redistribute it and/or modify it
 ;; ALU Instructions
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; ALU instructions require three cycles to execute, and use the ALU
 ;; pipeline in each of the three stages.  The results are available
-;; after the execute stage stage has finished.
+;; after the execute stage has finished.
 ;;
 ;; If the destination register is the PC, the pipelines are stalled
 ;; for several cycles.  That case is not modeled here.
 ;; ALU operations with no shifted operand
 (define_insn_reservation "1020alu_op" 1
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "type" "alu"))
+(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
+alu_sreg,alus_sreg,logic_reg,logics_reg,\
+adc_imm,adcs_imm,adc_reg,adcs_reg,\
+adr,bfm,rev,\
+shift_imm,shift_reg,\
+mov_imm,mov_reg,mvn_imm,mvn_reg,\
+multiple,no_insn"))
 "1020a_e,1020a_m,1020a_w")
 ;; ALU operations with a shift-by-constant operand
 (define_insn_reservation "1020alu_shift_op" 1
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "type" "alu_shift"))
+(eq_attr "type" "alu_shift_imm,alus_shift_imm,\
+logic_shift_imm,logics_shift_imm,\
+extend,mov_shift,mvn_shift"))
 "1020a_e,1020a_m,1020a_w")
 ;; ALU operations with a shift-by-register operand
 ;; These really stall in the decoder, in order to read
 ;; the shift value in a second cycle. Pretend we take two cycles in
 ;; the execute stage.
 (define_insn_reservation "1020alu_shift_reg_op" 2
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "type" "alu_shift_reg"))
+(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
+logic_shift_reg,logics_shift_reg,\
+mov_shift_reg,mvn_shift_reg"))
 "1020a_e*2,1020a_m,1020a_w")
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Multiplication Instructions
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; The result of the "smul" and "smulw" instructions is not available
 ;; until after the memory stage.
 (define_insn_reservation "1020mult1" 2
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "insn" "smulxy,smulwy"))
+(eq_attr "type" "smulxy,smulwy"))
 "1020a_e,1020a_m,1020a_w")
 ;; The "smlaxy" and "smlawx" instructions require two iterations through
 ;; the execute stage; the result is available immediately following
 ;; the execute stage.
 (define_insn_reservation "1020mult2" 2
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "insn" "smlaxy,smlalxy,smlawx"))
+(eq_attr "type" "smlaxy,smlalxy,smlawx"))
 "1020a_e*2,1020a_m,1020a_w")
 ;; The "smlalxy", "mul", and "mla" instructions require two iterations
 ;; through the execute stage; the result is not available until after
 ;; the memory stage.
 (define_insn_reservation "1020mult3" 3
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "insn" "smlalxy,mul,mla"))
+(eq_attr "type" "smlalxy,mul,mla"))
 "1020a_e*2,1020a_m,1020a_w")
 ;; The "muls" and "mlas" instructions loop in the execute stage for
 ;; four iterations in order to set the flags.  The value result is
 ;; available after three iterations.
 (define_insn_reservation "1020mult4" 3
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "insn" "muls,mlas"))
+(eq_attr "type" "muls,mlas"))
 "1020a_e*4,1020a_m,1020a_w")
 ;; Long multiply instructions that produce two registers of
 ;; output (such as umull) make their results available in two cycles;
 ;; the least significant word is available before the most significant
 ;; The "umull", "umlal", "smull", and "smlal" instructions all take
 ;; three iterations through the execute cycle, and make their results
 ;; available after the memory cycle.
 (define_insn_reservation "1020mult5" 4
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "insn" "umull,umlal,smull,smlal"))
+(eq_attr "type" "umull,umlal,smull,smlal"))
 "1020a_e*3,1020a_m,1020a_w")
 ;; The "umulls", "umlals", "smulls", and "smlals" instructions loop in
 ;; the execute stage for five iterations in order to set the flags.
 ;; The value result is available after four iterations.
 (define_insn_reservation "1020mult6" 4
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "insn" "umulls,umlals,smulls,smlals"))
+(eq_attr "type" "umulls,umlals,smulls,smlals"))
 "1020a_e*5,1020a_m,1020a_w")
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Load/Store Instructions
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; with LSL of zero.  The remainder take 1 cycle to execute.
 ;; For 4byte loads there is a bypass from the load stage
 (define_insn_reservation "1020load1_op" 2
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "type" "load_byte,load1"))
+(eq_attr "type" "load_byte,load_4"))
 "1020a_e+1020l_e,1020l_m,1020l_w")
 (define_insn_reservation "1020store1_op" 0
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "type" "store1"))
+(eq_attr "type" "store_4"))
 "1020a_e+1020l_e,1020l_m,1020l_w")
 ;; A load's result can be stored by an immediately following store
 (define_bypass 1 "1020load1_op" "1020store1_op" "arm_no_early_store_addr_dep")
 ;; As with ALU operations, if one of the destination registers is the
 ;; PC, there are additional stalls; that is not modeled.
 (define_insn_reservation "1020load2_op" 2
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "type" "load2"))
+(eq_attr "type" "load_8"))
 "1020a_e+1020l_e,1020l_m,1020l_w")
 (define_insn_reservation "1020store2_op" 0
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "type" "store2"))
+(eq_attr "type" "store_8"))
 "1020a_e+1020l_e,1020l_m,1020l_w")
 (define_insn_reservation "1020load34_op" 3
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "type" "load3,load4"))
+(eq_attr "type" "load_12,load_16"))
 "1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
 (define_insn_reservation "1020store34_op" 0
 (and (eq_attr "tune" "arm1020e,arm1022e")
-(eq_attr "type" "store3,store4"))
+(eq_attr "type" "store_12,store_16"))
 "1020a_e+1020l_e,1020l_e+1020l_m,1020l_m,1020l_w")
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Branch and Call Instructions
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 (define_insn_reservation "1020branch_op" 0
 (and (eq_attr "tune" "arm1020e,arm1022e")
 (eq_attr "type" "branch"))
 "1020a_e")
-;; The latency for a call is not predictable.  Therefore, we use 32 as
+;; The latency for a call is not predictable.  Therefore, we model as blocking
-;; roughly equivalent to positive infinity.
+;; execution for a number of cycles but we can't do anything more accurate
+;; than that.
 (define_insn_reservation "1020call_op" 32
 (and (eq_attr "tune" "arm1020e,arm1022e")
 (eq_attr "type" "call"))
-"1020a_e*32")
+"1020a_e*4")
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; VFP
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Note, no instruction can issue to the VFP if the core is stalled in the
 ;; first execute state.  We model this by using 1020a_e in the first cycle.
 (define_insn_reservation "v10_ffarith" 5
 (and (eq_attr "vfp10" "yes")
-(eq_attr "type" "fcpys,ffariths,ffarithd,fcmps,fcmpd"))
+(eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd"))
 "1020a_e+v10_fmac")
 (define_insn_reservation "v10_farith" 5
 (and (eq_attr "vfp10" "yes")
 (eq_attr "type" "faddd,fadds"))
 "1020a_e+v10_fmac")
 (define_insn_reservation "v10_cvt" 5
 (and (eq_attr "vfp10" "yes")
-(eq_attr "type" "f_cvt"))
+(eq_attr "type" "f_cvt,f_cvti2f,f_cvtf2i"))
 "1020a_e+v10_fmac")
 (define_insn_reservation "v10_fmul" 6
 (and (eq_attr "vfp10" "yes")
-(eq_attr "type" "fmuls,fmacs,fmuld,fmacd"))
+(eq_attr "type" "fmuls,fmacs,ffmas,fmuld,fmacd,ffmad"))
 "1020a_e+v10_fmac*2")
 (define_insn_reservation "v10_fdivs" 18
 (and (eq_attr "vfp10" "yes")
-(eq_attr "type" "fdivs"))
+(eq_attr "type" "fdivs, fsqrts"))
-"1020a_e+v10_ds*14")
+"1020a_e+v10_ds*4")
 (define_insn_reservation "v10_fdivd" 32
 (and (eq_attr "vfp10" "yes")
-(eq_attr "type" "fdivd"))
+(eq_attr "type" "fdivd, fsqrtd"))
-"1020a_e+v10_fmac+v10_ds*28")
+"1020a_e+v10_fmac+v10_ds*4")
 (define_insn_reservation "v10_floads" 4
 (and (eq_attr "vfp10" "yes")
 (eq_attr "type" "f_loads"))
 "1020a_e+1020l_e+v10_ls1,v10_ls2")
 ;; Moves to/from arm regs also use the load/store pipeline.
 (define_insn_reservation "v10_c2v" 4
 (and (eq_attr "vfp10" "yes")
-(eq_attr "type" "r_2_f"))
+(eq_attr "type" "f_mcr,f_mcrr"))
 "1020a_e+1020l_e+v10_ls1,v10_ls2")
 (define_insn_reservation "v10_fstores" 1
 (and (eq_attr "vfp10" "yes")
 (eq_attr "type" "f_stores"))
 (eq_attr "type" "f_stored"))
 "1020a_e+1020l_e+v10_ls1+v10_ls2+v10_ls3,v10_ls2+v10_ls3,v10_ls3")
 (define_insn_reservation "v10_v2c" 1
 (and (eq_attr "vfp10" "yes")
-(eq_attr "type" "f_2_r"))
+(eq_attr "type" "f_mrc,f_mrrc"))
 "1020a_e+1020l_e,1020l_m,1020l_w")
 (define_insn_reservation "v10_to_cpsr" 2
 (and (eq_attr "vfp10" "yes")
 (eq_attr "type" "f_flag"))

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comparison gcc/config/arm/arm1020e.md @ 111:04ced10e8804