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comparison gcc/config/arm/arm926ejs.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents a06113de4d67
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; ARM 926EJ-S Pipeline Description 1 ;; ARM 926EJ-S Pipeline Description
2 ;; Copyright (C) 2003, 2007 Free Software Foundation, Inc. 2 ;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery, LLC. 3 ;; Written by CodeSourcery, LLC.
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
48 ;; ALU Instructions 48 ;; ALU Instructions
49 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 49 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
50 50
51 ;; ALU instructions require three cycles to execute, and use the ALU 51 ;; ALU instructions require three cycles to execute, and use the ALU
52 ;; pipeline in each of the three stages. The results are available 52 ;; pipeline in each of the three stages. The results are available
53 ;; after the execute stage stage has finished. 53 ;; after the execute stage has finished.
54 ;; 54 ;;
55 ;; If the destination register is the PC, the pipelines are stalled 55 ;; If the destination register is the PC, the pipelines are stalled
56 ;; for several cycles. That case is not modeled here. 56 ;; for several cycles. That case is not modeled here.
57 57
58 ;; ALU operations with no shifted operand 58 ;; ALU operations with no shifted operand
59 (define_insn_reservation "9_alu_op" 1 59 (define_insn_reservation "9_alu_op" 1
60 (and (eq_attr "tune" "arm926ejs") 60 (and (eq_attr "tune" "arm926ejs")
61 (eq_attr "type" "alu,alu_shift")) 61 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
62 alu_sreg,alus_sreg,logic_reg,logics_reg,\
63 adc_imm,adcs_imm,adc_reg,adcs_reg,\
64 adr,bfm,rev,\
65 alu_shift_imm,alus_shift_imm,\
66 logic_shift_imm,logics_shift_imm,\
67 shift_imm,shift_reg,extend,\
68 mov_imm,mov_reg,mov_shift,\
69 mvn_imm,mvn_reg,mvn_shift,\
70 multiple,no_insn"))
62 "e,m,w") 71 "e,m,w")
63 72
64 ;; ALU operations with a shift-by-register operand 73 ;; ALU operations with a shift-by-register operand
65 ;; These really stall in the decoder, in order to read 74 ;; These really stall in the decoder, in order to read
66 ;; the shift value in a second cycle. Pretend we take two cycles in 75 ;; the shift value in a second cycle. Pretend we take two cycles in
67 ;; the execute stage. 76 ;; the execute stage.
68 (define_insn_reservation "9_alu_shift_reg_op" 2 77 (define_insn_reservation "9_alu_shift_reg_op" 2
69 (and (eq_attr "tune" "arm926ejs") 78 (and (eq_attr "tune" "arm926ejs")
70 (eq_attr "type" "alu_shift_reg")) 79 (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
80 logic_shift_reg,logics_shift_reg,\
81 mov_shift_reg,mvn_shift_reg"))
71 "e*2,m,w") 82 "e*2,m,w")
72 83
73 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 84 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
74 ;; Multiplication Instructions 85 ;; Multiplication Instructions
75 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 86 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
79 ;; times. Multiply operations occur in both the execute and memory 90 ;; times. Multiply operations occur in both the execute and memory
80 ;; stages of the pipeline 91 ;; stages of the pipeline
81 92
82 (define_insn_reservation "9_mult1" 3 93 (define_insn_reservation "9_mult1" 3
83 (and (eq_attr "tune" "arm926ejs") 94 (and (eq_attr "tune" "arm926ejs")
84 (eq_attr "insn" "smlalxy,mul,mla")) 95 (eq_attr "type" "smlalxy,mul,mla"))
85 "e*2,m,w") 96 "e*2,m,w")
86 97
87 (define_insn_reservation "9_mult2" 4 98 (define_insn_reservation "9_mult2" 4
88 (and (eq_attr "tune" "arm926ejs") 99 (and (eq_attr "tune" "arm926ejs")
89 (eq_attr "insn" "muls,mlas")) 100 (eq_attr "type" "muls,mlas"))
90 "e*3,m,w") 101 "e*3,m,w")
91 102
92 (define_insn_reservation "9_mult3" 4 103 (define_insn_reservation "9_mult3" 4
93 (and (eq_attr "tune" "arm926ejs") 104 (and (eq_attr "tune" "arm926ejs")
94 (eq_attr "insn" "umull,umlal,smull,smlal")) 105 (eq_attr "type" "umull,umlal,smull,smlal"))
95 "e*3,m,w") 106 "e*3,m,w")
96 107
97 (define_insn_reservation "9_mult4" 5 108 (define_insn_reservation "9_mult4" 5
98 (and (eq_attr "tune" "arm926ejs") 109 (and (eq_attr "tune" "arm926ejs")
99 (eq_attr "insn" "umulls,umlals,smulls,smlals")) 110 (eq_attr "type" "umulls,umlals,smulls,smlals"))
100 "e*4,m,w") 111 "e*4,m,w")
101 112
102 (define_insn_reservation "9_mult5" 2 113 (define_insn_reservation "9_mult5" 2
103 (and (eq_attr "tune" "arm926ejs") 114 (and (eq_attr "tune" "arm926ejs")
104 (eq_attr "insn" "smulxy,smlaxy,smlawx")) 115 (eq_attr "type" "smulxy,smlaxy,smlawx"))
105 "e,m,w") 116 "e,m,w")
106 117
107 (define_insn_reservation "9_mult6" 3 118 (define_insn_reservation "9_mult6" 3
108 (and (eq_attr "tune" "arm926ejs") 119 (and (eq_attr "tune" "arm926ejs")
109 (eq_attr "insn" "smlalxy")) 120 (eq_attr "type" "smlalxy"))
110 "e*2,m,w") 121 "e*2,m,w")
111 122
112 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 123 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
113 ;; Load/Store Instructions 124 ;; Load/Store Instructions
114 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 125 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
120 131
121 ;; Loads with a shifted offset take 3 cycles, and are (a) probably the 132 ;; Loads with a shifted offset take 3 cycles, and are (a) probably the
122 ;; most common and (b) the pessimistic assumption will lead to fewer stalls. 133 ;; most common and (b) the pessimistic assumption will lead to fewer stalls.
123 (define_insn_reservation "9_load1_op" 3 134 (define_insn_reservation "9_load1_op" 3
124 (and (eq_attr "tune" "arm926ejs") 135 (and (eq_attr "tune" "arm926ejs")
125 (eq_attr "type" "load1,load_byte")) 136 (eq_attr "type" "load_4,load_byte"))
126 "e*2,m,w") 137 "e*2,m,w")
127 138
128 (define_insn_reservation "9_store1_op" 0 139 (define_insn_reservation "9_store1_op" 0
129 (and (eq_attr "tune" "arm926ejs") 140 (and (eq_attr "tune" "arm926ejs")
130 (eq_attr "type" "store1")) 141 (eq_attr "type" "store_4"))
131 "e,m,w") 142 "e,m,w")
132 143
133 ;; multiple word loads and stores 144 ;; multiple word loads and stores
134 (define_insn_reservation "9_load2_op" 3 145 (define_insn_reservation "9_load2_op" 3
135 (and (eq_attr "tune" "arm926ejs") 146 (and (eq_attr "tune" "arm926ejs")
136 (eq_attr "type" "load2")) 147 (eq_attr "type" "load_8"))
137 "e,m*2,w") 148 "e,m*2,w")
138 149
139 (define_insn_reservation "9_load3_op" 4 150 (define_insn_reservation "9_load3_op" 4
140 (and (eq_attr "tune" "arm926ejs") 151 (and (eq_attr "tune" "arm926ejs")
141 (eq_attr "type" "load3")) 152 (eq_attr "type" "load_12"))
142 "e,m*3,w") 153 "e,m*3,w")
143 154
144 (define_insn_reservation "9_load4_op" 5 155 (define_insn_reservation "9_load4_op" 5
145 (and (eq_attr "tune" "arm926ejs") 156 (and (eq_attr "tune" "arm926ejs")
146 (eq_attr "type" "load4")) 157 (eq_attr "type" "load_16"))
147 "e,m*4,w") 158 "e,m*4,w")
148 159
149 (define_insn_reservation "9_store2_op" 0 160 (define_insn_reservation "9_store2_op" 0
150 (and (eq_attr "tune" "arm926ejs") 161 (and (eq_attr "tune" "arm926ejs")
151 (eq_attr "type" "store2")) 162 (eq_attr "type" "store_8"))
152 "e,m*2,w") 163 "e,m*2,w")
153 164
154 (define_insn_reservation "9_store3_op" 0 165 (define_insn_reservation "9_store3_op" 0
155 (and (eq_attr "tune" "arm926ejs") 166 (and (eq_attr "tune" "arm926ejs")
156 (eq_attr "type" "store3")) 167 (eq_attr "type" "store_12"))
157 "e,m*3,w") 168 "e,m*3,w")
158 169
159 (define_insn_reservation "9_store4_op" 0 170 (define_insn_reservation "9_store4_op" 0
160 (and (eq_attr "tune" "arm926ejs") 171 (and (eq_attr "tune" "arm926ejs")
161 (eq_attr "type" "store4")) 172 (eq_attr "type" "store_16"))
162 "e,m*4,w") 173 "e,m*4,w")
163 174
164 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 175 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
165 ;; Branch and Call Instructions 176 ;; Branch and Call Instructions
166 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 177 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;