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comparison gcc/config/arm/cortex-m4.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 561a7518be6b
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; ARM Cortex-M4 pipeline description 1 ;; ARM Cortex-M4 pipeline description
2 ;; Copyright (C) 2010 Free Software Foundation, Inc. 2 ;; Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 ;; Contributed by CodeSourcery. 3 ;; Contributed by CodeSourcery.
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
29 (define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b") 29 (define_reservation "cortex_m4_ex" "cortex_m4_a+cortex_m4_b")
30 30
31 ;; ALU and multiply is one cycle. 31 ;; ALU and multiply is one cycle.
32 (define_insn_reservation "cortex_m4_alu" 1 32 (define_insn_reservation "cortex_m4_alu" 1
33 (and (eq_attr "tune" "cortexm4") 33 (and (eq_attr "tune" "cortexm4")
34 (eq_attr "type" "alu,alu_shift,alu_shift_reg,mult")) 34 (ior (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
35 alu_sreg,alus_sreg,logic_reg,logics_reg,\
36 adc_imm,adcs_imm,adc_reg,adcs_reg,\
37 adr,bfm,clz,rbit,rev,alu_dsp_reg,\
38 shift_imm,shift_reg,extend,\
39 alu_shift_imm,alus_shift_imm,\
40 logic_shift_imm,logics_shift_imm,\
41 alu_shift_reg,alus_shift_reg,\
42 logic_shift_reg,logics_shift_reg,\
43 mov_imm,mov_reg,mov_shift,mov_shift_reg,\
44 mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
45 mrs,multiple,no_insn")
46 (ior (eq_attr "mul32" "yes")
47 (eq_attr "mul64" "yes"))))
35 "cortex_m4_ex") 48 "cortex_m4_ex")
36 49
37 ;; Byte, half-word and word load is two cycles. 50 ;; Byte, half-word and word load is two cycles.
38 (define_insn_reservation "cortex_m4_load1" 2 51 (define_insn_reservation "cortex_m4_load1" 2
39 (and (eq_attr "tune" "cortexm4") 52 (and (eq_attr "tune" "cortexm4")
40 (eq_attr "type" "load_byte,load1")) 53 (eq_attr "type" "load_byte,load_4"))
41 "cortex_m4_a, cortex_m4_b") 54 "cortex_m4_a, cortex_m4_b")
42 55
43 ;; str rx, [ry, #imm] is always one cycle. 56 ;; str rx, [ry, #imm] is always one cycle.
44 (define_insn_reservation "cortex_m4_store1_1" 1 57 (define_insn_reservation "cortex_m4_store1_1" 1
45 (and (and (eq_attr "tune" "cortexm4") 58 (and (and (eq_attr "tune" "cortexm4")
46 (eq_attr "type" "store1")) 59 (eq_attr "type" "store_4"))
47 (ne (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0))) 60 (match_test "arm_address_offset_is_imm (insn)"))
48 "cortex_m4_a") 61 "cortex_m4_a")
49 62
50 ;; Other byte, half-word and word load is two cycles. 63 ;; Other byte, half-word and word load is two cycles.
51 (define_insn_reservation "cortex_m4_store1_2" 2 64 (define_insn_reservation "cortex_m4_store1_2" 2
52 (and (and (eq_attr "tune" "cortexm4") 65 (and (and (eq_attr "tune" "cortexm4")
53 (eq_attr "type" "store1")) 66 (eq_attr "type" "store_4"))
54 (eq (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0))) 67 (not (match_test "arm_address_offset_is_imm (insn)")))
55 "cortex_m4_a*2") 68 "cortex_m4_a*2")
56 69
57 (define_insn_reservation "cortex_m4_load2" 3 70 (define_insn_reservation "cortex_m4_load2" 3
58 (and (eq_attr "tune" "cortexm4") 71 (and (eq_attr "tune" "cortexm4")
59 (eq_attr "type" "load2")) 72 (eq_attr "type" "load_8"))
60 "cortex_m4_ex*3") 73 "cortex_m4_ex*3")
61 74
62 (define_insn_reservation "cortex_m4_store2" 3 75 (define_insn_reservation "cortex_m4_store2" 3
63 (and (eq_attr "tune" "cortexm4") 76 (and (eq_attr "tune" "cortexm4")
64 (eq_attr "type" "store2")) 77 (eq_attr "type" "store_8"))
65 "cortex_m4_ex*3") 78 "cortex_m4_ex*3")
66 79
67 (define_insn_reservation "cortex_m4_load3" 4 80 (define_insn_reservation "cortex_m4_load3" 4
68 (and (eq_attr "tune" "cortexm4") 81 (and (eq_attr "tune" "cortexm4")
69 (eq_attr "type" "load3")) 82 (eq_attr "type" "load_12"))
70 "cortex_m4_ex*4") 83 "cortex_m4_ex*4")
71 84
72 (define_insn_reservation "cortex_m4_store3" 4 85 (define_insn_reservation "cortex_m4_store3" 4
73 (and (eq_attr "tune" "cortexm4") 86 (and (eq_attr "tune" "cortexm4")
74 (eq_attr "type" "store3")) 87 (eq_attr "type" "store_12"))
75 "cortex_m4_ex*4") 88 "cortex_m4_ex*4")
76 89
77 (define_insn_reservation "cortex_m4_load4" 5 90 (define_insn_reservation "cortex_m4_load4" 5
78 (and (eq_attr "tune" "cortexm4") 91 (and (eq_attr "tune" "cortexm4")
79 (eq_attr "type" "load4")) 92 (eq_attr "type" "load_16"))
80 "cortex_m4_ex*5") 93 "cortex_m4_ex*5")
81 94
82 (define_insn_reservation "cortex_m4_store4" 5 95 (define_insn_reservation "cortex_m4_store4" 5
83 (and (eq_attr "tune" "cortexm4") 96 (and (eq_attr "tune" "cortexm4")
84 (eq_attr "type" "store4")) 97 (eq_attr "type" "store_16"))
85 "cortex_m4_ex*5") 98 "cortex_m4_ex*5")
99
100 (define_bypass 1 "cortex_m4_load1"
101 "cortex_m4_store1_1,cortex_m4_store1_2"
102 "arm_no_early_store_addr_dep")
86 103
87 ;; If the address of load or store depends on the result of the preceding 104 ;; If the address of load or store depends on the result of the preceding
88 ;; instruction, the latency is increased by one. 105 ;; instruction, the latency is increased by one.
89 106
90 (define_bypass 2 "cortex_m4_alu" 107 (define_bypass 2 "cortex_m4_alu"