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comparison gcc/config/arm/fa726te.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 561a7518be6b
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Faraday FA726TE Pipeline Description 1 ;; Faraday FA726TE Pipeline Description
2 ;; Copyright (C) 2010 Free Software Foundation, Inc. 2 ;; Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description. 3 ;; Written by I-Jui Sung, based on ARM926EJ-S Pipeline Description.
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it under 7 ;; GCC is free software; you can redistribute it and/or modify it under
68 ;; ALU Instructions 68 ;; ALU Instructions
69 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 69 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
70 70
71 ;; ALU instructions require three cycles to execute, and use the ALU 71 ;; ALU instructions require three cycles to execute, and use the ALU
72 ;; pipeline in each of the three stages. The results are available 72 ;; pipeline in each of the three stages. The results are available
73 ;; after the execute stage stage has finished. 73 ;; after the execute stage has finished.
74 ;; 74 ;;
75 ;; If the destination register is the PC, the pipelines are stalled 75 ;; If the destination register is the PC, the pipelines are stalled
76 ;; for several cycles. That case is not modeled here. 76 ;; for several cycles. That case is not modeled here.
77 77
78 ;; Move instructions. 78 ;; Move instructions.
79 (define_insn_reservation "726te_shift_op" 1 79 (define_insn_reservation "726te_shift_op" 1
80 (and (eq_attr "tune" "fa726te") 80 (and (eq_attr "tune" "fa726te")
81 (eq_attr "insn" "mov,mvn")) 81 (eq_attr "type" "mov_imm,mov_reg,mov_shift,mov_shift_reg,\
82 mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
82 "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") 83 "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
83 84
84 ;; ALU operations with no shifted operand will finished in 1 cycle 85 ;; ALU operations with no shifted operand will finished in 1 cycle
85 ;; Other ALU instructions 2 cycles. 86 ;; Other ALU instructions 2 cycles.
86 (define_insn_reservation "726te_alu_op" 1 87 (define_insn_reservation "726te_alu_op" 1
87 (and (eq_attr "tune" "fa726te") 88 (and (eq_attr "tune" "fa726te")
88 (and (eq_attr "type" "alu") 89 (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
89 (not (eq_attr "insn" "mov,mvn")))) 90 alu_sreg,alus_sreg,logic_reg,logics_reg,\
91 adc_imm,adcs_imm,adc_reg,adcs_reg,\
92 adr,bfm,rev,\
93 shift_imm,shift_reg,\
94 mrs,multiple,no_insn"))
90 "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") 95 "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
91 96
92 ;; ALU operations with a shift-by-register operand. 97 ;; ALU operations with a shift-by-register operand.
93 ;; These really stall in the decoder, in order to read the shift value 98 ;; These really stall in the decoder, in order to read the shift value
94 ;; in the first cycle. If the instruction uses both shifter and AU, 99 ;; in the first cycle. If the instruction uses both shifter and AU,
95 ;; it takes 3 cycles. 100 ;; it takes 3 cycles.
96 (define_insn_reservation "726te_alu_shift_op" 3 101 (define_insn_reservation "726te_alu_shift_op" 3
97 (and (eq_attr "tune" "fa726te") 102 (and (eq_attr "tune" "fa726te")
98 (and (eq_attr "type" "alu_shift") 103 (eq_attr "type" "extend,alu_shift_imm,alus_shift_imm,\
99 (not (eq_attr "insn" "mov,mvn")))) 104 logic_shift_imm,logics_shift_imm"))
100 "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") 105 "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
101 106
102 (define_insn_reservation "726te_alu_shift_reg_op" 3 107 (define_insn_reservation "726te_alu_shift_reg_op" 3
103 (and (eq_attr "tune" "fa726te") 108 (and (eq_attr "tune" "fa726te")
104 (and (eq_attr "type" "alu_shift_reg") 109 (eq_attr "type" "alu_shift_reg,alus_shift_reg,\
105 (not (eq_attr "insn" "mov,mvn")))) 110 logic_shift_reg,logics_shift_reg"))
106 "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)") 111 "fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
107 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 112 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
108 ;; Multiplication Instructions 113 ;; Multiplication Instructions
109 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 114 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
110 115
113 ;; times. Multiply operations occur in both the execute and memory 118 ;; times. Multiply operations occur in both the execute and memory
114 ;; stages of the pipeline 119 ;; stages of the pipeline
115 120
116 (define_insn_reservation "726te_mult_op" 3 121 (define_insn_reservation "726te_mult_op" 3
117 (and (eq_attr "tune" "fa726te") 122 (and (eq_attr "tune" "fa726te")
118 (eq_attr "insn" "smlalxy,mul,mla,muls,mlas,umull,umlal,smull,smlal,\ 123 (eq_attr "type" "smlalxy,mul,mla,muls,mlas,umull,umlal,smull,smlal,\
119 umulls,umlals,smulls,smlals,smlawx,smulxy,smlaxy")) 124 umulls,umlals,smulls,smlals,smlawx,smulxy,smlaxy"))
120 "fa726te_issue+fa726te_mac_pipe") 125 "fa726te_issue+fa726te_mac_pipe")
121 126
122 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; 127 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
123 ;; Load/Store Instructions 128 ;; Load/Store Instructions
137 ;; same "bundle", and the 2nd load will introudce another ISSUE stall but is 142 ;; same "bundle", and the 2nd load will introudce another ISSUE stall but is
138 ;; still ok to execute (and may be benefical sometimes). 143 ;; still ok to execute (and may be benefical sometimes).
139 144
140 (define_insn_reservation "726te_load1_op" 3 145 (define_insn_reservation "726te_load1_op" 3
141 (and (eq_attr "tune" "fa726te") 146 (and (eq_attr "tune" "fa726te")
142 (eq_attr "type" "load1,load_byte")) 147 (eq_attr "type" "load_4,load_byte"))
143 "(fa726te_issue+fa726te_lsu_pipe_e+fa726te_lsu_pipe_w)\ 148 "(fa726te_issue+fa726te_lsu_pipe_e+fa726te_lsu_pipe_w)\
144 | (fa726te_issue+fa726te_lsu1_pipe_e+fa726te_lsu1_pipe_w,fa726te_blockage)") 149 | (fa726te_issue+fa726te_lsu1_pipe_e+fa726te_lsu1_pipe_w,fa726te_blockage)")
145 150
146 (define_insn_reservation "726te_store1_op" 1 151 (define_insn_reservation "726te_store1_op" 1
147 (and (eq_attr "tune" "fa726te") 152 (and (eq_attr "tune" "fa726te")
148 (eq_attr "type" "store1")) 153 (eq_attr "type" "store_4"))
149 "fa726te_blockage*2") 154 "fa726te_blockage*2")
150 155
151 ;; Load/Store Multiple blocks all pipelines in EX stages until WB. 156 ;; Load/Store Multiple blocks all pipelines in EX stages until WB.
152 ;; No other instructions can be issued together. Since they essentially 157 ;; No other instructions can be issued together. Since they essentially
153 ;; prevent all scheduling opportunities, we model them together here. 158 ;; prevent all scheduling opportunities, we model them together here.
154 159
155 ;; The LDM is breaking into multiple load instructions, later instruction in 160 ;; The LDM is breaking into multiple load instructions, later instruction in
156 ;; the pipe 1 is stalled. 161 ;; the pipe 1 is stalled.
157 (define_insn_reservation "726te_ldm2_op" 4 162 (define_insn_reservation "726te_ldm2_op" 4
158 (and (eq_attr "tune" "fa726te") 163 (and (eq_attr "tune" "fa726te")
159 (eq_attr "type" "load2,load3")) 164 (eq_attr "type" "load_8,load_12"))
160 "fa726te_blockage*4") 165 "fa726te_blockage*4")
161 166
162 (define_insn_reservation "726te_ldm3_op" 5 167 (define_insn_reservation "726te_ldm3_op" 5
163 (and (eq_attr "tune" "fa726te") 168 (and (eq_attr "tune" "fa726te")
164 (eq_attr "type" "load4")) 169 (eq_attr "type" "load_16"))
165 "fa726te_blockage*5") 170 "fa726te_blockage*5")
166 171
167 (define_insn_reservation "726te_stm2_op" 2 172 (define_insn_reservation "726te_stm2_op" 2
168 (and (eq_attr "tune" "fa726te") 173 (and (eq_attr "tune" "fa726te")
169 (eq_attr "type" "store2,store3")) 174 (eq_attr "type" "store_8,store_12"))
170 "fa726te_blockage*3") 175 "fa726te_blockage*3")
171 176
172 (define_insn_reservation "726te_stm3_op" 3 177 (define_insn_reservation "726te_stm3_op" 3
173 (and (eq_attr "tune" "fa726te") 178 (and (eq_attr "tune" "fa726te")
174 (eq_attr "type" "store4")) 179 (eq_attr "type" "store_16"))
175 "fa726te_blockage*4") 180 "fa726te_blockage*4")
176 181
177 (define_bypass 1 "726te_load1_op,726te_ldm2_op,726te_ldm3_op" "726te_store1_op,\ 182 (define_bypass 1 "726te_load1_op,726te_ldm2_op,726te_ldm3_op" "726te_store1_op,\
178 726te_stm2_op,726te_stm3_op" "arm_no_early_store_addr_dep") 183 726te_stm2_op,726te_stm3_op" "arm_no_early_store_addr_dep")
179 (define_bypass 0 "726te_shift_op,726te_alu_op,726te_alu_shift_op,\ 184 (define_bypass 0 "726te_shift_op,726te_alu_op,726te_alu_shift_op,\