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comparison gcc/config/arm/iwmmxt.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
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68:561a7518be6b 111:04ced10e8804
1 ;; ??? This file needs auditing for thumb2
2 ;; Patterns for the Intel Wireless MMX technology architecture. 1 ;; Patterns for the Intel Wireless MMX technology architecture.
3 ;; Copyright (C) 2003, 2004, 2005, 2007, 2008, 2010 2 ;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Red Hat. 3 ;; Contributed by Red Hat.
6 4
7 ;; This file is part of GCC. 5 ;; This file is part of GCC.
8 6
9 ;; GCC is free software; you can redistribute it and/or modify it under 7 ;; GCC is free software; you can redistribute it and/or modify it under
18 16
19 ;; You should have received a copy of the GNU General Public License 17 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see 18 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>. 19 ;; <http://www.gnu.org/licenses/>.
22 20
21 ;; Register numbers. Need to sync with FIRST_IWMMXT_GR_REGNUM in arm.h
22 (define_constants
23 [(WCGR0 96)
24 (WCGR1 97)
25 (WCGR2 98)
26 (WCGR3 99)
27 ]
28 )
29
30 (define_insn "tbcstv8qi"
31 [(set (match_operand:V8QI 0 "register_operand" "=y")
32 (vec_duplicate:V8QI (match_operand:QI 1 "s_register_operand" "r")))]
33 "TARGET_REALLY_IWMMXT"
34 "tbcstb%?\\t%0, %1"
35 [(set_attr "predicable" "yes")
36 (set_attr "type" "wmmx_tbcst")]
37 )
38
39 (define_insn "tbcstv4hi"
40 [(set (match_operand:V4HI 0 "register_operand" "=y")
41 (vec_duplicate:V4HI (match_operand:HI 1 "s_register_operand" "r")))]
42 "TARGET_REALLY_IWMMXT"
43 "tbcsth%?\\t%0, %1"
44 [(set_attr "predicable" "yes")
45 (set_attr "type" "wmmx_tbcst")]
46 )
47
48 (define_insn "tbcstv2si"
49 [(set (match_operand:V2SI 0 "register_operand" "=y")
50 (vec_duplicate:V2SI (match_operand:SI 1 "s_register_operand" "r")))]
51 "TARGET_REALLY_IWMMXT"
52 "tbcstw%?\\t%0, %1"
53 [(set_attr "predicable" "yes")
54 (set_attr "type" "wmmx_tbcst")]
55 )
23 56
24 (define_insn "iwmmxt_iordi3" 57 (define_insn "iwmmxt_iordi3"
25 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") 58 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
26 (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r") 59 (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
27 (match_operand:DI 2 "register_operand" "y,r,r")))] 60 (match_operand:DI 2 "register_operand" "y,r,r")))]
29 "@ 62 "@
30 wor%?\\t%0, %1, %2 63 wor%?\\t%0, %1, %2
31 # 64 #
32 #" 65 #"
33 [(set_attr "predicable" "yes") 66 [(set_attr "predicable" "yes")
34 (set_attr "length" "4,8,8")]) 67 (set_attr "length" "4,8,8")
68 (set_attr "type" "wmmx_wor,*,*")]
69 )
35 70
36 (define_insn "iwmmxt_xordi3" 71 (define_insn "iwmmxt_xordi3"
37 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") 72 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
38 (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r") 73 (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
39 (match_operand:DI 2 "register_operand" "y,r,r")))] 74 (match_operand:DI 2 "register_operand" "y,r,r")))]
41 "@ 76 "@
42 wxor%?\\t%0, %1, %2 77 wxor%?\\t%0, %1, %2
43 # 78 #
44 #" 79 #"
45 [(set_attr "predicable" "yes") 80 [(set_attr "predicable" "yes")
46 (set_attr "length" "4,8,8")]) 81 (set_attr "length" "4,8,8")
82 (set_attr "type" "wmmx_wxor,*,*")]
83 )
47 84
48 (define_insn "iwmmxt_anddi3" 85 (define_insn "iwmmxt_anddi3"
49 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") 86 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
50 (and:DI (match_operand:DI 1 "register_operand" "%y,0,r") 87 (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
51 (match_operand:DI 2 "register_operand" "y,r,r")))] 88 (match_operand:DI 2 "register_operand" "y,r,r")))]
53 "@ 90 "@
54 wand%?\\t%0, %1, %2 91 wand%?\\t%0, %1, %2
55 # 92 #
56 #" 93 #"
57 [(set_attr "predicable" "yes") 94 [(set_attr "predicable" "yes")
58 (set_attr "length" "4,8,8")]) 95 (set_attr "length" "4,8,8")
96 (set_attr "type" "wmmx_wand,*,*")]
97 )
59 98
60 (define_insn "iwmmxt_nanddi3" 99 (define_insn "iwmmxt_nanddi3"
61 [(set (match_operand:DI 0 "register_operand" "=y") 100 [(set (match_operand:DI 0 "register_operand" "=y")
62 (and:DI (match_operand:DI 1 "register_operand" "y") 101 (and:DI (match_operand:DI 1 "register_operand" "y")
63 (not:DI (match_operand:DI 2 "register_operand" "y"))))] 102 (not:DI (match_operand:DI 2 "register_operand" "y"))))]
64 "TARGET_REALLY_IWMMXT" 103 "TARGET_REALLY_IWMMXT"
65 "wandn%?\\t%0, %1, %2" 104 "wandn%?\\t%0, %1, %2"
66 [(set_attr "predicable" "yes")]) 105 [(set_attr "predicable" "yes")
106 (set_attr "type" "wmmx_wandn")]
107 )
67 108
68 (define_insn "*iwmmxt_arm_movdi" 109 (define_insn "*iwmmxt_arm_movdi"
69 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, m,y,y,yr,y,yrUy") 110 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,r, y,Uy,*w, r,*w,*w, *Uv")
70 (match_operand:DI 1 "di_operand" "rIK,mi,r,y,yr,y,yrUy,y"))] 111 (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r,y,r,y,Uy,y, r,*w,*w,*Uvi,*w"))]
71 "TARGET_REALLY_IWMMXT 112 "TARGET_REALLY_IWMMXT
72 && ( register_operand (operands[0], DImode) 113 && ( register_operand (operands[0], DImode)
73 || register_operand (operands[1], DImode))" 114 || register_operand (operands[1], DImode))"
74 "* 115 "*
75 {
76 switch (which_alternative) 116 switch (which_alternative)
77 { 117 {
118 case 0:
119 case 1:
120 case 2:
121 return \"#\";
122 case 3: case 4:
123 return output_move_double (operands, true, NULL);
124 case 5:
125 return \"wmov%?\\t%0,%1\";
126 case 6:
127 return \"tmcrr%?\\t%0,%Q1,%R1\";
128 case 7:
129 return \"tmrrc%?\\t%Q0,%R0,%1\";
130 case 8:
131 return \"wldrd%?\\t%0,%1\";
132 case 9:
133 return \"wstrd%?\\t%1,%0\";
134 case 10:
135 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
136 case 11:
137 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
138 case 12:
139 if (TARGET_VFP_SINGLE)
140 return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
141 else
142 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
143 case 13: case 14:
144 return output_move_vfp (operands);
78 default: 145 default:
79 return output_move_double (operands); 146 gcc_unreachable ();
80 case 0:
81 return \"#\";
82 case 3:
83 return \"wmov%?\\t%0,%1\";
84 case 4:
85 return \"tmcrr%?\\t%0,%Q1,%R1\";
86 case 5:
87 return \"tmrrc%?\\t%Q0,%R0,%1\";
88 case 6:
89 return \"wldrd%?\\t%0,%1\";
90 case 7:
91 return \"wstrd%?\\t%1,%0\";
92 } 147 }
93 }" 148 "
94 [(set_attr "length" "8,8,8,4,4,4,4,4") 149 [(set (attr "length") (cond [(eq_attr "alternative" "0,3,4") (const_int 8)
95 (set_attr "type" "*,load1,store2,*,*,*,*,*") 150 (eq_attr "alternative" "1") (const_int 12)
96 (set_attr "pool_range" "*,1020,*,*,*,*,*,*") 151 (eq_attr "alternative" "2") (const_int 16)
97 (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")] 152 (eq_attr "alternative" "12")
153 (if_then_else
154 (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1))
155 (const_int 8)
156 (const_int 4))]
157 (const_int 4)))
158 (set_attr "type" "*,*,*,load_8,store_8,*,*,*,*,*,f_mcrr,f_mrrc,\
159 ffarithd,f_loadd,f_stored")
160 (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*")
161 (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")]
98 ) 162 )
99 163
100 (define_insn "*iwmmxt_movsi_insn" 164 (define_insn "*iwmmxt_movsi_insn"
101 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,rk, m,z,r,?z,Uy,z") 165 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk, m,z,r,?z,?Uy,*t, r,*t,*t ,*Uv")
102 (match_operand:SI 1 "general_operand" "rk, I,K,mi,rk,r,z,Uy,z, z"))] 166 (match_operand:SI 1 "general_operand" " rk,I,K,j,mi,rk,r,z,Uy, z, r,*t,*t,*Uvi, *t"))]
103 "TARGET_REALLY_IWMMXT 167 "TARGET_REALLY_IWMMXT
104 && ( register_operand (operands[0], SImode) 168 && ( register_operand (operands[0], SImode)
105 || register_operand (operands[1], SImode))" 169 || register_operand (operands[1], SImode))"
106 "* 170 "*
107 switch (which_alternative) 171 switch (which_alternative)
108 { 172 {
109 case 0: return \"mov\\t%0, %1\"; 173 case 0: return \"mov\\t%0, %1\";
110 case 1: return \"mov\\t%0, %1\"; 174 case 1: return \"mov\\t%0, %1\";
111 case 2: return \"mvn\\t%0, #%B1\"; 175 case 2: return \"mvn\\t%0, #%B1\";
112 case 3: return \"ldr\\t%0, %1\"; 176 case 3: return \"movw\\t%0, %1\";
113 case 4: return \"str\\t%1, %0\"; 177 case 4: return \"ldr\\t%0, %1\";
114 case 5: return \"tmcr\\t%0, %1\"; 178 case 5: return \"str\\t%1, %0\";
115 case 6: return \"tmrc\\t%0, %1\"; 179 case 6: return \"tmcr\\t%0, %1\";
116 case 7: return arm_output_load_gr (operands); 180 case 7: return \"tmrc\\t%0, %1\";
117 case 8: return \"wstrw\\t%1, %0\"; 181 case 8: return arm_output_load_gr (operands);
118 default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\"; 182 case 9: return \"wstrw\\t%1, %0\";
119 }" 183 case 10:return \"fmsr\\t%0, %1\";
120 [(set_attr "type" "*,*,*,load1,store1,*,*,load1,store1,*") 184 case 11:return \"fmrs\\t%0, %1\";
121 (set_attr "length" "*,*,*,*, *,*,*, 16, *,8") 185 case 12:return \"fcpys\\t%0, %1\\t%@ int\";
122 (set_attr "pool_range" "*,*,*,4096, *,*,*,1024, *,*") 186 case 13: case 14:
123 (set_attr "neg_pool_range" "*,*,*,4084, *,*,*, *, 1012,*") 187 return output_move_vfp (operands);
188 default:
189 gcc_unreachable ();
190 }"
191 [(set_attr "type" "*,*,*,*,load_4,store_4,*,*,*,*,f_mcr,f_mrc,\
192 fmov,f_loads,f_stores")
193 (set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*")
194 (set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*")
195 (set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*")
124 ;; Note - the "predicable" attribute is not allowed to have alternatives. 196 ;; Note - the "predicable" attribute is not allowed to have alternatives.
125 ;; Since the wSTRw wCx instruction is not predicable, we cannot support 197 ;; Since the wSTRw wCx instruction is not predicable, we cannot support
126 ;; predicating any of the alternatives in this template. Instead, 198 ;; predicating any of the alternatives in this template. Instead,
127 ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn. 199 ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
128 (set_attr "predicable" "no") 200 (set_attr "predicable" "no")
153 case 2: return \"ldr%?\\t%0, %1\"; 225 case 2: return \"ldr%?\\t%0, %1\";
154 case 3: return \"str%?\\t%1, %0\"; 226 case 3: return \"str%?\\t%1, %0\";
155 case 4: return \"tmcr%?\\t%0, %1\"; 227 case 4: return \"tmcr%?\\t%0, %1\";
156 default: return \"tmrc%?\\t%0, %1\"; 228 default: return \"tmrc%?\\t%0, %1\";
157 }" 229 }"
158 [(set_attr "type" "*,*,load1,store1,*,*") 230 [(set_attr "type" "*,*,load_4,store_4,*,*")
159 (set_attr "pool_range" "*,*,4096, *,*,*") 231 (set_attr "pool_range" "*,*,4096, *,*,*")
160 (set_attr "neg_pool_range" "*,*,4084, *,*,*")] 232 (set_attr "neg_pool_range" "*,*,4084, *,*,*")]
161 ) 233 )
162 234
163 (define_insn "mov<mode>_internal" 235 (define_insn "mov<mode>_internal"
171 case 1: return \"wstrd%?\\t%1, %0\"; 243 case 1: return \"wstrd%?\\t%1, %0\";
172 case 2: return \"wldrd%?\\t%0, %1\"; 244 case 2: return \"wldrd%?\\t%0, %1\";
173 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; 245 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
174 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; 246 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
175 case 5: return \"#\"; 247 case 5: return \"#\";
176 default: return output_move_double (operands); 248 default: return output_move_double (operands, true, NULL);
177 }" 249 }"
178 [(set_attr "predicable" "yes") 250 [(set_attr "predicable" "yes")
179 (set_attr "length" "4, 4, 4,4,4,8, 8,8") 251 (set_attr "length" "4, 4, 4,4,4,8, 8,8")
180 (set_attr "type" "*,store1,load1,*,*,*,load1,store1") 252 (set_attr "type" "wmmx_wmov,wmmx_wstr,wmmx_wldr,wmmx_tmrrc,wmmx_tmcrr,*,load_4,store_4")
181 (set_attr "pool_range" "*, *, 256,*,*,*, 256,*") 253 (set_attr "pool_range" "*, *, 256,*,*,*, 256,*")
182 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244,*")]) 254 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244,*")]
255 )
256
257 (define_expand "iwmmxt_setwcgr0"
258 [(set (reg:SI WCGR0)
259 (match_operand:SI 0 "register_operand" ""))]
260 "TARGET_REALLY_IWMMXT"
261 {}
262 )
263
264 (define_expand "iwmmxt_setwcgr1"
265 [(set (reg:SI WCGR1)
266 (match_operand:SI 0 "register_operand" ""))]
267 "TARGET_REALLY_IWMMXT"
268 {}
269 )
270
271 (define_expand "iwmmxt_setwcgr2"
272 [(set (reg:SI WCGR2)
273 (match_operand:SI 0 "register_operand" ""))]
274 "TARGET_REALLY_IWMMXT"
275 {}
276 )
277
278 (define_expand "iwmmxt_setwcgr3"
279 [(set (reg:SI WCGR3)
280 (match_operand:SI 0 "register_operand" ""))]
281 "TARGET_REALLY_IWMMXT"
282 {}
283 )
284
285 (define_expand "iwmmxt_getwcgr0"
286 [(set (match_operand:SI 0 "register_operand" "")
287 (reg:SI WCGR0))]
288 "TARGET_REALLY_IWMMXT"
289 {}
290 )
291
292 (define_expand "iwmmxt_getwcgr1"
293 [(set (match_operand:SI 0 "register_operand" "")
294 (reg:SI WCGR1))]
295 "TARGET_REALLY_IWMMXT"
296 {}
297 )
298
299 (define_expand "iwmmxt_getwcgr2"
300 [(set (match_operand:SI 0 "register_operand" "")
301 (reg:SI WCGR2))]
302 "TARGET_REALLY_IWMMXT"
303 {}
304 )
305
306 (define_expand "iwmmxt_getwcgr3"
307 [(set (match_operand:SI 0 "register_operand" "")
308 (reg:SI WCGR3))]
309 "TARGET_REALLY_IWMMXT"
310 {}
311 )
312
313 (define_insn "*and<mode>3_iwmmxt"
314 [(set (match_operand:VMMX 0 "register_operand" "=y")
315 (and:VMMX (match_operand:VMMX 1 "register_operand" "y")
316 (match_operand:VMMX 2 "register_operand" "y")))]
317 "TARGET_REALLY_IWMMXT"
318 "wand\\t%0, %1, %2"
319 [(set_attr "predicable" "yes")
320 (set_attr "type" "wmmx_wand")]
321 )
322
323 (define_insn "*ior<mode>3_iwmmxt"
324 [(set (match_operand:VMMX 0 "register_operand" "=y")
325 (ior:VMMX (match_operand:VMMX 1 "register_operand" "y")
326 (match_operand:VMMX 2 "register_operand" "y")))]
327 "TARGET_REALLY_IWMMXT"
328 "wor\\t%0, %1, %2"
329 [(set_attr "predicable" "yes")
330 (set_attr "type" "wmmx_wor")]
331 )
332
333 (define_insn "*xor<mode>3_iwmmxt"
334 [(set (match_operand:VMMX 0 "register_operand" "=y")
335 (xor:VMMX (match_operand:VMMX 1 "register_operand" "y")
336 (match_operand:VMMX 2 "register_operand" "y")))]
337 "TARGET_REALLY_IWMMXT"
338 "wxor\\t%0, %1, %2"
339 [(set_attr "predicable" "yes")
340 (set_attr "type" "wmmx_wxor")]
341 )
342
183 343
184 ;; Vector add/subtract 344 ;; Vector add/subtract
185 345
186 (define_insn "*add<mode>3_iwmmxt" 346 (define_insn "*add<mode>3_iwmmxt"
187 [(set (match_operand:VMMX 0 "register_operand" "=y") 347 [(set (match_operand:VMMX 0 "register_operand" "=y")
188 (plus:VMMX (match_operand:VMMX 1 "register_operand" "y") 348 (plus:VMMX (match_operand:VMMX 1 "register_operand" "y")
189 (match_operand:VMMX 2 "register_operand" "y")))] 349 (match_operand:VMMX 2 "register_operand" "y")))]
190 "TARGET_REALLY_IWMMXT" 350 "TARGET_REALLY_IWMMXT"
191 "wadd<MMX_char>%?\\t%0, %1, %2" 351 "wadd<MMX_char>%?\\t%0, %1, %2"
192 [(set_attr "predicable" "yes")]) 352 [(set_attr "predicable" "yes")
353 (set_attr "type" "wmmx_wadd")]
354 )
193 355
194 (define_insn "ssaddv8qi3" 356 (define_insn "ssaddv8qi3"
195 [(set (match_operand:V8QI 0 "register_operand" "=y") 357 [(set (match_operand:V8QI 0 "register_operand" "=y")
196 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") 358 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
197 (match_operand:V8QI 2 "register_operand" "y")))] 359 (match_operand:V8QI 2 "register_operand" "y")))]
198 "TARGET_REALLY_IWMMXT" 360 "TARGET_REALLY_IWMMXT"
199 "waddbss%?\\t%0, %1, %2" 361 "waddbss%?\\t%0, %1, %2"
200 [(set_attr "predicable" "yes")]) 362 [(set_attr "predicable" "yes")
363 (set_attr "type" "wmmx_wadd")]
364 )
201 365
202 (define_insn "ssaddv4hi3" 366 (define_insn "ssaddv4hi3"
203 [(set (match_operand:V4HI 0 "register_operand" "=y") 367 [(set (match_operand:V4HI 0 "register_operand" "=y")
204 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") 368 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
205 (match_operand:V4HI 2 "register_operand" "y")))] 369 (match_operand:V4HI 2 "register_operand" "y")))]
206 "TARGET_REALLY_IWMMXT" 370 "TARGET_REALLY_IWMMXT"
207 "waddhss%?\\t%0, %1, %2" 371 "waddhss%?\\t%0, %1, %2"
208 [(set_attr "predicable" "yes")]) 372 [(set_attr "predicable" "yes")
373 (set_attr "type" "wmmx_wadd")]
374 )
209 375
210 (define_insn "ssaddv2si3" 376 (define_insn "ssaddv2si3"
211 [(set (match_operand:V2SI 0 "register_operand" "=y") 377 [(set (match_operand:V2SI 0 "register_operand" "=y")
212 (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") 378 (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
213 (match_operand:V2SI 2 "register_operand" "y")))] 379 (match_operand:V2SI 2 "register_operand" "y")))]
214 "TARGET_REALLY_IWMMXT" 380 "TARGET_REALLY_IWMMXT"
215 "waddwss%?\\t%0, %1, %2" 381 "waddwss%?\\t%0, %1, %2"
216 [(set_attr "predicable" "yes")]) 382 [(set_attr "predicable" "yes")
383 (set_attr "type" "wmmx_wadd")]
384 )
217 385
218 (define_insn "usaddv8qi3" 386 (define_insn "usaddv8qi3"
219 [(set (match_operand:V8QI 0 "register_operand" "=y") 387 [(set (match_operand:V8QI 0 "register_operand" "=y")
220 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") 388 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
221 (match_operand:V8QI 2 "register_operand" "y")))] 389 (match_operand:V8QI 2 "register_operand" "y")))]
222 "TARGET_REALLY_IWMMXT" 390 "TARGET_REALLY_IWMMXT"
223 "waddbus%?\\t%0, %1, %2" 391 "waddbus%?\\t%0, %1, %2"
224 [(set_attr "predicable" "yes")]) 392 [(set_attr "predicable" "yes")
393 (set_attr "type" "wmmx_wadd")]
394 )
225 395
226 (define_insn "usaddv4hi3" 396 (define_insn "usaddv4hi3"
227 [(set (match_operand:V4HI 0 "register_operand" "=y") 397 [(set (match_operand:V4HI 0 "register_operand" "=y")
228 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") 398 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
229 (match_operand:V4HI 2 "register_operand" "y")))] 399 (match_operand:V4HI 2 "register_operand" "y")))]
230 "TARGET_REALLY_IWMMXT" 400 "TARGET_REALLY_IWMMXT"
231 "waddhus%?\\t%0, %1, %2" 401 "waddhus%?\\t%0, %1, %2"
232 [(set_attr "predicable" "yes")]) 402 [(set_attr "predicable" "yes")
403 (set_attr "type" "wmmx_wadd")]
404 )
233 405
234 (define_insn "usaddv2si3" 406 (define_insn "usaddv2si3"
235 [(set (match_operand:V2SI 0 "register_operand" "=y") 407 [(set (match_operand:V2SI 0 "register_operand" "=y")
236 (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") 408 (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
237 (match_operand:V2SI 2 "register_operand" "y")))] 409 (match_operand:V2SI 2 "register_operand" "y")))]
238 "TARGET_REALLY_IWMMXT" 410 "TARGET_REALLY_IWMMXT"
239 "waddwus%?\\t%0, %1, %2" 411 "waddwus%?\\t%0, %1, %2"
240 [(set_attr "predicable" "yes")]) 412 [(set_attr "predicable" "yes")
413 (set_attr "type" "wmmx_wadd")]
414 )
241 415
242 (define_insn "*sub<mode>3_iwmmxt" 416 (define_insn "*sub<mode>3_iwmmxt"
243 [(set (match_operand:VMMX 0 "register_operand" "=y") 417 [(set (match_operand:VMMX 0 "register_operand" "=y")
244 (minus:VMMX (match_operand:VMMX 1 "register_operand" "y") 418 (minus:VMMX (match_operand:VMMX 1 "register_operand" "y")
245 (match_operand:VMMX 2 "register_operand" "y")))] 419 (match_operand:VMMX 2 "register_operand" "y")))]
246 "TARGET_REALLY_IWMMXT" 420 "TARGET_REALLY_IWMMXT"
247 "wsub<MMX_char>%?\\t%0, %1, %2" 421 "wsub<MMX_char>%?\\t%0, %1, %2"
248 [(set_attr "predicable" "yes")]) 422 [(set_attr "predicable" "yes")
423 (set_attr "type" "wmmx_wsub")]
424 )
249 425
250 (define_insn "sssubv8qi3" 426 (define_insn "sssubv8qi3"
251 [(set (match_operand:V8QI 0 "register_operand" "=y") 427 [(set (match_operand:V8QI 0 "register_operand" "=y")
252 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") 428 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
253 (match_operand:V8QI 2 "register_operand" "y")))] 429 (match_operand:V8QI 2 "register_operand" "y")))]
254 "TARGET_REALLY_IWMMXT" 430 "TARGET_REALLY_IWMMXT"
255 "wsubbss%?\\t%0, %1, %2" 431 "wsubbss%?\\t%0, %1, %2"
256 [(set_attr "predicable" "yes")]) 432 [(set_attr "predicable" "yes")
433 (set_attr "type" "wmmx_wsub")]
434 )
257 435
258 (define_insn "sssubv4hi3" 436 (define_insn "sssubv4hi3"
259 [(set (match_operand:V4HI 0 "register_operand" "=y") 437 [(set (match_operand:V4HI 0 "register_operand" "=y")
260 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") 438 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
261 (match_operand:V4HI 2 "register_operand" "y")))] 439 (match_operand:V4HI 2 "register_operand" "y")))]
262 "TARGET_REALLY_IWMMXT" 440 "TARGET_REALLY_IWMMXT"
263 "wsubhss%?\\t%0, %1, %2" 441 "wsubhss%?\\t%0, %1, %2"
264 [(set_attr "predicable" "yes")]) 442 [(set_attr "predicable" "yes")
443 (set_attr "type" "wmmx_wsub")]
444 )
265 445
266 (define_insn "sssubv2si3" 446 (define_insn "sssubv2si3"
267 [(set (match_operand:V2SI 0 "register_operand" "=y") 447 [(set (match_operand:V2SI 0 "register_operand" "=y")
268 (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") 448 (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
269 (match_operand:V2SI 2 "register_operand" "y")))] 449 (match_operand:V2SI 2 "register_operand" "y")))]
270 "TARGET_REALLY_IWMMXT" 450 "TARGET_REALLY_IWMMXT"
271 "wsubwss%?\\t%0, %1, %2" 451 "wsubwss%?\\t%0, %1, %2"
272 [(set_attr "predicable" "yes")]) 452 [(set_attr "predicable" "yes")
453 (set_attr "type" "wmmx_wsub")]
454 )
273 455
274 (define_insn "ussubv8qi3" 456 (define_insn "ussubv8qi3"
275 [(set (match_operand:V8QI 0 "register_operand" "=y") 457 [(set (match_operand:V8QI 0 "register_operand" "=y")
276 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") 458 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
277 (match_operand:V8QI 2 "register_operand" "y")))] 459 (match_operand:V8QI 2 "register_operand" "y")))]
278 "TARGET_REALLY_IWMMXT" 460 "TARGET_REALLY_IWMMXT"
279 "wsubbus%?\\t%0, %1, %2" 461 "wsubbus%?\\t%0, %1, %2"
280 [(set_attr "predicable" "yes")]) 462 [(set_attr "predicable" "yes")
463 (set_attr "type" "wmmx_wsub")]
464 )
281 465
282 (define_insn "ussubv4hi3" 466 (define_insn "ussubv4hi3"
283 [(set (match_operand:V4HI 0 "register_operand" "=y") 467 [(set (match_operand:V4HI 0 "register_operand" "=y")
284 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") 468 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
285 (match_operand:V4HI 2 "register_operand" "y")))] 469 (match_operand:V4HI 2 "register_operand" "y")))]
286 "TARGET_REALLY_IWMMXT" 470 "TARGET_REALLY_IWMMXT"
287 "wsubhus%?\\t%0, %1, %2" 471 "wsubhus%?\\t%0, %1, %2"
288 [(set_attr "predicable" "yes")]) 472 [(set_attr "predicable" "yes")
473 (set_attr "type" "wmmx_wsub")]
474 )
289 475
290 (define_insn "ussubv2si3" 476 (define_insn "ussubv2si3"
291 [(set (match_operand:V2SI 0 "register_operand" "=y") 477 [(set (match_operand:V2SI 0 "register_operand" "=y")
292 (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") 478 (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
293 (match_operand:V2SI 2 "register_operand" "y")))] 479 (match_operand:V2SI 2 "register_operand" "y")))]
294 "TARGET_REALLY_IWMMXT" 480 "TARGET_REALLY_IWMMXT"
295 "wsubwus%?\\t%0, %1, %2" 481 "wsubwus%?\\t%0, %1, %2"
296 [(set_attr "predicable" "yes")]) 482 [(set_attr "predicable" "yes")
483 (set_attr "type" "wmmx_wsub")]
484 )
297 485
298 (define_insn "*mulv4hi3_iwmmxt" 486 (define_insn "*mulv4hi3_iwmmxt"
299 [(set (match_operand:V4HI 0 "register_operand" "=y") 487 [(set (match_operand:V4HI 0 "register_operand" "=y")
300 (mult:V4HI (match_operand:V4HI 1 "register_operand" "y") 488 (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
301 (match_operand:V4HI 2 "register_operand" "y")))] 489 (match_operand:V4HI 2 "register_operand" "y")))]
302 "TARGET_REALLY_IWMMXT" 490 "TARGET_REALLY_IWMMXT"
303 "wmulul%?\\t%0, %1, %2" 491 "wmulul%?\\t%0, %1, %2"
304 [(set_attr "predicable" "yes")]) 492 [(set_attr "predicable" "yes")
493 (set_attr "type" "wmmx_wmul")]
494 )
305 495
306 (define_insn "smulv4hi3_highpart" 496 (define_insn "smulv4hi3_highpart"
307 [(set (match_operand:V4HI 0 "register_operand" "=y") 497 [(set (match_operand:V4HI 0 "register_operand" "=y")
308 (truncate:V4HI 498 (truncate:V4HI
309 (lshiftrt:V4SI 499 (lshiftrt:V4SI
310 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) 500 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
311 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) 501 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
312 (const_int 16))))] 502 (const_int 16))))]
313 "TARGET_REALLY_IWMMXT" 503 "TARGET_REALLY_IWMMXT"
314 "wmulsm%?\\t%0, %1, %2" 504 "wmulsm%?\\t%0, %1, %2"
315 [(set_attr "predicable" "yes")]) 505 [(set_attr "predicable" "yes")
506 (set_attr "type" "wmmx_wmul")]
507 )
316 508
317 (define_insn "umulv4hi3_highpart" 509 (define_insn "umulv4hi3_highpart"
318 [(set (match_operand:V4HI 0 "register_operand" "=y") 510 [(set (match_operand:V4HI 0 "register_operand" "=y")
319 (truncate:V4HI 511 (truncate:V4HI
320 (lshiftrt:V4SI 512 (lshiftrt:V4SI
321 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) 513 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
322 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) 514 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
323 (const_int 16))))] 515 (const_int 16))))]
324 "TARGET_REALLY_IWMMXT" 516 "TARGET_REALLY_IWMMXT"
325 "wmulum%?\\t%0, %1, %2" 517 "wmulum%?\\t%0, %1, %2"
326 [(set_attr "predicable" "yes")]) 518 [(set_attr "predicable" "yes")
519 (set_attr "type" "wmmx_wmul")]
520 )
327 521
328 (define_insn "iwmmxt_wmacs" 522 (define_insn "iwmmxt_wmacs"
329 [(set (match_operand:DI 0 "register_operand" "=y") 523 [(set (match_operand:DI 0 "register_operand" "=y")
330 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 524 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
331 (match_operand:V4HI 2 "register_operand" "y") 525 (match_operand:V4HI 2 "register_operand" "y")
332 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))] 526 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
333 "TARGET_REALLY_IWMMXT" 527 "TARGET_REALLY_IWMMXT"
334 "wmacs%?\\t%0, %2, %3" 528 "wmacs%?\\t%0, %2, %3"
335 [(set_attr "predicable" "yes")]) 529 [(set_attr "predicable" "yes")
530 (set_attr "type" "wmmx_wmac")]
531 )
336 532
337 (define_insn "iwmmxt_wmacsz" 533 (define_insn "iwmmxt_wmacsz"
338 [(set (match_operand:DI 0 "register_operand" "=y") 534 [(set (match_operand:DI 0 "register_operand" "=y")
339 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") 535 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
340 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))] 536 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
341 "TARGET_REALLY_IWMMXT" 537 "TARGET_REALLY_IWMMXT"
342 "wmacsz%?\\t%0, %1, %2" 538 "wmacsz%?\\t%0, %1, %2"
343 [(set_attr "predicable" "yes")]) 539 [(set_attr "predicable" "yes")
540 (set_attr "type" "wmmx_wmac")]
541 )
344 542
345 (define_insn "iwmmxt_wmacu" 543 (define_insn "iwmmxt_wmacu"
346 [(set (match_operand:DI 0 "register_operand" "=y") 544 [(set (match_operand:DI 0 "register_operand" "=y")
347 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 545 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
348 (match_operand:V4HI 2 "register_operand" "y") 546 (match_operand:V4HI 2 "register_operand" "y")
349 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))] 547 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
350 "TARGET_REALLY_IWMMXT" 548 "TARGET_REALLY_IWMMXT"
351 "wmacu%?\\t%0, %2, %3" 549 "wmacu%?\\t%0, %2, %3"
352 [(set_attr "predicable" "yes")]) 550 [(set_attr "predicable" "yes")
551 (set_attr "type" "wmmx_wmac")]
552 )
353 553
354 (define_insn "iwmmxt_wmacuz" 554 (define_insn "iwmmxt_wmacuz"
355 [(set (match_operand:DI 0 "register_operand" "=y") 555 [(set (match_operand:DI 0 "register_operand" "=y")
356 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") 556 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
357 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))] 557 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
358 "TARGET_REALLY_IWMMXT" 558 "TARGET_REALLY_IWMMXT"
359 "wmacuz%?\\t%0, %1, %2" 559 "wmacuz%?\\t%0, %1, %2"
360 [(set_attr "predicable" "yes")]) 560 [(set_attr "predicable" "yes")
561 (set_attr "type" "wmmx_wmac")]
562 )
361 563
362 ;; Same as xordi3, but don't show input operands so that we don't think 564 ;; Same as xordi3, but don't show input operands so that we don't think
363 ;; they are live. 565 ;; they are live.
364 (define_insn "iwmmxt_clrdi" 566 (define_insn "iwmmxt_clrdi"
365 [(set (match_operand:DI 0 "register_operand" "=y") 567 [(set (match_operand:DI 0 "register_operand" "=y")
366 (unspec:DI [(const_int 0)] UNSPEC_CLRDI))] 568 (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
367 "TARGET_REALLY_IWMMXT" 569 "TARGET_REALLY_IWMMXT"
368 "wxor%?\\t%0, %0, %0" 570 "wxor%?\\t%0, %0, %0"
369 [(set_attr "predicable" "yes")]) 571 [(set_attr "predicable" "yes")
572 (set_attr "type" "wmmx_wxor")]
573 )
370 574
371 ;; Seems like cse likes to generate these, so we have to support them. 575 ;; Seems like cse likes to generate these, so we have to support them.
372 576
373 (define_insn "*iwmmxt_clrv8qi" 577 (define_insn "iwmmxt_clrv8qi"
374 [(set (match_operand:V8QI 0 "register_operand" "=y") 578 [(set (match_operand:V8QI 0 "s_register_operand" "=y")
375 (const_vector:V8QI [(const_int 0) (const_int 0) 579 (const_vector:V8QI [(const_int 0) (const_int 0)
376 (const_int 0) (const_int 0) 580 (const_int 0) (const_int 0)
377 (const_int 0) (const_int 0) 581 (const_int 0) (const_int 0)
378 (const_int 0) (const_int 0)]))] 582 (const_int 0) (const_int 0)]))]
379 "TARGET_REALLY_IWMMXT" 583 "TARGET_REALLY_IWMMXT"
380 "wxor%?\\t%0, %0, %0" 584 "wxor%?\\t%0, %0, %0"
381 [(set_attr "predicable" "yes")]) 585 [(set_attr "predicable" "yes")
382 586 (set_attr "type" "wmmx_wxor")]
383 (define_insn "*iwmmxt_clrv4hi" 587 )
384 [(set (match_operand:V4HI 0 "register_operand" "=y") 588
589 (define_insn "iwmmxt_clrv4hi"
590 [(set (match_operand:V4HI 0 "s_register_operand" "=y")
385 (const_vector:V4HI [(const_int 0) (const_int 0) 591 (const_vector:V4HI [(const_int 0) (const_int 0)
386 (const_int 0) (const_int 0)]))] 592 (const_int 0) (const_int 0)]))]
387 "TARGET_REALLY_IWMMXT" 593 "TARGET_REALLY_IWMMXT"
388 "wxor%?\\t%0, %0, %0" 594 "wxor%?\\t%0, %0, %0"
389 [(set_attr "predicable" "yes")]) 595 [(set_attr "predicable" "yes")
390 596 (set_attr "type" "wmmx_wxor")]
391 (define_insn "*iwmmxt_clrv2si" 597 )
598
599 (define_insn "iwmmxt_clrv2si"
392 [(set (match_operand:V2SI 0 "register_operand" "=y") 600 [(set (match_operand:V2SI 0 "register_operand" "=y")
393 (const_vector:V2SI [(const_int 0) (const_int 0)]))] 601 (const_vector:V2SI [(const_int 0) (const_int 0)]))]
394 "TARGET_REALLY_IWMMXT" 602 "TARGET_REALLY_IWMMXT"
395 "wxor%?\\t%0, %0, %0" 603 "wxor%?\\t%0, %0, %0"
396 [(set_attr "predicable" "yes")]) 604 [(set_attr "predicable" "yes")
605 (set_attr "type" "wmmx_wxor")]
606 )
397 607
398 ;; Unsigned averages/sum of absolute differences 608 ;; Unsigned averages/sum of absolute differences
399 609
400 (define_insn "iwmmxt_uavgrndv8qi3" 610 (define_insn "iwmmxt_uavgrndv8qi3"
401 [(set (match_operand:V8QI 0 "register_operand" "=y") 611 [(set (match_operand:V8QI 0 "register_operand" "=y")
402 (ashiftrt:V8QI 612 (truncate:V8QI
403 (plus:V8QI (plus:V8QI 613 (lshiftrt:V8HI
404 (match_operand:V8QI 1 "register_operand" "y") 614 (plus:V8HI
405 (match_operand:V8QI 2 "register_operand" "y")) 615 (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
406 (const_vector:V8QI [(const_int 1) 616 (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
407 (const_int 1) 617 (const_vector:V8HI [(const_int 1)
408 (const_int 1) 618 (const_int 1)
409 (const_int 1) 619 (const_int 1)
410 (const_int 1) 620 (const_int 1)
411 (const_int 1) 621 (const_int 1)
412 (const_int 1) 622 (const_int 1)
413 (const_int 1)])) 623 (const_int 1)
414 (const_int 1)))] 624 (const_int 1)]))
625 (const_int 1))))]
415 "TARGET_REALLY_IWMMXT" 626 "TARGET_REALLY_IWMMXT"
416 "wavg2br%?\\t%0, %1, %2" 627 "wavg2br%?\\t%0, %1, %2"
417 [(set_attr "predicable" "yes")]) 628 [(set_attr "predicable" "yes")
629 (set_attr "type" "wmmx_wavg2")]
630 )
418 631
419 (define_insn "iwmmxt_uavgrndv4hi3" 632 (define_insn "iwmmxt_uavgrndv4hi3"
420 [(set (match_operand:V4HI 0 "register_operand" "=y") 633 [(set (match_operand:V4HI 0 "register_operand" "=y")
421 (ashiftrt:V4HI 634 (truncate:V4HI
422 (plus:V4HI (plus:V4HI 635 (lshiftrt:V4SI
423 (match_operand:V4HI 1 "register_operand" "y") 636 (plus:V4SI
424 (match_operand:V4HI 2 "register_operand" "y")) 637 (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
425 (const_vector:V4HI [(const_int 1) 638 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
426 (const_int 1) 639 (const_vector:V4SI [(const_int 1)
427 (const_int 1) 640 (const_int 1)
428 (const_int 1)])) 641 (const_int 1)
429 (const_int 1)))] 642 (const_int 1)]))
643 (const_int 1))))]
430 "TARGET_REALLY_IWMMXT" 644 "TARGET_REALLY_IWMMXT"
431 "wavg2hr%?\\t%0, %1, %2" 645 "wavg2hr%?\\t%0, %1, %2"
432 [(set_attr "predicable" "yes")]) 646 [(set_attr "predicable" "yes")
433 647 (set_attr "type" "wmmx_wavg2")]
648 )
434 649
435 (define_insn "iwmmxt_uavgv8qi3" 650 (define_insn "iwmmxt_uavgv8qi3"
436 [(set (match_operand:V8QI 0 "register_operand" "=y") 651 [(set (match_operand:V8QI 0 "register_operand" "=y")
437 (ashiftrt:V8QI (plus:V8QI 652 (truncate:V8QI
438 (match_operand:V8QI 1 "register_operand" "y") 653 (lshiftrt:V8HI
439 (match_operand:V8QI 2 "register_operand" "y")) 654 (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
440 (const_int 1)))] 655 (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
656 (const_int 1))))]
441 "TARGET_REALLY_IWMMXT" 657 "TARGET_REALLY_IWMMXT"
442 "wavg2b%?\\t%0, %1, %2" 658 "wavg2b%?\\t%0, %1, %2"
443 [(set_attr "predicable" "yes")]) 659 [(set_attr "predicable" "yes")
660 (set_attr "type" "wmmx_wavg2")]
661 )
444 662
445 (define_insn "iwmmxt_uavgv4hi3" 663 (define_insn "iwmmxt_uavgv4hi3"
446 [(set (match_operand:V4HI 0 "register_operand" "=y") 664 [(set (match_operand:V4HI 0 "register_operand" "=y")
447 (ashiftrt:V4HI (plus:V4HI 665 (truncate:V4HI
448 (match_operand:V4HI 1 "register_operand" "y") 666 (lshiftrt:V4SI
449 (match_operand:V4HI 2 "register_operand" "y")) 667 (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
450 (const_int 1)))] 668 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
669 (const_int 1))))]
451 "TARGET_REALLY_IWMMXT" 670 "TARGET_REALLY_IWMMXT"
452 "wavg2h%?\\t%0, %1, %2" 671 "wavg2h%?\\t%0, %1, %2"
453 [(set_attr "predicable" "yes")]) 672 [(set_attr "predicable" "yes")
454 673 (set_attr "type" "wmmx_wavg2")]
455 (define_insn "iwmmxt_psadbw" 674 )
456 [(set (match_operand:V8QI 0 "register_operand" "=y")
457 (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
458 (match_operand:V8QI 2 "register_operand" "y"))))]
459 "TARGET_REALLY_IWMMXT"
460 "psadbw%?\\t%0, %1, %2"
461 [(set_attr "predicable" "yes")])
462
463 675
464 ;; Insert/extract/shuffle 676 ;; Insert/extract/shuffle
465 677
466 (define_insn "iwmmxt_tinsrb" 678 (define_insn "iwmmxt_tinsrb"
467 [(set (match_operand:V8QI 0 "register_operand" "=y") 679 [(set (match_operand:V8QI 0 "register_operand" "=y")
468 (vec_merge:V8QI (match_operand:V8QI 1 "register_operand" "0") 680 (vec_merge:V8QI
469 (vec_duplicate:V8QI 681 (vec_duplicate:V8QI
470 (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r"))) 682 (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
471 (match_operand:SI 3 "immediate_operand" "i")))] 683 (match_operand:V8QI 1 "register_operand" "0")
472 "TARGET_REALLY_IWMMXT" 684 (match_operand:SI 3 "immediate_operand" "i")))]
473 "tinsrb%?\\t%0, %2, %3" 685 "TARGET_REALLY_IWMMXT"
474 [(set_attr "predicable" "yes")]) 686 "*
687 {
688 return arm_output_iwmmxt_tinsr (operands);
689 }
690 "
691 [(set_attr "predicable" "yes")
692 (set_attr "type" "wmmx_tinsr")]
693 )
475 694
476 (define_insn "iwmmxt_tinsrh" 695 (define_insn "iwmmxt_tinsrh"
477 [(set (match_operand:V4HI 0 "register_operand" "=y") 696 [(set (match_operand:V4HI 0 "register_operand" "=y")
478 (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0") 697 (vec_merge:V4HI
479 (vec_duplicate:V4HI 698 (vec_duplicate:V4HI
480 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r"))) 699 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
481 (match_operand:SI 3 "immediate_operand" "i")))] 700 (match_operand:V4HI 1 "register_operand" "0")
482 "TARGET_REALLY_IWMMXT" 701 (match_operand:SI 3 "immediate_operand" "i")))]
483 "tinsrh%?\\t%0, %2, %3" 702 "TARGET_REALLY_IWMMXT"
484 [(set_attr "predicable" "yes")]) 703 "*
704 {
705 return arm_output_iwmmxt_tinsr (operands);
706 }
707 "
708 [(set_attr "predicable" "yes")
709 (set_attr "type" "wmmx_tinsr")]
710 )
485 711
486 (define_insn "iwmmxt_tinsrw" 712 (define_insn "iwmmxt_tinsrw"
487 [(set (match_operand:V2SI 0 "register_operand" "=y") 713 [(set (match_operand:V2SI 0 "register_operand" "=y")
488 (vec_merge:V2SI (match_operand:V2SI 1 "register_operand" "0") 714 (vec_merge:V2SI
489 (vec_duplicate:V2SI 715 (vec_duplicate:V2SI
490 (match_operand:SI 2 "nonimmediate_operand" "r")) 716 (match_operand:SI 2 "nonimmediate_operand" "r"))
491 (match_operand:SI 3 "immediate_operand" "i")))] 717 (match_operand:V2SI 1 "register_operand" "0")
492 "TARGET_REALLY_IWMMXT" 718 (match_operand:SI 3 "immediate_operand" "i")))]
493 "tinsrw%?\\t%0, %2, %3" 719 "TARGET_REALLY_IWMMXT"
494 [(set_attr "predicable" "yes")]) 720 "*
721 {
722 return arm_output_iwmmxt_tinsr (operands);
723 }
724 "
725 [(set_attr "predicable" "yes")
726 (set_attr "type" "wmmx_tinsr")]
727 )
495 728
496 (define_insn "iwmmxt_textrmub" 729 (define_insn "iwmmxt_textrmub"
497 [(set (match_operand:SI 0 "register_operand" "=r") 730 [(set (match_operand:SI 0 "register_operand" "=r")
498 (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") 731 (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
732 (parallel
733 [(match_operand:SI 2 "immediate_operand" "i")]))))]
734 "TARGET_REALLY_IWMMXT"
735 "textrmub%?\\t%0, %1, %2"
736 [(set_attr "predicable" "yes")
737 (set_attr "type" "wmmx_textrm")]
738 )
739
740 (define_insn "iwmmxt_textrmsb"
741 [(set (match_operand:SI 0 "register_operand" "=r")
742 (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
499 (parallel 743 (parallel
500 [(match_operand:SI 2 "immediate_operand" "i")]))))] 744 [(match_operand:SI 2 "immediate_operand" "i")]))))]
501 "TARGET_REALLY_IWMMXT" 745 "TARGET_REALLY_IWMMXT"
502 "textrmub%?\\t%0, %1, %2" 746 "textrmsb%?\\t%0, %1, %2"
503 [(set_attr "predicable" "yes")]) 747 [(set_attr "predicable" "yes")
504 748 (set_attr "type" "wmmx_textrm")]
505 (define_insn "iwmmxt_textrmsb" 749 )
506 [(set (match_operand:SI 0 "register_operand" "=r") 750
507 (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") 751 (define_insn "iwmmxt_textrmuh"
752 [(set (match_operand:SI 0 "register_operand" "=r")
753 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
508 (parallel 754 (parallel
509 [(match_operand:SI 2 "immediate_operand" "i")]))))] 755 [(match_operand:SI 2 "immediate_operand" "i")]))))]
510 "TARGET_REALLY_IWMMXT" 756 "TARGET_REALLY_IWMMXT"
511 "textrmsb%?\\t%0, %1, %2" 757 "textrmuh%?\\t%0, %1, %2"
512 [(set_attr "predicable" "yes")]) 758 [(set_attr "predicable" "yes")
513 759 (set_attr "type" "wmmx_textrm")]
514 (define_insn "iwmmxt_textrmuh" 760 )
515 [(set (match_operand:SI 0 "register_operand" "=r") 761
516 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") 762 (define_insn "iwmmxt_textrmsh"
763 [(set (match_operand:SI 0 "register_operand" "=r")
764 (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
517 (parallel 765 (parallel
518 [(match_operand:SI 2 "immediate_operand" "i")]))))] 766 [(match_operand:SI 2 "immediate_operand" "i")]))))]
519 "TARGET_REALLY_IWMMXT"
520 "textrmuh%?\\t%0, %1, %2"
521 [(set_attr "predicable" "yes")])
522
523 (define_insn "iwmmxt_textrmsh"
524 [(set (match_operand:SI 0 "register_operand" "=r")
525 (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
526 (parallel
527 [(match_operand:SI 2 "immediate_operand" "i")]))))]
528 "TARGET_REALLY_IWMMXT" 767 "TARGET_REALLY_IWMMXT"
529 "textrmsh%?\\t%0, %1, %2" 768 "textrmsh%?\\t%0, %1, %2"
530 [(set_attr "predicable" "yes")]) 769 [(set_attr "predicable" "yes")
770 (set_attr "type" "wmmx_textrm")]
771 )
531 772
532 ;; There are signed/unsigned variants of this instruction, but they are 773 ;; There are signed/unsigned variants of this instruction, but they are
533 ;; pointless. 774 ;; pointless.
534 (define_insn "iwmmxt_textrmw" 775 (define_insn "iwmmxt_textrmw"
535 [(set (match_operand:SI 0 "register_operand" "=r") 776 [(set (match_operand:SI 0 "register_operand" "=r")
536 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 777 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
537 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] 778 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
538 "TARGET_REALLY_IWMMXT" 779 "TARGET_REALLY_IWMMXT"
539 "textrmsw%?\\t%0, %1, %2" 780 "textrmsw%?\\t%0, %1, %2"
540 [(set_attr "predicable" "yes")]) 781 [(set_attr "predicable" "yes")
782 (set_attr "type" "wmmx_textrm")]
783 )
541 784
542 (define_insn "iwmmxt_wshufh" 785 (define_insn "iwmmxt_wshufh"
543 [(set (match_operand:V4HI 0 "register_operand" "=y") 786 [(set (match_operand:V4HI 0 "register_operand" "=y")
544 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 787 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
545 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))] 788 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
546 "TARGET_REALLY_IWMMXT" 789 "TARGET_REALLY_IWMMXT"
547 "wshufh%?\\t%0, %1, %2" 790 "wshufh%?\\t%0, %1, %2"
548 [(set_attr "predicable" "yes")]) 791 [(set_attr "predicable" "yes")
792 (set_attr "type" "wmmx_wshufh")]
793 )
549 794
550 ;; Mask-generating comparisons 795 ;; Mask-generating comparisons
551 ;; 796 ;;
552 ;; Note - you cannot use patterns like these here: 797 ;; Note - you cannot use patterns like these here:
553 ;; 798 ;;
555 ;; 800 ;;
556 ;; Because GCC will assume that the truth value (1 or 0) is installed 801 ;; Because GCC will assume that the truth value (1 or 0) is installed
557 ;; into the entire destination vector, (with the '1' going into the least 802 ;; into the entire destination vector, (with the '1' going into the least
558 ;; significant element of the vector). This is not how these instructions 803 ;; significant element of the vector). This is not how these instructions
559 ;; behave. 804 ;; behave.
560 ;;
561 ;; Unfortunately the current patterns are illegal. They are SET insns
562 ;; without a SET in them. They work in most cases for ordinary code
563 ;; generation, but there are circumstances where they can cause gcc to fail.
564 ;; XXX - FIXME.
565 805
566 (define_insn "eqv8qi3" 806 (define_insn "eqv8qi3"
567 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y") 807 [(set (match_operand:V8QI 0 "register_operand" "=y")
568 (match_operand:V8QI 1 "register_operand" "y") 808 (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y")
569 (match_operand:V8QI 2 "register_operand" "y")] 809 (match_operand:V8QI 2 "register_operand" "y")]
570 VUNSPEC_WCMP_EQ)] 810 VUNSPEC_WCMP_EQ))]
571 "TARGET_REALLY_IWMMXT" 811 "TARGET_REALLY_IWMMXT"
572 "wcmpeqb%?\\t%0, %1, %2" 812 "wcmpeqb%?\\t%0, %1, %2"
573 [(set_attr "predicable" "yes")]) 813 [(set_attr "predicable" "yes")
814 (set_attr "type" "wmmx_wcmpeq")]
815 )
574 816
575 (define_insn "eqv4hi3" 817 (define_insn "eqv4hi3"
576 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y") 818 [(set (match_operand:V4HI 0 "register_operand" "=y")
577 (match_operand:V4HI 1 "register_operand" "y") 819 (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y")
578 (match_operand:V4HI 2 "register_operand" "y")] 820 (match_operand:V4HI 2 "register_operand" "y")]
579 VUNSPEC_WCMP_EQ)] 821 VUNSPEC_WCMP_EQ))]
580 "TARGET_REALLY_IWMMXT" 822 "TARGET_REALLY_IWMMXT"
581 "wcmpeqh%?\\t%0, %1, %2" 823 "wcmpeqh%?\\t%0, %1, %2"
582 [(set_attr "predicable" "yes")]) 824 [(set_attr "predicable" "yes")
825 (set_attr "type" "wmmx_wcmpeq")]
826 )
583 827
584 (define_insn "eqv2si3" 828 (define_insn "eqv2si3"
585 [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y") 829 [(set (match_operand:V2SI 0 "register_operand" "=y")
586 (match_operand:V2SI 1 "register_operand" "y") 830 (unspec_volatile:V2SI
587 (match_operand:V2SI 2 "register_operand" "y")] 831 [(match_operand:V2SI 1 "register_operand" "y")
588 VUNSPEC_WCMP_EQ)] 832 (match_operand:V2SI 2 "register_operand" "y")]
833 VUNSPEC_WCMP_EQ))]
589 "TARGET_REALLY_IWMMXT" 834 "TARGET_REALLY_IWMMXT"
590 "wcmpeqw%?\\t%0, %1, %2" 835 "wcmpeqw%?\\t%0, %1, %2"
591 [(set_attr "predicable" "yes")]) 836 [(set_attr "predicable" "yes")
837 (set_attr "type" "wmmx_wcmpeq")]
838 )
592 839
593 (define_insn "gtuv8qi3" 840 (define_insn "gtuv8qi3"
594 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y") 841 [(set (match_operand:V8QI 0 "register_operand" "=y")
595 (match_operand:V8QI 1 "register_operand" "y") 842 (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y")
596 (match_operand:V8QI 2 "register_operand" "y")] 843 (match_operand:V8QI 2 "register_operand" "y")]
597 VUNSPEC_WCMP_GTU)] 844 VUNSPEC_WCMP_GTU))]
598 "TARGET_REALLY_IWMMXT" 845 "TARGET_REALLY_IWMMXT"
599 "wcmpgtub%?\\t%0, %1, %2" 846 "wcmpgtub%?\\t%0, %1, %2"
600 [(set_attr "predicable" "yes")]) 847 [(set_attr "predicable" "yes")
848 (set_attr "type" "wmmx_wcmpgt")]
849 )
601 850
602 (define_insn "gtuv4hi3" 851 (define_insn "gtuv4hi3"
603 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y") 852 [(set (match_operand:V4HI 0 "register_operand" "=y")
604 (match_operand:V4HI 1 "register_operand" "y") 853 (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y")
605 (match_operand:V4HI 2 "register_operand" "y")] 854 (match_operand:V4HI 2 "register_operand" "y")]
606 VUNSPEC_WCMP_GTU)] 855 VUNSPEC_WCMP_GTU))]
607 "TARGET_REALLY_IWMMXT" 856 "TARGET_REALLY_IWMMXT"
608 "wcmpgtuh%?\\t%0, %1, %2" 857 "wcmpgtuh%?\\t%0, %1, %2"
609 [(set_attr "predicable" "yes")]) 858 [(set_attr "predicable" "yes")
859 (set_attr "type" "wmmx_wcmpgt")]
860 )
610 861
611 (define_insn "gtuv2si3" 862 (define_insn "gtuv2si3"
612 [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y") 863 [(set (match_operand:V2SI 0 "register_operand" "=y")
613 (match_operand:V2SI 1 "register_operand" "y") 864 (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y")
614 (match_operand:V2SI 2 "register_operand" "y")] 865 (match_operand:V2SI 2 "register_operand" "y")]
615 VUNSPEC_WCMP_GTU)] 866 VUNSPEC_WCMP_GTU))]
616 "TARGET_REALLY_IWMMXT" 867 "TARGET_REALLY_IWMMXT"
617 "wcmpgtuw%?\\t%0, %1, %2" 868 "wcmpgtuw%?\\t%0, %1, %2"
618 [(set_attr "predicable" "yes")]) 869 [(set_attr "predicable" "yes")
870 (set_attr "type" "wmmx_wcmpgt")]
871 )
619 872
620 (define_insn "gtv8qi3" 873 (define_insn "gtv8qi3"
621 [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y") 874 [(set (match_operand:V8QI 0 "register_operand" "=y")
622 (match_operand:V8QI 1 "register_operand" "y") 875 (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y")
623 (match_operand:V8QI 2 "register_operand" "y")] 876 (match_operand:V8QI 2 "register_operand" "y")]
624 VUNSPEC_WCMP_GT)] 877 VUNSPEC_WCMP_GT))]
625 "TARGET_REALLY_IWMMXT" 878 "TARGET_REALLY_IWMMXT"
626 "wcmpgtsb%?\\t%0, %1, %2" 879 "wcmpgtsb%?\\t%0, %1, %2"
627 [(set_attr "predicable" "yes")]) 880 [(set_attr "predicable" "yes")
881 (set_attr "type" "wmmx_wcmpgt")]
882 )
628 883
629 (define_insn "gtv4hi3" 884 (define_insn "gtv4hi3"
630 [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y") 885 [(set (match_operand:V4HI 0 "register_operand" "=y")
631 (match_operand:V4HI 1 "register_operand" "y") 886 (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y")
632 (match_operand:V4HI 2 "register_operand" "y")] 887 (match_operand:V4HI 2 "register_operand" "y")]
633 VUNSPEC_WCMP_GT)] 888 VUNSPEC_WCMP_GT))]
634 "TARGET_REALLY_IWMMXT" 889 "TARGET_REALLY_IWMMXT"
635 "wcmpgtsh%?\\t%0, %1, %2" 890 "wcmpgtsh%?\\t%0, %1, %2"
636 [(set_attr "predicable" "yes")]) 891 [(set_attr "predicable" "yes")
892 (set_attr "type" "wmmx_wcmpgt")]
893 )
637 894
638 (define_insn "gtv2si3" 895 (define_insn "gtv2si3"
639 [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y") 896 [(set (match_operand:V2SI 0 "register_operand" "=y")
640 (match_operand:V2SI 1 "register_operand" "y") 897 (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y")
641 (match_operand:V2SI 2 "register_operand" "y")] 898 (match_operand:V2SI 2 "register_operand" "y")]
642 VUNSPEC_WCMP_GT)] 899 VUNSPEC_WCMP_GT))]
643 "TARGET_REALLY_IWMMXT" 900 "TARGET_REALLY_IWMMXT"
644 "wcmpgtsw%?\\t%0, %1, %2" 901 "wcmpgtsw%?\\t%0, %1, %2"
645 [(set_attr "predicable" "yes")]) 902 [(set_attr "predicable" "yes")
903 (set_attr "type" "wmmx_wcmpgt")]
904 )
646 905
647 ;; Max/min insns 906 ;; Max/min insns
648 907
649 (define_insn "*smax<mode>3_iwmmxt" 908 (define_insn "*smax<mode>3_iwmmxt"
650 [(set (match_operand:VMMX 0 "register_operand" "=y") 909 [(set (match_operand:VMMX 0 "register_operand" "=y")
651 (smax:VMMX (match_operand:VMMX 1 "register_operand" "y") 910 (smax:VMMX (match_operand:VMMX 1 "register_operand" "y")
652 (match_operand:VMMX 2 "register_operand" "y")))] 911 (match_operand:VMMX 2 "register_operand" "y")))]
653 "TARGET_REALLY_IWMMXT" 912 "TARGET_REALLY_IWMMXT"
654 "wmaxs<MMX_char>%?\\t%0, %1, %2" 913 "wmaxs<MMX_char>%?\\t%0, %1, %2"
655 [(set_attr "predicable" "yes")]) 914 [(set_attr "predicable" "yes")
915 (set_attr "type" "wmmx_wmax")]
916 )
656 917
657 (define_insn "*umax<mode>3_iwmmxt" 918 (define_insn "*umax<mode>3_iwmmxt"
658 [(set (match_operand:VMMX 0 "register_operand" "=y") 919 [(set (match_operand:VMMX 0 "register_operand" "=y")
659 (umax:VMMX (match_operand:VMMX 1 "register_operand" "y") 920 (umax:VMMX (match_operand:VMMX 1 "register_operand" "y")
660 (match_operand:VMMX 2 "register_operand" "y")))] 921 (match_operand:VMMX 2 "register_operand" "y")))]
661 "TARGET_REALLY_IWMMXT" 922 "TARGET_REALLY_IWMMXT"
662 "wmaxu<MMX_char>%?\\t%0, %1, %2" 923 "wmaxu<MMX_char>%?\\t%0, %1, %2"
663 [(set_attr "predicable" "yes")]) 924 [(set_attr "predicable" "yes")
925 (set_attr "type" "wmmx_wmax")]
926 )
664 927
665 (define_insn "*smin<mode>3_iwmmxt" 928 (define_insn "*smin<mode>3_iwmmxt"
666 [(set (match_operand:VMMX 0 "register_operand" "=y") 929 [(set (match_operand:VMMX 0 "register_operand" "=y")
667 (smin:VMMX (match_operand:VMMX 1 "register_operand" "y") 930 (smin:VMMX (match_operand:VMMX 1 "register_operand" "y")
668 (match_operand:VMMX 2 "register_operand" "y")))] 931 (match_operand:VMMX 2 "register_operand" "y")))]
669 "TARGET_REALLY_IWMMXT" 932 "TARGET_REALLY_IWMMXT"
670 "wmins<MMX_char>%?\\t%0, %1, %2" 933 "wmins<MMX_char>%?\\t%0, %1, %2"
671 [(set_attr "predicable" "yes")]) 934 [(set_attr "predicable" "yes")
935 (set_attr "type" "wmmx_wmin")]
936 )
672 937
673 (define_insn "*umin<mode>3_iwmmxt" 938 (define_insn "*umin<mode>3_iwmmxt"
674 [(set (match_operand:VMMX 0 "register_operand" "=y") 939 [(set (match_operand:VMMX 0 "register_operand" "=y")
675 (umin:VMMX (match_operand:VMMX 1 "register_operand" "y") 940 (umin:VMMX (match_operand:VMMX 1 "register_operand" "y")
676 (match_operand:VMMX 2 "register_operand" "y")))] 941 (match_operand:VMMX 2 "register_operand" "y")))]
677 "TARGET_REALLY_IWMMXT" 942 "TARGET_REALLY_IWMMXT"
678 "wminu<MMX_char>%?\\t%0, %1, %2" 943 "wminu<MMX_char>%?\\t%0, %1, %2"
679 [(set_attr "predicable" "yes")]) 944 [(set_attr "predicable" "yes")
945 (set_attr "type" "wmmx_wmin")]
946 )
680 947
681 ;; Pack/unpack insns. 948 ;; Pack/unpack insns.
682 949
683 (define_insn "iwmmxt_wpackhss" 950 (define_insn "iwmmxt_wpackhss"
684 [(set (match_operand:V8QI 0 "register_operand" "=y") 951 [(set (match_operand:V8QI 0 "register_operand" "=y")
685 (vec_concat:V8QI 952 (vec_concat:V8QI
686 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) 953 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
687 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] 954 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
688 "TARGET_REALLY_IWMMXT" 955 "TARGET_REALLY_IWMMXT"
689 "wpackhss%?\\t%0, %1, %2" 956 "wpackhss%?\\t%0, %1, %2"
690 [(set_attr "predicable" "yes")]) 957 [(set_attr "predicable" "yes")
958 (set_attr "type" "wmmx_wpack")]
959 )
691 960
692 (define_insn "iwmmxt_wpackwss" 961 (define_insn "iwmmxt_wpackwss"
693 [(set (match_operand:V4HI 0 "register_operand" "=y") 962 [(set (match_operand:V4HI 0 "register_operand" "=y")
963 (vec_concat:V4HI
964 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
965 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
966 "TARGET_REALLY_IWMMXT"
967 "wpackwss%?\\t%0, %1, %2"
968 [(set_attr "predicable" "yes")
969 (set_attr "type" "wmmx_wpack")]
970 )
971
972 (define_insn "iwmmxt_wpackdss"
973 [(set (match_operand:V2SI 0 "register_operand" "=y")
974 (vec_concat:V2SI
975 (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
976 (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
977 "TARGET_REALLY_IWMMXT"
978 "wpackdss%?\\t%0, %1, %2"
979 [(set_attr "predicable" "yes")
980 (set_attr "type" "wmmx_wpack")]
981 )
982
983 (define_insn "iwmmxt_wpackhus"
984 [(set (match_operand:V8QI 0 "register_operand" "=y")
985 (vec_concat:V8QI
986 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
987 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
988 "TARGET_REALLY_IWMMXT"
989 "wpackhus%?\\t%0, %1, %2"
990 [(set_attr "predicable" "yes")
991 (set_attr "type" "wmmx_wpack")]
992 )
993
994 (define_insn "iwmmxt_wpackwus"
995 [(set (match_operand:V4HI 0 "register_operand" "=y")
694 (vec_concat:V4HI 996 (vec_concat:V4HI
695 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) 997 (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
696 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] 998 (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
697 "TARGET_REALLY_IWMMXT" 999 "TARGET_REALLY_IWMMXT"
698 "wpackwss%?\\t%0, %1, %2" 1000 "wpackwus%?\\t%0, %1, %2"
699 [(set_attr "predicable" "yes")]) 1001 [(set_attr "predicable" "yes")
700 1002 (set_attr "type" "wmmx_wpack")]
701 (define_insn "iwmmxt_wpackdss" 1003 )
702 [(set (match_operand:V2SI 0 "register_operand" "=y") 1004
1005 (define_insn "iwmmxt_wpackdus"
1006 [(set (match_operand:V2SI 0 "register_operand" "=y")
703 (vec_concat:V2SI 1007 (vec_concat:V2SI
704 (ss_truncate:SI (match_operand:DI 1 "register_operand" "y")) 1008 (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
705 (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] 1009 (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
706 "TARGET_REALLY_IWMMXT"
707 "wpackdss%?\\t%0, %1, %2"
708 [(set_attr "predicable" "yes")])
709
710 (define_insn "iwmmxt_wpackhus"
711 [(set (match_operand:V8QI 0 "register_operand" "=y")
712 (vec_concat:V8QI
713 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
714 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
715 "TARGET_REALLY_IWMMXT"
716 "wpackhus%?\\t%0, %1, %2"
717 [(set_attr "predicable" "yes")])
718
719 (define_insn "iwmmxt_wpackwus"
720 [(set (match_operand:V4HI 0 "register_operand" "=y")
721 (vec_concat:V4HI
722 (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
723 (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
724 "TARGET_REALLY_IWMMXT"
725 "wpackwus%?\\t%0, %1, %2"
726 [(set_attr "predicable" "yes")])
727
728 (define_insn "iwmmxt_wpackdus"
729 [(set (match_operand:V2SI 0 "register_operand" "=y")
730 (vec_concat:V2SI
731 (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
732 (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
733 "TARGET_REALLY_IWMMXT" 1010 "TARGET_REALLY_IWMMXT"
734 "wpackdus%?\\t%0, %1, %2" 1011 "wpackdus%?\\t%0, %1, %2"
735 [(set_attr "predicable" "yes")]) 1012 [(set_attr "predicable" "yes")
736 1013 (set_attr "type" "wmmx_wpack")]
1014 )
737 1015
738 (define_insn "iwmmxt_wunpckihb" 1016 (define_insn "iwmmxt_wunpckihb"
739 [(set (match_operand:V8QI 0 "register_operand" "=y") 1017 [(set (match_operand:V8QI 0 "register_operand" "=y")
740 (vec_merge:V8QI 1018 (vec_merge:V8QI
741 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") 1019 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
742 (parallel [(const_int 4) 1020 (parallel [(const_int 4)
743 (const_int 0) 1021 (const_int 0)
744 (const_int 5) 1022 (const_int 5)
745 (const_int 1) 1023 (const_int 1)
746 (const_int 6) 1024 (const_int 6)
747 (const_int 2) 1025 (const_int 2)
748 (const_int 7) 1026 (const_int 7)
749 (const_int 3)])) 1027 (const_int 3)]))
750 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") 1028 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
751 (parallel [(const_int 0) 1029 (parallel [(const_int 0)
752 (const_int 4) 1030 (const_int 4)
753 (const_int 1) 1031 (const_int 1)
754 (const_int 5) 1032 (const_int 5)
755 (const_int 2) 1033 (const_int 2)
756 (const_int 6) 1034 (const_int 6)
757 (const_int 3) 1035 (const_int 3)
758 (const_int 7)])) 1036 (const_int 7)]))
759 (const_int 85)))] 1037 (const_int 85)))]
760 "TARGET_REALLY_IWMMXT" 1038 "TARGET_REALLY_IWMMXT"
761 "wunpckihb%?\\t%0, %1, %2" 1039 "wunpckihb%?\\t%0, %1, %2"
762 [(set_attr "predicable" "yes")]) 1040 [(set_attr "predicable" "yes")
1041 (set_attr "type" "wmmx_wunpckih")]
1042 )
763 1043
764 (define_insn "iwmmxt_wunpckihh" 1044 (define_insn "iwmmxt_wunpckihh"
765 [(set (match_operand:V4HI 0 "register_operand" "=y") 1045 [(set (match_operand:V4HI 0 "register_operand" "=y")
766 (vec_merge:V4HI 1046 (vec_merge:V4HI
767 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") 1047 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
768 (parallel [(const_int 0) 1048 (parallel [(const_int 2)
769 (const_int 2) 1049 (const_int 0)
770 (const_int 1) 1050 (const_int 3)
771 (const_int 3)])) 1051 (const_int 1)]))
772 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") 1052 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
773 (parallel [(const_int 2) 1053 (parallel [(const_int 0)
774 (const_int 0) 1054 (const_int 2)
775 (const_int 3) 1055 (const_int 1)
776 (const_int 1)])) 1056 (const_int 3)]))
777 (const_int 5)))] 1057 (const_int 5)))]
778 "TARGET_REALLY_IWMMXT" 1058 "TARGET_REALLY_IWMMXT"
779 "wunpckihh%?\\t%0, %1, %2" 1059 "wunpckihh%?\\t%0, %1, %2"
780 [(set_attr "predicable" "yes")]) 1060 [(set_attr "predicable" "yes")
1061 (set_attr "type" "wmmx_wunpckih")]
1062 )
781 1063
782 (define_insn "iwmmxt_wunpckihw" 1064 (define_insn "iwmmxt_wunpckihw"
783 [(set (match_operand:V2SI 0 "register_operand" "=y") 1065 [(set (match_operand:V2SI 0 "register_operand" "=y")
784 (vec_merge:V2SI 1066 (vec_merge:V2SI
785 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") 1067 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
786 (parallel [(const_int 0) 1068 (parallel [(const_int 1)
787 (const_int 1)])) 1069 (const_int 0)]))
788 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") 1070 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
789 (parallel [(const_int 1) 1071 (parallel [(const_int 0)
790 (const_int 0)])) 1072 (const_int 1)]))
791 (const_int 1)))] 1073 (const_int 1)))]
792 "TARGET_REALLY_IWMMXT" 1074 "TARGET_REALLY_IWMMXT"
793 "wunpckihw%?\\t%0, %1, %2" 1075 "wunpckihw%?\\t%0, %1, %2"
794 [(set_attr "predicable" "yes")]) 1076 [(set_attr "predicable" "yes")
1077 (set_attr "type" "wmmx_wunpckih")]
1078 )
795 1079
796 (define_insn "iwmmxt_wunpckilb" 1080 (define_insn "iwmmxt_wunpckilb"
797 [(set (match_operand:V8QI 0 "register_operand" "=y") 1081 [(set (match_operand:V8QI 0 "register_operand" "=y")
798 (vec_merge:V8QI 1082 (vec_merge:V8QI
799 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") 1083 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
800 (parallel [(const_int 0) 1084 (parallel [(const_int 0)
801 (const_int 4) 1085 (const_int 4)
802 (const_int 1) 1086 (const_int 1)
803 (const_int 5) 1087 (const_int 5)
804 (const_int 2) 1088 (const_int 2)
805 (const_int 6) 1089 (const_int 6)
806 (const_int 3) 1090 (const_int 3)
807 (const_int 7)])) 1091 (const_int 7)]))
808 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") 1092 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
809 (parallel [(const_int 4) 1093 (parallel [(const_int 4)
810 (const_int 0) 1094 (const_int 0)
811 (const_int 5) 1095 (const_int 5)
812 (const_int 1) 1096 (const_int 1)
813 (const_int 6) 1097 (const_int 6)
814 (const_int 2) 1098 (const_int 2)
815 (const_int 7) 1099 (const_int 7)
816 (const_int 3)])) 1100 (const_int 3)]))
817 (const_int 85)))] 1101 (const_int 85)))]
818 "TARGET_REALLY_IWMMXT" 1102 "TARGET_REALLY_IWMMXT"
819 "wunpckilb%?\\t%0, %1, %2" 1103 "wunpckilb%?\\t%0, %1, %2"
820 [(set_attr "predicable" "yes")]) 1104 [(set_attr "predicable" "yes")
1105 (set_attr "type" "wmmx_wunpckil")]
1106 )
821 1107
822 (define_insn "iwmmxt_wunpckilh" 1108 (define_insn "iwmmxt_wunpckilh"
823 [(set (match_operand:V4HI 0 "register_operand" "=y") 1109 [(set (match_operand:V4HI 0 "register_operand" "=y")
824 (vec_merge:V4HI 1110 (vec_merge:V4HI
825 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") 1111 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
826 (parallel [(const_int 2) 1112 (parallel [(const_int 0)
827 (const_int 0) 1113 (const_int 2)
828 (const_int 3) 1114 (const_int 1)
829 (const_int 1)])) 1115 (const_int 3)]))
830 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") 1116 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
831 (parallel [(const_int 0) 1117 (parallel [(const_int 2)
832 (const_int 2) 1118 (const_int 0)
833 (const_int 1) 1119 (const_int 3)
834 (const_int 3)])) 1120 (const_int 1)]))
835 (const_int 5)))] 1121 (const_int 5)))]
836 "TARGET_REALLY_IWMMXT" 1122 "TARGET_REALLY_IWMMXT"
837 "wunpckilh%?\\t%0, %1, %2" 1123 "wunpckilh%?\\t%0, %1, %2"
838 [(set_attr "predicable" "yes")]) 1124 [(set_attr "predicable" "yes")
1125 (set_attr "type" "wmmx_wunpckil")]
1126 )
839 1127
840 (define_insn "iwmmxt_wunpckilw" 1128 (define_insn "iwmmxt_wunpckilw"
841 [(set (match_operand:V2SI 0 "register_operand" "=y") 1129 [(set (match_operand:V2SI 0 "register_operand" "=y")
842 (vec_merge:V2SI 1130 (vec_merge:V2SI
843 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") 1131 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
844 (parallel [(const_int 1) 1132 (parallel [(const_int 0)
845 (const_int 0)])) 1133 (const_int 1)]))
846 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") 1134 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
847 (parallel [(const_int 0) 1135 (parallel [(const_int 1)
848 (const_int 1)])) 1136 (const_int 0)]))
849 (const_int 1)))] 1137 (const_int 1)))]
850 "TARGET_REALLY_IWMMXT" 1138 "TARGET_REALLY_IWMMXT"
851 "wunpckilw%?\\t%0, %1, %2" 1139 "wunpckilw%?\\t%0, %1, %2"
852 [(set_attr "predicable" "yes")]) 1140 [(set_attr "predicable" "yes")
1141 (set_attr "type" "wmmx_wunpckil")]
1142 )
853 1143
854 (define_insn "iwmmxt_wunpckehub" 1144 (define_insn "iwmmxt_wunpckehub"
855 [(set (match_operand:V4HI 0 "register_operand" "=y") 1145 [(set (match_operand:V4HI 0 "register_operand" "=y")
856 (zero_extend:V4HI 1146 (vec_select:V4HI
857 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") 1147 (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
858 (parallel [(const_int 4) (const_int 5) 1148 (parallel [(const_int 4) (const_int 5)
859 (const_int 6) (const_int 7)]))))] 1149 (const_int 6) (const_int 7)])))]
860 "TARGET_REALLY_IWMMXT" 1150 "TARGET_REALLY_IWMMXT"
861 "wunpckehub%?\\t%0, %1" 1151 "wunpckehub%?\\t%0, %1"
862 [(set_attr "predicable" "yes")]) 1152 [(set_attr "predicable" "yes")
1153 (set_attr "type" "wmmx_wunpckeh")]
1154 )
863 1155
864 (define_insn "iwmmxt_wunpckehuh" 1156 (define_insn "iwmmxt_wunpckehuh"
865 [(set (match_operand:V2SI 0 "register_operand" "=y") 1157 [(set (match_operand:V2SI 0 "register_operand" "=y")
866 (zero_extend:V2SI 1158 (vec_select:V2SI
867 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") 1159 (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
868 (parallel [(const_int 2) (const_int 3)]))))] 1160 (parallel [(const_int 2) (const_int 3)])))]
869 "TARGET_REALLY_IWMMXT" 1161 "TARGET_REALLY_IWMMXT"
870 "wunpckehuh%?\\t%0, %1" 1162 "wunpckehuh%?\\t%0, %1"
871 [(set_attr "predicable" "yes")]) 1163 [(set_attr "predicable" "yes")
1164 (set_attr "type" "wmmx_wunpckeh")]
1165 )
872 1166
873 (define_insn "iwmmxt_wunpckehuw" 1167 (define_insn "iwmmxt_wunpckehuw"
874 [(set (match_operand:DI 0 "register_operand" "=y") 1168 [(set (match_operand:DI 0 "register_operand" "=y")
875 (zero_extend:DI 1169 (vec_select:DI
876 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 1170 (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
877 (parallel [(const_int 1)]))))] 1171 (parallel [(const_int 1)])))]
878 "TARGET_REALLY_IWMMXT" 1172 "TARGET_REALLY_IWMMXT"
879 "wunpckehuw%?\\t%0, %1" 1173 "wunpckehuw%?\\t%0, %1"
880 [(set_attr "predicable" "yes")]) 1174 [(set_attr "predicable" "yes")
1175 (set_attr "type" "wmmx_wunpckeh")]
1176 )
881 1177
882 (define_insn "iwmmxt_wunpckehsb" 1178 (define_insn "iwmmxt_wunpckehsb"
883 [(set (match_operand:V4HI 0 "register_operand" "=y") 1179 [(set (match_operand:V4HI 0 "register_operand" "=y")
884 (sign_extend:V4HI 1180 (vec_select:V4HI
885 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") 1181 (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
886 (parallel [(const_int 4) (const_int 5) 1182 (parallel [(const_int 4) (const_int 5)
887 (const_int 6) (const_int 7)]))))] 1183 (const_int 6) (const_int 7)])))]
888 "TARGET_REALLY_IWMMXT" 1184 "TARGET_REALLY_IWMMXT"
889 "wunpckehsb%?\\t%0, %1" 1185 "wunpckehsb%?\\t%0, %1"
890 [(set_attr "predicable" "yes")]) 1186 [(set_attr "predicable" "yes")
1187 (set_attr "type" "wmmx_wunpckeh")]
1188 )
891 1189
892 (define_insn "iwmmxt_wunpckehsh" 1190 (define_insn "iwmmxt_wunpckehsh"
893 [(set (match_operand:V2SI 0 "register_operand" "=y") 1191 [(set (match_operand:V2SI 0 "register_operand" "=y")
894 (sign_extend:V2SI 1192 (vec_select:V2SI
895 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") 1193 (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
896 (parallel [(const_int 2) (const_int 3)]))))] 1194 (parallel [(const_int 2) (const_int 3)])))]
897 "TARGET_REALLY_IWMMXT" 1195 "TARGET_REALLY_IWMMXT"
898 "wunpckehsh%?\\t%0, %1" 1196 "wunpckehsh%?\\t%0, %1"
899 [(set_attr "predicable" "yes")]) 1197 [(set_attr "predicable" "yes")
1198 (set_attr "type" "wmmx_wunpckeh")]
1199 )
900 1200
901 (define_insn "iwmmxt_wunpckehsw" 1201 (define_insn "iwmmxt_wunpckehsw"
902 [(set (match_operand:DI 0 "register_operand" "=y") 1202 [(set (match_operand:DI 0 "register_operand" "=y")
903 (sign_extend:DI 1203 (vec_select:DI
904 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 1204 (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
905 (parallel [(const_int 1)]))))] 1205 (parallel [(const_int 1)])))]
906 "TARGET_REALLY_IWMMXT" 1206 "TARGET_REALLY_IWMMXT"
907 "wunpckehsw%?\\t%0, %1" 1207 "wunpckehsw%?\\t%0, %1"
908 [(set_attr "predicable" "yes")]) 1208 [(set_attr "predicable" "yes")
1209 (set_attr "type" "wmmx_wunpckeh")]
1210 )
909 1211
910 (define_insn "iwmmxt_wunpckelub" 1212 (define_insn "iwmmxt_wunpckelub"
911 [(set (match_operand:V4HI 0 "register_operand" "=y") 1213 [(set (match_operand:V4HI 0 "register_operand" "=y")
912 (zero_extend:V4HI 1214 (vec_select:V4HI
913 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") 1215 (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
914 (parallel [(const_int 0) (const_int 1) 1216 (parallel [(const_int 0) (const_int 1)
915 (const_int 2) (const_int 3)]))))] 1217 (const_int 2) (const_int 3)])))]
916 "TARGET_REALLY_IWMMXT" 1218 "TARGET_REALLY_IWMMXT"
917 "wunpckelub%?\\t%0, %1" 1219 "wunpckelub%?\\t%0, %1"
918 [(set_attr "predicable" "yes")]) 1220 [(set_attr "predicable" "yes")
1221 (set_attr "type" "wmmx_wunpckel")]
1222 )
919 1223
920 (define_insn "iwmmxt_wunpckeluh" 1224 (define_insn "iwmmxt_wunpckeluh"
921 [(set (match_operand:V2SI 0 "register_operand" "=y") 1225 [(set (match_operand:V2SI 0 "register_operand" "=y")
922 (zero_extend:V2SI 1226 (vec_select:V2SI
923 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") 1227 (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
924 (parallel [(const_int 0) (const_int 1)]))))] 1228 (parallel [(const_int 0) (const_int 1)])))]
925 "TARGET_REALLY_IWMMXT" 1229 "TARGET_REALLY_IWMMXT"
926 "wunpckeluh%?\\t%0, %1" 1230 "wunpckeluh%?\\t%0, %1"
927 [(set_attr "predicable" "yes")]) 1231 [(set_attr "predicable" "yes")
1232 (set_attr "type" "wmmx_wunpckel")]
1233 )
928 1234
929 (define_insn "iwmmxt_wunpckeluw" 1235 (define_insn "iwmmxt_wunpckeluw"
930 [(set (match_operand:DI 0 "register_operand" "=y") 1236 [(set (match_operand:DI 0 "register_operand" "=y")
931 (zero_extend:DI 1237 (vec_select:DI
932 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 1238 (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
933 (parallel [(const_int 0)]))))] 1239 (parallel [(const_int 0)])))]
934 "TARGET_REALLY_IWMMXT" 1240 "TARGET_REALLY_IWMMXT"
935 "wunpckeluw%?\\t%0, %1" 1241 "wunpckeluw%?\\t%0, %1"
936 [(set_attr "predicable" "yes")]) 1242 [(set_attr "predicable" "yes")
1243 (set_attr "type" "wmmx_wunpckel")]
1244 )
937 1245
938 (define_insn "iwmmxt_wunpckelsb" 1246 (define_insn "iwmmxt_wunpckelsb"
939 [(set (match_operand:V4HI 0 "register_operand" "=y") 1247 [(set (match_operand:V4HI 0 "register_operand" "=y")
940 (sign_extend:V4HI 1248 (vec_select:V4HI
941 (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") 1249 (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
942 (parallel [(const_int 0) (const_int 1) 1250 (parallel [(const_int 0) (const_int 1)
943 (const_int 2) (const_int 3)]))))] 1251 (const_int 2) (const_int 3)])))]
944 "TARGET_REALLY_IWMMXT" 1252 "TARGET_REALLY_IWMMXT"
945 "wunpckelsb%?\\t%0, %1" 1253 "wunpckelsb%?\\t%0, %1"
946 [(set_attr "predicable" "yes")]) 1254 [(set_attr "predicable" "yes")
1255 (set_attr "type" "wmmx_wunpckel")]
1256 )
947 1257
948 (define_insn "iwmmxt_wunpckelsh" 1258 (define_insn "iwmmxt_wunpckelsh"
949 [(set (match_operand:V2SI 0 "register_operand" "=y") 1259 [(set (match_operand:V2SI 0 "register_operand" "=y")
950 (sign_extend:V2SI 1260 (vec_select:V2SI
951 (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") 1261 (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
952 (parallel [(const_int 0) (const_int 1)]))))] 1262 (parallel [(const_int 0) (const_int 1)])))]
953 "TARGET_REALLY_IWMMXT" 1263 "TARGET_REALLY_IWMMXT"
954 "wunpckelsh%?\\t%0, %1" 1264 "wunpckelsh%?\\t%0, %1"
955 [(set_attr "predicable" "yes")]) 1265 [(set_attr "predicable" "yes")
1266 (set_attr "type" "wmmx_wunpckel")]
1267 )
956 1268
957 (define_insn "iwmmxt_wunpckelsw" 1269 (define_insn "iwmmxt_wunpckelsw"
958 [(set (match_operand:DI 0 "register_operand" "=y") 1270 [(set (match_operand:DI 0 "register_operand" "=y")
959 (sign_extend:DI 1271 (vec_select:DI
960 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") 1272 (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
961 (parallel [(const_int 0)]))))] 1273 (parallel [(const_int 0)])))]
962 "TARGET_REALLY_IWMMXT" 1274 "TARGET_REALLY_IWMMXT"
963 "wunpckelsw%?\\t%0, %1" 1275 "wunpckelsw%?\\t%0, %1"
964 [(set_attr "predicable" "yes")]) 1276 [(set_attr "predicable" "yes")
1277 (set_attr "type" "wmmx_wunpckel")]
1278 )
965 1279
966 ;; Shifts 1280 ;; Shifts
967 1281
968 (define_insn "rorv4hi3" 1282 (define_insn "ror<mode>3"
969 [(set (match_operand:V4HI 0 "register_operand" "=y") 1283 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
970 (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y") 1284 (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
971 (match_operand:SI 2 "register_operand" "z")))] 1285 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
972 "TARGET_REALLY_IWMMXT" 1286 "TARGET_REALLY_IWMMXT"
973 "wrorhg%?\\t%0, %1, %2" 1287 "*
974 [(set_attr "predicable" "yes")]) 1288 switch (which_alternative)
975 1289 {
976 (define_insn "rorv2si3" 1290 case 0:
977 [(set (match_operand:V2SI 0 "register_operand" "=y") 1291 return \"wror<MMX_char>g%?\\t%0, %1, %2\";
978 (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y") 1292 case 1:
979 (match_operand:SI 2 "register_operand" "z")))] 1293 return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true);
980 "TARGET_REALLY_IWMMXT" 1294 default:
981 "wrorwg%?\\t%0, %1, %2" 1295 gcc_unreachable ();
982 [(set_attr "predicable" "yes")]) 1296 }
983 1297 "
984 (define_insn "rordi3" 1298 [(set_attr "predicable" "yes")
985 [(set (match_operand:DI 0 "register_operand" "=y") 1299 (set_attr "arch" "*, iwmmxt2")
986 (rotatert:DI (match_operand:DI 1 "register_operand" "y") 1300 (set_attr "type" "wmmx_wror, wmmx_wror")]
987 (match_operand:SI 2 "register_operand" "z")))] 1301 )
988 "TARGET_REALLY_IWMMXT"
989 "wrordg%?\\t%0, %1, %2"
990 [(set_attr "predicable" "yes")])
991 1302
992 (define_insn "ashr<mode>3_iwmmxt" 1303 (define_insn "ashr<mode>3_iwmmxt"
993 [(set (match_operand:VSHFT 0 "register_operand" "=y") 1304 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
994 (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y") 1305 (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
995 (match_operand:SI 2 "register_operand" "z")))] 1306 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
996 "TARGET_REALLY_IWMMXT" 1307 "TARGET_REALLY_IWMMXT"
997 "wsra<MMX_char>g%?\\t%0, %1, %2" 1308 "*
998 [(set_attr "predicable" "yes")]) 1309 switch (which_alternative)
1310 {
1311 case 0:
1312 return \"wsra<MMX_char>g%?\\t%0, %1, %2\";
1313 case 1:
1314 return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true);
1315 default:
1316 gcc_unreachable ();
1317 }
1318 "
1319 [(set_attr "predicable" "yes")
1320 (set_attr "arch" "*, iwmmxt2")
1321 (set_attr "type" "wmmx_wsra, wmmx_wsra")]
1322 )
999 1323
1000 (define_insn "lshr<mode>3_iwmmxt" 1324 (define_insn "lshr<mode>3_iwmmxt"
1001 [(set (match_operand:VSHFT 0 "register_operand" "=y") 1325 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1002 (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y") 1326 (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1003 (match_operand:SI 2 "register_operand" "z")))] 1327 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
1004 "TARGET_REALLY_IWMMXT" 1328 "TARGET_REALLY_IWMMXT"
1005 "wsrl<MMX_char>g%?\\t%0, %1, %2" 1329 "*
1006 [(set_attr "predicable" "yes")]) 1330 switch (which_alternative)
1331 {
1332 case 0:
1333 return \"wsrl<MMX_char>g%?\\t%0, %1, %2\";
1334 case 1:
1335 return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false);
1336 default:
1337 gcc_unreachable ();
1338 }
1339 "
1340 [(set_attr "predicable" "yes")
1341 (set_attr "arch" "*, iwmmxt2")
1342 (set_attr "type" "wmmx_wsrl, wmmx_wsrl")]
1343 )
1007 1344
1008 (define_insn "ashl<mode>3_iwmmxt" 1345 (define_insn "ashl<mode>3_iwmmxt"
1009 [(set (match_operand:VSHFT 0 "register_operand" "=y") 1346 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1010 (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y") 1347 (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1011 (match_operand:SI 2 "register_operand" "z")))] 1348 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
1012 "TARGET_REALLY_IWMMXT" 1349 "TARGET_REALLY_IWMMXT"
1013 "wsll<MMX_char>g%?\\t%0, %1, %2" 1350 "*
1014 [(set_attr "predicable" "yes")]) 1351 switch (which_alternative)
1015 1352 {
1016 (define_insn "rorv4hi3_di" 1353 case 0:
1017 [(set (match_operand:V4HI 0 "register_operand" "=y") 1354 return \"wsll<MMX_char>g%?\\t%0, %1, %2\";
1018 (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y") 1355 case 1:
1019 (match_operand:DI 2 "register_operand" "y")))] 1356 return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false);
1020 "TARGET_REALLY_IWMMXT" 1357 default:
1021 "wrorh%?\\t%0, %1, %2" 1358 gcc_unreachable ();
1022 [(set_attr "predicable" "yes")]) 1359 }
1023 1360 "
1024 (define_insn "rorv2si3_di" 1361 [(set_attr "predicable" "yes")
1025 [(set (match_operand:V2SI 0 "register_operand" "=y") 1362 (set_attr "arch" "*, iwmmxt2")
1026 (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y") 1363 (set_attr "type" "wmmx_wsll, wmmx_wsll")]
1027 (match_operand:DI 2 "register_operand" "y")))] 1364 )
1028 "TARGET_REALLY_IWMMXT" 1365
1029 "wrorw%?\\t%0, %1, %2" 1366 (define_insn "ror<mode>3_di"
1030 [(set_attr "predicable" "yes")]) 1367 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1031 1368 (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1032 (define_insn "rordi3_di" 1369 (match_operand:DI 2 "imm_or_reg_operand" "y,i")))]
1033 [(set (match_operand:DI 0 "register_operand" "=y") 1370 "TARGET_REALLY_IWMMXT"
1034 (rotatert:DI (match_operand:DI 1 "register_operand" "y") 1371 "*
1035 (match_operand:DI 2 "register_operand" "y")))] 1372 switch (which_alternative)
1036 "TARGET_REALLY_IWMMXT" 1373 {
1037 "wrord%?\\t%0, %1, %2" 1374 case 0:
1038 [(set_attr "predicable" "yes")]) 1375 return \"wror<MMX_char>%?\\t%0, %1, %2\";
1039 1376 case 1:
1040 (define_insn "ashrv4hi3_di" 1377 return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true);
1041 [(set (match_operand:V4HI 0 "register_operand" "=y") 1378 default:
1042 (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") 1379 gcc_unreachable ();
1043 (match_operand:DI 2 "register_operand" "y")))] 1380 }
1044 "TARGET_REALLY_IWMMXT" 1381 "
1045 "wsrah%?\\t%0, %1, %2" 1382 [(set_attr "predicable" "yes")
1046 [(set_attr "predicable" "yes")]) 1383 (set_attr "arch" "*, iwmmxt2")
1047 1384 (set_attr "type" "wmmx_wror, wmmx_wror")]
1048 (define_insn "ashrv2si3_di" 1385 )
1049 [(set (match_operand:V2SI 0 "register_operand" "=y") 1386
1050 (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") 1387 (define_insn "ashr<mode>3_di"
1051 (match_operand:DI 2 "register_operand" "y")))] 1388 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1052 "TARGET_REALLY_IWMMXT" 1389 (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1053 "wsraw%?\\t%0, %1, %2" 1390 (match_operand:DI 2 "imm_or_reg_operand" "y,i")))]
1054 [(set_attr "predicable" "yes")]) 1391 "TARGET_REALLY_IWMMXT"
1055 1392 "*
1056 (define_insn "ashrdi3_di" 1393 switch (which_alternative)
1057 [(set (match_operand:DI 0 "register_operand" "=y") 1394 {
1058 (ashiftrt:DI (match_operand:DI 1 "register_operand" "y") 1395 case 0:
1059 (match_operand:DI 2 "register_operand" "y")))] 1396 return \"wsra<MMX_char>%?\\t%0, %1, %2\";
1060 "TARGET_REALLY_IWMMXT" 1397 case 1:
1061 "wsrad%?\\t%0, %1, %2" 1398 return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true);
1062 [(set_attr "predicable" "yes")]) 1399 default:
1063 1400 gcc_unreachable ();
1064 (define_insn "lshrv4hi3_di" 1401 }
1065 [(set (match_operand:V4HI 0 "register_operand" "=y") 1402 "
1066 (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") 1403 [(set_attr "predicable" "yes")
1067 (match_operand:DI 2 "register_operand" "y")))] 1404 (set_attr "arch" "*, iwmmxt2")
1068 "TARGET_REALLY_IWMMXT" 1405 (set_attr "type" "wmmx_wsra, wmmx_wsra")]
1069 "wsrlh%?\\t%0, %1, %2" 1406 )
1070 [(set_attr "predicable" "yes")]) 1407
1071 1408 (define_insn "lshr<mode>3_di"
1072 (define_insn "lshrv2si3_di" 1409 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1073 [(set (match_operand:V2SI 0 "register_operand" "=y") 1410 (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1074 (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") 1411 (match_operand:DI 2 "register_operand" "y,i")))]
1075 (match_operand:DI 2 "register_operand" "y")))] 1412 "TARGET_REALLY_IWMMXT"
1076 "TARGET_REALLY_IWMMXT" 1413 "*
1077 "wsrlw%?\\t%0, %1, %2" 1414 switch (which_alternative)
1078 [(set_attr "predicable" "yes")]) 1415 {
1079 1416 case 0:
1080 (define_insn "lshrdi3_di" 1417 return \"wsrl<MMX_char>%?\\t%0, %1, %2\";
1081 [(set (match_operand:DI 0 "register_operand" "=y") 1418 case 1:
1082 (lshiftrt:DI (match_operand:DI 1 "register_operand" "y") 1419 return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false);
1083 (match_operand:DI 2 "register_operand" "y")))] 1420 default:
1084 "TARGET_REALLY_IWMMXT" 1421 gcc_unreachable ();
1085 "wsrld%?\\t%0, %1, %2" 1422 }
1086 [(set_attr "predicable" "yes")]) 1423 "
1087 1424 [(set_attr "predicable" "yes")
1088 (define_insn "ashlv4hi3_di" 1425 (set_attr "arch" "*, iwmmxt2")
1089 [(set (match_operand:V4HI 0 "register_operand" "=y") 1426 (set_attr "type" "wmmx_wsrl, wmmx_wsrl")]
1090 (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y") 1427 )
1091 (match_operand:DI 2 "register_operand" "y")))] 1428
1092 "TARGET_REALLY_IWMMXT" 1429 (define_insn "ashl<mode>3_di"
1093 "wsllh%?\\t%0, %1, %2" 1430 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1094 [(set_attr "predicable" "yes")]) 1431 (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1095 1432 (match_operand:DI 2 "imm_or_reg_operand" "y,i")))]
1096 (define_insn "ashlv2si3_di" 1433 "TARGET_REALLY_IWMMXT"
1097 [(set (match_operand:V2SI 0 "register_operand" "=y") 1434 "*
1098 (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y") 1435 switch (which_alternative)
1099 (match_operand:DI 2 "register_operand" "y")))] 1436 {
1100 "TARGET_REALLY_IWMMXT" 1437 case 0:
1101 "wsllw%?\\t%0, %1, %2" 1438 return \"wsll<MMX_char>%?\\t%0, %1, %2\";
1102 [(set_attr "predicable" "yes")]) 1439 case 1:
1103 1440 return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false);
1104 (define_insn "ashldi3_di" 1441 default:
1105 [(set (match_operand:DI 0 "register_operand" "=y") 1442 gcc_unreachable ();
1106 (ashift:DI (match_operand:DI 1 "register_operand" "y") 1443 }
1107 (match_operand:DI 2 "register_operand" "y")))] 1444 "
1108 "TARGET_REALLY_IWMMXT" 1445 [(set_attr "predicable" "yes")
1109 "wslld%?\\t%0, %1, %2" 1446 (set_attr "arch" "*, iwmmxt2")
1110 [(set_attr "predicable" "yes")]) 1447 (set_attr "type" "wmmx_wsll, wmmx_wsll")]
1448 )
1111 1449
1112 (define_insn "iwmmxt_wmadds" 1450 (define_insn "iwmmxt_wmadds"
1113 [(set (match_operand:V4HI 0 "register_operand" "=y") 1451 [(set (match_operand:V2SI 0 "register_operand" "=y")
1114 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 1452 (plus:V2SI
1115 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))] 1453 (mult:V2SI
1454 (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1455 (parallel [(const_int 1) (const_int 3)]))
1456 (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
1457 (parallel [(const_int 1) (const_int 3)])))
1458 (mult:V2SI
1459 (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
1460 (parallel [(const_int 0) (const_int 2)]))
1461 (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
1462 (parallel [(const_int 0) (const_int 2)])))))]
1116 "TARGET_REALLY_IWMMXT" 1463 "TARGET_REALLY_IWMMXT"
1117 "wmadds%?\\t%0, %1, %2" 1464 "wmadds%?\\t%0, %1, %2"
1118 [(set_attr "predicable" "yes")]) 1465 [(set_attr "predicable" "yes")
1466 (set_attr "type" "wmmx_wmadd")]
1467 )
1119 1468
1120 (define_insn "iwmmxt_wmaddu" 1469 (define_insn "iwmmxt_wmaddu"
1121 [(set (match_operand:V4HI 0 "register_operand" "=y") 1470 [(set (match_operand:V2SI 0 "register_operand" "=y")
1122 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 1471 (plus:V2SI
1123 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))] 1472 (mult:V2SI
1473 (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1474 (parallel [(const_int 1) (const_int 3)]))
1475 (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
1476 (parallel [(const_int 1) (const_int 3)])))
1477 (mult:V2SI
1478 (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
1479 (parallel [(const_int 0) (const_int 2)]))
1480 (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
1481 (parallel [(const_int 0) (const_int 2)])))))]
1124 "TARGET_REALLY_IWMMXT" 1482 "TARGET_REALLY_IWMMXT"
1125 "wmaddu%?\\t%0, %1, %2" 1483 "wmaddu%?\\t%0, %1, %2"
1126 [(set_attr "predicable" "yes")]) 1484 [(set_attr "predicable" "yes")
1485 (set_attr "type" "wmmx_wmadd")]
1486 )
1127 1487
1128 (define_insn "iwmmxt_tmia" 1488 (define_insn "iwmmxt_tmia"
1129 [(set (match_operand:DI 0 "register_operand" "=y") 1489 [(set (match_operand:DI 0 "register_operand" "=y")
1130 (plus:DI (match_operand:DI 1 "register_operand" "0") 1490 (plus:DI (match_operand:DI 1 "register_operand" "0")
1131 (mult:DI (sign_extend:DI 1491 (mult:DI (sign_extend:DI
1132 (match_operand:SI 2 "register_operand" "r")) 1492 (match_operand:SI 2 "register_operand" "r"))
1133 (sign_extend:DI 1493 (sign_extend:DI
1134 (match_operand:SI 3 "register_operand" "r")))))] 1494 (match_operand:SI 3 "register_operand" "r")))))]
1135 "TARGET_REALLY_IWMMXT" 1495 "TARGET_REALLY_IWMMXT"
1136 "tmia%?\\t%0, %2, %3" 1496 "tmia%?\\t%0, %2, %3"
1137 [(set_attr "predicable" "yes")]) 1497 [(set_attr "predicable" "yes")
1498 (set_attr "type" "wmmx_tmia")]
1499 )
1138 1500
1139 (define_insn "iwmmxt_tmiaph" 1501 (define_insn "iwmmxt_tmiaph"
1140 [(set (match_operand:DI 0 "register_operand" "=y") 1502 [(set (match_operand:DI 0 "register_operand" "=y")
1141 (plus:DI (match_operand:DI 1 "register_operand" "0") 1503 (plus:DI (match_operand:DI 1 "register_operand" "0")
1142 (plus:DI 1504 (plus:DI
1143 (mult:DI (sign_extend:DI 1505 (mult:DI (sign_extend:DI
1506 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1507 (sign_extend:DI
1508 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1509 (mult:DI (sign_extend:DI
1510 (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1511 (sign_extend:DI
1512 (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1513 "TARGET_REALLY_IWMMXT"
1514 "tmiaph%?\\t%0, %2, %3"
1515 [(set_attr "predicable" "yes")
1516 (set_attr "type" "wmmx_tmiaph")]
1517 )
1518
1519 (define_insn "iwmmxt_tmiabb"
1520 [(set (match_operand:DI 0 "register_operand" "=y")
1521 (plus:DI (match_operand:DI 1 "register_operand" "0")
1522 (mult:DI (sign_extend:DI
1144 (truncate:HI (match_operand:SI 2 "register_operand" "r"))) 1523 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1145 (sign_extend:DI 1524 (sign_extend:DI
1146 (truncate:HI (match_operand:SI 3 "register_operand" "r")))) 1525 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1147 (mult:DI (sign_extend:DI 1526 "TARGET_REALLY_IWMMXT"
1148 (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16)))) 1527 "tmiabb%?\\t%0, %2, %3"
1149 (sign_extend:DI 1528 [(set_attr "predicable" "yes")
1150 (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))] 1529 (set_attr "type" "wmmx_tmiaxy")]
1151 "TARGET_REALLY_IWMMXT" 1530 )
1152 "tmiaph%?\\t%0, %2, %3" 1531
1153 [(set_attr "predicable" "yes")]) 1532 (define_insn "iwmmxt_tmiatb"
1154 1533 [(set (match_operand:DI 0 "register_operand" "=y")
1155 (define_insn "iwmmxt_tmiabb" 1534 (plus:DI (match_operand:DI 1 "register_operand" "0")
1156 [(set (match_operand:DI 0 "register_operand" "=y")
1157 (plus:DI (match_operand:DI 1 "register_operand" "0")
1158 (mult:DI (sign_extend:DI 1535 (mult:DI (sign_extend:DI
1159 (truncate:HI (match_operand:SI 2 "register_operand" "r"))) 1536 (truncate:HI
1537 (ashiftrt:SI
1538 (match_operand:SI 2 "register_operand" "r")
1539 (const_int 16))))
1160 (sign_extend:DI 1540 (sign_extend:DI
1161 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))] 1541 (truncate:HI
1162 "TARGET_REALLY_IWMMXT" 1542 (match_operand:SI 3 "register_operand" "r"))))))]
1163 "tmiabb%?\\t%0, %2, %3" 1543 "TARGET_REALLY_IWMMXT"
1164 [(set_attr "predicable" "yes")]) 1544 "tmiatb%?\\t%0, %2, %3"
1165 1545 [(set_attr "predicable" "yes")
1166 (define_insn "iwmmxt_tmiatb" 1546 (set_attr "type" "wmmx_tmiaxy")]
1167 [(set (match_operand:DI 0 "register_operand" "=y") 1547 )
1168 (plus:DI (match_operand:DI 1 "register_operand" "0") 1548
1549 (define_insn "iwmmxt_tmiabt"
1550 [(set (match_operand:DI 0 "register_operand" "=y")
1551 (plus:DI (match_operand:DI 1 "register_operand" "0")
1169 (mult:DI (sign_extend:DI 1552 (mult:DI (sign_extend:DI
1170 (truncate:HI (ashiftrt:SI 1553 (truncate:HI
1171 (match_operand:SI 2 "register_operand" "r") 1554 (match_operand:SI 2 "register_operand" "r")))
1172 (const_int 16))))
1173 (sign_extend:DI 1555 (sign_extend:DI
1174 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))] 1556 (truncate:HI
1175 "TARGET_REALLY_IWMMXT" 1557 (ashiftrt:SI
1176 "tmiatb%?\\t%0, %2, %3" 1558 (match_operand:SI 3 "register_operand" "r")
1177 [(set_attr "predicable" "yes")]) 1559 (const_int 16)))))))]
1178
1179 (define_insn "iwmmxt_tmiabt"
1180 [(set (match_operand:DI 0 "register_operand" "=y")
1181 (plus:DI (match_operand:DI 1 "register_operand" "0")
1182 (mult:DI (sign_extend:DI
1183 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1184 (sign_extend:DI
1185 (truncate:HI (ashiftrt:SI
1186 (match_operand:SI 3 "register_operand" "r")
1187 (const_int 16)))))))]
1188 "TARGET_REALLY_IWMMXT" 1560 "TARGET_REALLY_IWMMXT"
1189 "tmiabt%?\\t%0, %2, %3" 1561 "tmiabt%?\\t%0, %2, %3"
1190 [(set_attr "predicable" "yes")]) 1562 [(set_attr "predicable" "yes")
1563 (set_attr "type" "wmmx_tmiaxy")]
1564 )
1191 1565
1192 (define_insn "iwmmxt_tmiatt" 1566 (define_insn "iwmmxt_tmiatt"
1193 [(set (match_operand:DI 0 "register_operand" "=y") 1567 [(set (match_operand:DI 0 "register_operand" "=y")
1194 (plus:DI (match_operand:DI 1 "register_operand" "0") 1568 (plus:DI (match_operand:DI 1 "register_operand" "0")
1195 (mult:DI (sign_extend:DI 1569 (mult:DI (sign_extend:DI
1196 (truncate:HI (ashiftrt:SI 1570 (truncate:HI
1197 (match_operand:SI 2 "register_operand" "r") 1571 (ashiftrt:SI
1198 (const_int 16)))) 1572 (match_operand:SI 2 "register_operand" "r")
1573 (const_int 16))))
1199 (sign_extend:DI 1574 (sign_extend:DI
1200 (truncate:HI (ashiftrt:SI 1575 (truncate:HI
1201 (match_operand:SI 3 "register_operand" "r") 1576 (ashiftrt:SI
1202 (const_int 16)))))))] 1577 (match_operand:SI 3 "register_operand" "r")
1578 (const_int 16)))))))]
1203 "TARGET_REALLY_IWMMXT" 1579 "TARGET_REALLY_IWMMXT"
1204 "tmiatt%?\\t%0, %2, %3" 1580 "tmiatt%?\\t%0, %2, %3"
1205 [(set_attr "predicable" "yes")]) 1581 [(set_attr "predicable" "yes")
1206 1582 (set_attr "type" "wmmx_tmiaxy")]
1207 (define_insn "iwmmxt_tbcstqi" 1583 )
1208 [(set (match_operand:V8QI 0 "register_operand" "=y")
1209 (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))]
1210 "TARGET_REALLY_IWMMXT"
1211 "tbcstb%?\\t%0, %1"
1212 [(set_attr "predicable" "yes")])
1213
1214 (define_insn "iwmmxt_tbcsthi"
1215 [(set (match_operand:V4HI 0 "register_operand" "=y")
1216 (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))]
1217 "TARGET_REALLY_IWMMXT"
1218 "tbcsth%?\\t%0, %1"
1219 [(set_attr "predicable" "yes")])
1220
1221 (define_insn "iwmmxt_tbcstsi"
1222 [(set (match_operand:V2SI 0 "register_operand" "=y")
1223 (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))]
1224 "TARGET_REALLY_IWMMXT"
1225 "tbcstw%?\\t%0, %1"
1226 [(set_attr "predicable" "yes")])
1227 1584
1228 (define_insn "iwmmxt_tmovmskb" 1585 (define_insn "iwmmxt_tmovmskb"
1229 [(set (match_operand:SI 0 "register_operand" "=r") 1586 [(set (match_operand:SI 0 "register_operand" "=r")
1230 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] 1587 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1231 "TARGET_REALLY_IWMMXT" 1588 "TARGET_REALLY_IWMMXT"
1232 "tmovmskb%?\\t%0, %1" 1589 "tmovmskb%?\\t%0, %1"
1233 [(set_attr "predicable" "yes")]) 1590 [(set_attr "predicable" "yes")
1591 (set_attr "type" "wmmx_tmovmsk")]
1592 )
1234 1593
1235 (define_insn "iwmmxt_tmovmskh" 1594 (define_insn "iwmmxt_tmovmskh"
1236 [(set (match_operand:SI 0 "register_operand" "=r") 1595 [(set (match_operand:SI 0 "register_operand" "=r")
1237 (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] 1596 (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1238 "TARGET_REALLY_IWMMXT" 1597 "TARGET_REALLY_IWMMXT"
1239 "tmovmskh%?\\t%0, %1" 1598 "tmovmskh%?\\t%0, %1"
1240 [(set_attr "predicable" "yes")]) 1599 [(set_attr "predicable" "yes")
1600 (set_attr "type" "wmmx_tmovmsk")]
1601 )
1241 1602
1242 (define_insn "iwmmxt_tmovmskw" 1603 (define_insn "iwmmxt_tmovmskw"
1243 [(set (match_operand:SI 0 "register_operand" "=r") 1604 [(set (match_operand:SI 0 "register_operand" "=r")
1244 (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] 1605 (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1245 "TARGET_REALLY_IWMMXT" 1606 "TARGET_REALLY_IWMMXT"
1246 "tmovmskw%?\\t%0, %1" 1607 "tmovmskw%?\\t%0, %1"
1247 [(set_attr "predicable" "yes")]) 1608 [(set_attr "predicable" "yes")
1609 (set_attr "type" "wmmx_tmovmsk")]
1610 )
1248 1611
1249 (define_insn "iwmmxt_waccb" 1612 (define_insn "iwmmxt_waccb"
1250 [(set (match_operand:DI 0 "register_operand" "=y") 1613 [(set (match_operand:DI 0 "register_operand" "=y")
1251 (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))] 1614 (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1252 "TARGET_REALLY_IWMMXT" 1615 "TARGET_REALLY_IWMMXT"
1253 "waccb%?\\t%0, %1" 1616 "waccb%?\\t%0, %1"
1254 [(set_attr "predicable" "yes")]) 1617 [(set_attr "predicable" "yes")
1618 (set_attr "type" "wmmx_wacc")]
1619 )
1255 1620
1256 (define_insn "iwmmxt_wacch" 1621 (define_insn "iwmmxt_wacch"
1257 [(set (match_operand:DI 0 "register_operand" "=y") 1622 [(set (match_operand:DI 0 "register_operand" "=y")
1258 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))] 1623 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1259 "TARGET_REALLY_IWMMXT" 1624 "TARGET_REALLY_IWMMXT"
1260 "wacch%?\\t%0, %1" 1625 "wacch%?\\t%0, %1"
1261 [(set_attr "predicable" "yes")]) 1626 [(set_attr "predicable" "yes")
1627 (set_attr "type" "wmmx_wacc")]
1628 )
1262 1629
1263 (define_insn "iwmmxt_waccw" 1630 (define_insn "iwmmxt_waccw"
1264 [(set (match_operand:DI 0 "register_operand" "=y") 1631 [(set (match_operand:DI 0 "register_operand" "=y")
1265 (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))] 1632 (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1266 "TARGET_REALLY_IWMMXT" 1633 "TARGET_REALLY_IWMMXT"
1267 "waccw%?\\t%0, %1" 1634 "waccw%?\\t%0, %1"
1268 [(set_attr "predicable" "yes")]) 1635 [(set_attr "predicable" "yes")
1269 1636 (set_attr "type" "wmmx_wacc")]
1270 (define_insn "iwmmxt_walign" 1637 )
1271 [(set (match_operand:V8QI 0 "register_operand" "=y,y") 1638
1639 ;; use unspec here to prevent 8 * imm to be optimized by cse
1640 (define_insn "iwmmxt_waligni"
1641 [(set (match_operand:V8QI 0 "register_operand" "=y")
1642 (unspec:V8QI [(subreg:V8QI
1643 (ashiftrt:TI
1644 (subreg:TI (vec_concat:V16QI
1645 (match_operand:V8QI 1 "register_operand" "y")
1646 (match_operand:V8QI 2 "register_operand" "y")) 0)
1647 (mult:SI
1648 (match_operand:SI 3 "immediate_operand" "i")
1649 (const_int 8))) 0)] UNSPEC_WALIGNI))]
1650 "TARGET_REALLY_IWMMXT"
1651 "waligni%?\\t%0, %1, %2, %3"
1652 [(set_attr "predicable" "yes")
1653 (set_attr "type" "wmmx_waligni")]
1654 )
1655
1656 (define_insn "iwmmxt_walignr"
1657 [(set (match_operand:V8QI 0 "register_operand" "=y")
1272 (subreg:V8QI (ashiftrt:TI 1658 (subreg:V8QI (ashiftrt:TI
1273 (subreg:TI (vec_concat:V16QI 1659 (subreg:TI (vec_concat:V16QI
1274 (match_operand:V8QI 1 "register_operand" "y,y") 1660 (match_operand:V8QI 1 "register_operand" "y")
1275 (match_operand:V8QI 2 "register_operand" "y,y")) 0) 1661 (match_operand:V8QI 2 "register_operand" "y")) 0)
1276 (mult:SI 1662 (mult:SI
1277 (match_operand:SI 3 "nonmemory_operand" "i,z") 1663 (zero_extract:SI (match_operand:SI 3 "register_operand" "z") (const_int 3) (const_int 0))
1278 (const_int 8))) 0))] 1664 (const_int 8))) 0))]
1279 "TARGET_REALLY_IWMMXT" 1665 "TARGET_REALLY_IWMMXT"
1280 "@ 1666 "walignr%U3%?\\t%0, %1, %2"
1281 waligni%?\\t%0, %1, %2, %3 1667 [(set_attr "predicable" "yes")
1282 walignr%U3%?\\t%0, %1, %2" 1668 (set_attr "type" "wmmx_walignr")]
1283 [(set_attr "predicable" "yes")]) 1669 )
1284 1670
1285 (define_insn "iwmmxt_tmrc" 1671 (define_insn "iwmmxt_walignr0"
1286 [(set (match_operand:SI 0 "register_operand" "=r") 1672 [(set (match_operand:V8QI 0 "register_operand" "=y")
1287 (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] 1673 (subreg:V8QI (ashiftrt:TI
1288 VUNSPEC_TMRC))] 1674 (subreg:TI (vec_concat:V16QI
1289 "TARGET_REALLY_IWMMXT" 1675 (match_operand:V8QI 1 "register_operand" "y")
1290 "tmrc%?\\t%0, %w1" 1676 (match_operand:V8QI 2 "register_operand" "y")) 0)
1291 [(set_attr "predicable" "yes")]) 1677 (mult:SI
1292 1678 (zero_extract:SI (reg:SI WCGR0) (const_int 3) (const_int 0))
1293 (define_insn "iwmmxt_tmcr" 1679 (const_int 8))) 0))]
1294 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i") 1680 "TARGET_REALLY_IWMMXT"
1295 (match_operand:SI 1 "register_operand" "r")] 1681 "walignr0%?\\t%0, %1, %2"
1296 VUNSPEC_TMCR)] 1682 [(set_attr "predicable" "yes")
1297 "TARGET_REALLY_IWMMXT" 1683 (set_attr "type" "wmmx_walignr")]
1298 "tmcr%?\\t%w0, %1" 1684 )
1299 [(set_attr "predicable" "yes")]) 1685
1686 (define_insn "iwmmxt_walignr1"
1687 [(set (match_operand:V8QI 0 "register_operand" "=y")
1688 (subreg:V8QI (ashiftrt:TI
1689 (subreg:TI (vec_concat:V16QI
1690 (match_operand:V8QI 1 "register_operand" "y")
1691 (match_operand:V8QI 2 "register_operand" "y")) 0)
1692 (mult:SI
1693 (zero_extract:SI (reg:SI WCGR1) (const_int 3) (const_int 0))
1694 (const_int 8))) 0))]
1695 "TARGET_REALLY_IWMMXT"
1696 "walignr1%?\\t%0, %1, %2"
1697 [(set_attr "predicable" "yes")
1698 (set_attr "type" "wmmx_walignr")]
1699 )
1700
1701 (define_insn "iwmmxt_walignr2"
1702 [(set (match_operand:V8QI 0 "register_operand" "=y")
1703 (subreg:V8QI (ashiftrt:TI
1704 (subreg:TI (vec_concat:V16QI
1705 (match_operand:V8QI 1 "register_operand" "y")
1706 (match_operand:V8QI 2 "register_operand" "y")) 0)
1707 (mult:SI
1708 (zero_extract:SI (reg:SI WCGR2) (const_int 3) (const_int 0))
1709 (const_int 8))) 0))]
1710 "TARGET_REALLY_IWMMXT"
1711 "walignr2%?\\t%0, %1, %2"
1712 [(set_attr "predicable" "yes")
1713 (set_attr "type" "wmmx_walignr")]
1714 )
1715
1716 (define_insn "iwmmxt_walignr3"
1717 [(set (match_operand:V8QI 0 "register_operand" "=y")
1718 (subreg:V8QI (ashiftrt:TI
1719 (subreg:TI (vec_concat:V16QI
1720 (match_operand:V8QI 1 "register_operand" "y")
1721 (match_operand:V8QI 2 "register_operand" "y")) 0)
1722 (mult:SI
1723 (zero_extract:SI (reg:SI WCGR3) (const_int 3) (const_int 0))
1724 (const_int 8))) 0))]
1725 "TARGET_REALLY_IWMMXT"
1726 "walignr3%?\\t%0, %1, %2"
1727 [(set_attr "predicable" "yes")
1728 (set_attr "type" "wmmx_walignr")]
1729 )
1300 1730
1301 (define_insn "iwmmxt_wsadb" 1731 (define_insn "iwmmxt_wsadb"
1302 [(set (match_operand:V8QI 0 "register_operand" "=y") 1732 [(set (match_operand:V2SI 0 "register_operand" "=y")
1303 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") 1733 (unspec:V2SI [
1304 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))] 1734 (match_operand:V2SI 1 "register_operand" "0")
1305 "TARGET_REALLY_IWMMXT" 1735 (match_operand:V8QI 2 "register_operand" "y")
1306 "wsadb%?\\t%0, %1, %2" 1736 (match_operand:V8QI 3 "register_operand" "y")] UNSPEC_WSAD))]
1307 [(set_attr "predicable" "yes")]) 1737 "TARGET_REALLY_IWMMXT"
1738 "wsadb%?\\t%0, %2, %3"
1739 [(set_attr "predicable" "yes")
1740 (set_attr "type" "wmmx_wsad")]
1741 )
1308 1742
1309 (define_insn "iwmmxt_wsadh" 1743 (define_insn "iwmmxt_wsadh"
1310 [(set (match_operand:V4HI 0 "register_operand" "=y") 1744 [(set (match_operand:V2SI 0 "register_operand" "=y")
1311 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 1745 (unspec:V2SI [
1312 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))] 1746 (match_operand:V2SI 1 "register_operand" "0")
1313 "TARGET_REALLY_IWMMXT" 1747 (match_operand:V4HI 2 "register_operand" "y")
1314 "wsadh%?\\t%0, %1, %2" 1748 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WSAD))]
1315 [(set_attr "predicable" "yes")]) 1749 "TARGET_REALLY_IWMMXT"
1750 "wsadh%?\\t%0, %2, %3"
1751 [(set_attr "predicable" "yes")
1752 (set_attr "type" "wmmx_wsad")]
1753 )
1316 1754
1317 (define_insn "iwmmxt_wsadbz" 1755 (define_insn "iwmmxt_wsadbz"
1318 [(set (match_operand:V8QI 0 "register_operand" "=y") 1756 [(set (match_operand:V2SI 0 "register_operand" "=y")
1319 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") 1757 (unspec:V2SI [(match_operand:V8QI 1 "register_operand" "y")
1320 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))] 1758 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1321 "TARGET_REALLY_IWMMXT" 1759 "TARGET_REALLY_IWMMXT"
1322 "wsadbz%?\\t%0, %1, %2" 1760 "wsadbz%?\\t%0, %1, %2"
1323 [(set_attr "predicable" "yes")]) 1761 [(set_attr "predicable" "yes")
1762 (set_attr "type" "wmmx_wsad")]
1763 )
1324 1764
1325 (define_insn "iwmmxt_wsadhz" 1765 (define_insn "iwmmxt_wsadhz"
1326 [(set (match_operand:V4HI 0 "register_operand" "=y") 1766 [(set (match_operand:V2SI 0 "register_operand" "=y")
1327 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") 1767 (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "y")
1328 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))] 1768 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1329 "TARGET_REALLY_IWMMXT" 1769 "TARGET_REALLY_IWMMXT"
1330 "wsadhz%?\\t%0, %1, %2" 1770 "wsadhz%?\\t%0, %1, %2"
1331 [(set_attr "predicable" "yes")]) 1771 [(set_attr "predicable" "yes")
1332 1772 (set_attr "type" "wmmx_wsad")]
1773 )
1774
1775 (include "iwmmxt2.md")