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comparison gcc/config/bfin/bfin.h @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
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68:561a7518be6b 111:04ced10e8804
1 /* Definitions for the Blackfin port. 1 /* Definitions for the Blackfin port.
2 Copyright (C) 2005, 2007, 2008, 2009, 2010, 2011 2 Copyright (C) 2005-2017 Free Software Foundation, Inc.
3 Free Software Foundation, Inc.
4 Contributed by Analog Devices. 3 Contributed by Analog Devices.
5 4
6 This file is part of GCC. 5 This file is part of GCC.
7 6
8 GCC is free software; you can redistribute it and/or modify it 7 GCC is free software; you can redistribute it and/or modify it
20 <http://www.gnu.org/licenses/>. */ 19 <http://www.gnu.org/licenses/>. */
21 20
22 #ifndef _BFIN_CONFIG 21 #ifndef _BFIN_CONFIG
23 #define _BFIN_CONFIG 22 #define _BFIN_CONFIG
24 23
24 #ifndef BFIN_OPTS_H
25 #include "config/bfin/bfin-opts.h"
26 #endif
27
25 #define OBJECT_FORMAT_ELF 28 #define OBJECT_FORMAT_ELF
26 29
27 #define BRT 1 30 #define BRT 1
28 #define BRF 0 31 #define BRF 0
29
30 /* CPU type. */
31 typedef enum bfin_cpu_type
32 {
33 BFIN_CPU_UNKNOWN,
34 BFIN_CPU_BF512,
35 BFIN_CPU_BF514,
36 BFIN_CPU_BF516,
37 BFIN_CPU_BF518,
38 BFIN_CPU_BF522,
39 BFIN_CPU_BF523,
40 BFIN_CPU_BF524,
41 BFIN_CPU_BF525,
42 BFIN_CPU_BF526,
43 BFIN_CPU_BF527,
44 BFIN_CPU_BF531,
45 BFIN_CPU_BF532,
46 BFIN_CPU_BF533,
47 BFIN_CPU_BF534,
48 BFIN_CPU_BF536,
49 BFIN_CPU_BF537,
50 BFIN_CPU_BF538,
51 BFIN_CPU_BF539,
52 BFIN_CPU_BF542,
53 BFIN_CPU_BF542M,
54 BFIN_CPU_BF544,
55 BFIN_CPU_BF544M,
56 BFIN_CPU_BF547,
57 BFIN_CPU_BF547M,
58 BFIN_CPU_BF548,
59 BFIN_CPU_BF548M,
60 BFIN_CPU_BF549,
61 BFIN_CPU_BF549M,
62 BFIN_CPU_BF561
63 } bfin_cpu_t;
64
65 /* Value of -mcpu= */
66 extern bfin_cpu_t bfin_cpu_type;
67
68 /* Value of -msi-revision= */
69 extern int bfin_si_revision;
70
71 extern unsigned int bfin_workarounds;
72
73 /* Print subsidiary information on the compiler version in use. */
74 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)")
75 32
76 /* Predefinition in the preprocessor for this target machine */ 33 /* Predefinition in the preprocessor for this target machine */
77 #ifndef TARGET_CPU_CPP_BUILTINS 34 #ifndef TARGET_CPU_CPP_BUILTINS
78 #define TARGET_CPU_CPP_BUILTINS() \ 35 #define TARGET_CPU_CPP_BUILTINS() \
79 do \ 36 do \
83 builtin_define ("__ADSPBLACKFIN__"); \ 40 builtin_define ("__ADSPBLACKFIN__"); \
84 builtin_define ("__ADSPLPBLACKFIN__"); \ 41 builtin_define ("__ADSPLPBLACKFIN__"); \
85 \ 42 \
86 switch (bfin_cpu_type) \ 43 switch (bfin_cpu_type) \
87 { \ 44 { \
45 case BFIN_CPU_UNKNOWN: \
46 break; \
88 case BFIN_CPU_BF512: \ 47 case BFIN_CPU_BF512: \
89 builtin_define ("__ADSPBF512__"); \ 48 builtin_define ("__ADSPBF512__"); \
90 builtin_define ("__ADSPBF51x__"); \ 49 builtin_define ("__ADSPBF51x__"); \
91 break; \ 50 break; \
92 case BFIN_CPU_BF514: \ 51 case BFIN_CPU_BF514: \
149 case BFIN_CPU_BF539: \ 108 case BFIN_CPU_BF539: \
150 builtin_define ("__ADSPBF539__"); \ 109 builtin_define ("__ADSPBF539__"); \
151 break; \ 110 break; \
152 case BFIN_CPU_BF542M: \ 111 case BFIN_CPU_BF542M: \
153 builtin_define ("__ADSPBF542M__"); \ 112 builtin_define ("__ADSPBF542M__"); \
113 /* FALLTHRU */ \
154 case BFIN_CPU_BF542: \ 114 case BFIN_CPU_BF542: \
155 builtin_define ("__ADSPBF542__"); \ 115 builtin_define ("__ADSPBF542__"); \
156 builtin_define ("__ADSPBF54x__"); \ 116 builtin_define ("__ADSPBF54x__"); \
157 break; \ 117 break; \
158 case BFIN_CPU_BF544M: \ 118 case BFIN_CPU_BF544M: \
159 builtin_define ("__ADSPBF544M__"); \ 119 builtin_define ("__ADSPBF544M__"); \
120 /* FALLTHRU */ \
160 case BFIN_CPU_BF544: \ 121 case BFIN_CPU_BF544: \
161 builtin_define ("__ADSPBF544__"); \ 122 builtin_define ("__ADSPBF544__"); \
162 builtin_define ("__ADSPBF54x__"); \ 123 builtin_define ("__ADSPBF54x__"); \
163 break; \ 124 break; \
164 case BFIN_CPU_BF547M: \ 125 case BFIN_CPU_BF547M: \
165 builtin_define ("__ADSPBF547M__"); \ 126 builtin_define ("__ADSPBF547M__"); \
127 /* FALLTHRU */ \
166 case BFIN_CPU_BF547: \ 128 case BFIN_CPU_BF547: \
167 builtin_define ("__ADSPBF547__"); \ 129 builtin_define ("__ADSPBF547__"); \
168 builtin_define ("__ADSPBF54x__"); \ 130 builtin_define ("__ADSPBF54x__"); \
169 break; \ 131 break; \
170 case BFIN_CPU_BF548M: \ 132 case BFIN_CPU_BF548M: \
171 builtin_define ("__ADSPBF548M__"); \ 133 builtin_define ("__ADSPBF548M__"); \
134 /* FALLTHRU */ \
172 case BFIN_CPU_BF548: \ 135 case BFIN_CPU_BF548: \
173 builtin_define ("__ADSPBF548__"); \ 136 builtin_define ("__ADSPBF548__"); \
174 builtin_define ("__ADSPBF54x__"); \ 137 builtin_define ("__ADSPBF54x__"); \
175 break; \ 138 break; \
176 case BFIN_CPU_BF549M: \ 139 case BFIN_CPU_BF549M: \
177 builtin_define ("__ADSPBF549M__"); \ 140 builtin_define ("__ADSPBF549M__"); \
141 /* FALLTHRU */ \
178 case BFIN_CPU_BF549: \ 142 case BFIN_CPU_BF549: \
179 builtin_define ("__ADSPBF549__"); \ 143 builtin_define ("__ADSPBF549__"); \
180 builtin_define ("__ADSPBF54x__"); \ 144 builtin_define ("__ADSPBF54x__"); \
181 break; \ 145 break; \
182 case BFIN_CPU_BF561: \ 146 case BFIN_CPU_BF561: \
183 builtin_define ("__ADSPBF561__"); \ 147 builtin_define ("__ADSPBF561__"); \
184 break; \ 148 break; \
149 case BFIN_CPU_BF592: \
150 builtin_define ("__ADSPBF592__"); \
151 builtin_define ("__ADSPBF59x__"); \
152 break; \
185 } \ 153 } \
186 \ 154 \
187 if (bfin_si_revision != -1) \ 155 if (bfin_si_revision != -1) \
188 { \ 156 { \
189 /* space of 0xnnnn and a NUL */ \ 157 /* space of 0xnnnn and a NUL */ \
268 This is the value stored for true. */ 236 This is the value stored for true. */
269 #define STORE_FLAG_VALUE 1 237 #define STORE_FLAG_VALUE 1
270 238
271 /* Define this if pushing a word on the stack 239 /* Define this if pushing a word on the stack
272 makes the stack pointer a smaller address. */ 240 makes the stack pointer a smaller address. */
273 #define STACK_GROWS_DOWNWARD 241 #define STACK_GROWS_DOWNWARD 1
274 242
275 #define STACK_PUSH_CODE PRE_DEC 243 #define STACK_PUSH_CODE PRE_DEC
276 244
277 /* Define this to nonzero if the nominal address of the stack frame 245 /* Define this to nonzero if the nominal address of the stack frame
278 is at the high-address end of the local variables; 246 is at the high-address end of the local variables;
281 #define FRAME_GROWS_DOWNWARD 1 249 #define FRAME_GROWS_DOWNWARD 1
282 250
283 /* We define a dummy ARGP register; the parameters start at offset 0 from 251 /* We define a dummy ARGP register; the parameters start at offset 0 from
284 it. */ 252 it. */
285 #define FIRST_PARM_OFFSET(DECL) 0 253 #define FIRST_PARM_OFFSET(DECL) 0
286
287 /* Offset within stack frame to start allocating local variables at.
288 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
289 first local allocated. Otherwise, it is the offset to the BEGINNING
290 of the first local allocated. */
291 #define STARTING_FRAME_OFFSET 0
292 254
293 /* Register to use for pushing function arguments. */ 255 /* Register to use for pushing function arguments. */
294 #define STACK_POINTER_REGNUM REG_P6 256 #define STACK_POINTER_REGNUM REG_P6
295 257
296 /* Base register for access to local variables of the function. */ 258 /* Base register for access to local variables of the function. */
350 312
351 One use of this macro is to increase alignment of medium-size 313 One use of this macro is to increase alignment of medium-size
352 data to make it all fit in fewer cache lines. */ 314 data to make it all fit in fewer cache lines. */
353 315
354 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN)) 316 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN))
355
356 /* Make strings word-aligned so strcpy from constants will be faster. */
357 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
358 (TREE_CODE (EXP) == STRING_CST \
359 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
360 317
361 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18) 318 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18)
362 319
363 /* Definitions for register eliminations. 320 /* Definitions for register eliminations.
364 321
648 #define IREG_POSSIBLE_P(OUTER) \ 605 #define IREG_POSSIBLE_P(OUTER) \
649 ((OUTER) == POST_INC || (OUTER) == PRE_INC \ 606 ((OUTER) == POST_INC || (OUTER) == PRE_INC \
650 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \ 607 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \
651 || (OUTER) == MEM || (OUTER) == ADDRESS) 608 || (OUTER) == MEM || (OUTER) == ADDRESS)
652 609
653 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \ 610 #define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \
654 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS) 611 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS)
655 612
656 #define INDEX_REG_CLASS PREGS 613 #define INDEX_REG_CLASS PREGS
657 614
658 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \ 615 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \
663 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \ 620 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \
664 ((X) >= FIRST_PSEUDO_REGISTER \ 621 ((X) >= FIRST_PSEUDO_REGISTER \
665 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)) 622 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX))
666 623
667 #ifdef REG_OK_STRICT 624 #ifdef REG_OK_STRICT
668 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \ 625 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \
669 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX) 626 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)
670 #else 627 #else
671 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \ 628 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \
672 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX) 629 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX)
673 #endif 630 #endif
674 631
675 #define REGNO_OK_FOR_INDEX_P(X) 0 632 #define REGNO_OK_FOR_INDEX_P(X) 0
676 633
701 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \ 658 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \
702 : (REGNO) == REG_CC ? CCREGS \ 659 : (REGNO) == REG_CC ? CCREGS \
703 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ 660 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \
704 : NO_REGS) 661 : NO_REGS)
705 662
706 /* The following macro defines cover classes for Integrated Register
707 Allocator. Cover classes is a set of non-intersected register
708 classes covering all hard registers used for register allocation
709 purpose. Any move between two registers of a cover class should be
710 cheaper than load or store of the registers. The macro value is
711 array of register classes with LIM_REG_CLASSES used as the end
712 marker. */
713
714 #define IRA_COVER_CLASSES \
715 { \
716 MOST_REGS, AREGS, CCREGS, LIM_REG_CLASSES \
717 }
718
719 /* When this hook returns true for MODE, the compiler allows 663 /* When this hook returns true for MODE, the compiler allows
720 registers explicitly used in the rtl to be used as spill registers 664 registers explicitly used in the rtl to be used as spill registers
721 but prevents the compiler from extending the lifetime of these 665 but prevents the compiler from extending the lifetime of these
722 registers. */ 666 registers. */
723 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 667 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
724 668
725 /* Do not allow to store a value in REG_CC for any mode */
726 /* Do not allow to store value in pregs if mode is not SI*/
727 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE))
728
729 /* Return the maximum number of consecutive registers 669 /* Return the maximum number of consecutive registers
730 needed to represent mode MODE in a register of class CLASS. */ 670 needed to represent mode MODE in a register of class CLASS. */
731 #define CLASS_MAX_NREGS(CLASS, MODE) \ 671 #define CLASS_MAX_NREGS(CLASS, MODE) \
732 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \ 672 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \
733 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 673 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
734 674
735 #define HARD_REGNO_NREGS(REGNO, MODE) \
736 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \
737 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \
738 : CLASS_MAX_NREGS (GENERAL_REGS, MODE))
739
740 /* A C expression that is nonzero if hard register TO can be 675 /* A C expression that is nonzero if hard register TO can be
741 considered for use as a rename register for FROM register */ 676 considered for use as a rename register for FROM register */
742 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO) 677 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO)
743
744 /* A C expression that is nonzero if it is desirable to choose
745 register allocation so as to avoid move instructions between a
746 value of mode MODE1 and a value of mode MODE2.
747
748 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R,
749 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1,
750 MODE2)' must be zero. */
751 #define MODES_TIEABLE_P(MODE1, MODE2) \
752 ((MODE1) == (MODE2) \
753 || ((GET_MODE_CLASS (MODE1) == MODE_INT \
754 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \
755 && (GET_MODE_CLASS (MODE2) == MODE_INT \
756 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \
757 && (MODE1) != BImode && (MODE2) != BImode \
758 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \
759 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD))
760 678
761 /* `PREFERRED_RELOAD_CLASS (X, CLASS)' 679 /* `PREFERRED_RELOAD_CLASS (X, CLASS)'
762 A C expression that places additional restrictions on the register 680 A C expression that places additional restrictions on the register
763 class to use when it is necessary to copy value X into a register 681 class to use when it is necessary to copy value X into a register
764 in class CLASS. The value is a register class; perhaps CLASS, or 682 in class CLASS. The value is a register class; perhaps CLASS, or
833 751
834 /* Describe how we implement __builtin_eh_return. */ 752 /* Describe how we implement __builtin_eh_return. */
835 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 753 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
836 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2) 754 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2)
837 #define EH_RETURN_HANDLER_RTX \ 755 #define EH_RETURN_HANDLER_RTX \
838 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD)) 756 gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx, \
757 UNITS_PER_WORD))
839 758
840 /* Addressing Modes */ 759 /* Addressing Modes */
841
842 /* Nonzero if the constant value X is a legitimate general operand.
843 symbol_ref are not legitimate and will be put into constant pool.
844 See force_const_mem().
845 If -mno-pool, all constants are legitimate.
846 */
847 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X)
848 760
849 /* A number, the maximum number of registers that can appear in a 761 /* A number, the maximum number of registers that can appear in a
850 valid memory address. Note that it is up to you to specify a 762 valid memory address. Note that it is up to you to specify a
851 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P' 763 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P'
852 would ever accept. */ 764 would ever accept. */
874 || GET_CODE (X) == LABEL_REF \ 786 || GET_CODE (X) == LABEL_REF \
875 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 787 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
876 788
877 #define NOTICE_UPDATE_CC(EXPR, INSN) 0 789 #define NOTICE_UPDATE_CC(EXPR, INSN) 0
878 790
879 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
880 is done just by pretending it is already truncated. */
881 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
882
883 /* Max number of bytes we can move from memory to memory 791 /* Max number of bytes we can move from memory to memory
884 in one reasonably fast instruction. */ 792 in one reasonably fast instruction. */
885 #define MOVE_MAX UNITS_PER_WORD 793 #define MOVE_MAX UNITS_PER_WORD
886 794
887 /* If a memory-to-memory move would take MOVE_RATIO or more simple 795 /* If a memory-to-memory move would take MOVE_RATIO or more simple
915 #define BYTES_BIG_ENDIAN 0 823 #define BYTES_BIG_ENDIAN 0
916 824
917 /* Define this if most significant word of a multiword number is numbered. */ 825 /* Define this if most significant word of a multiword number is numbered. */
918 #define WORDS_BIG_ENDIAN 0 826 #define WORDS_BIG_ENDIAN 0
919 827
920 /* number of bits in an addressable storage unit */
921 #define BITS_PER_UNIT 8
922
923 /* Width in bits of a "word", which is the contents of a machine register. 828 /* Width in bits of a "word", which is the contents of a machine register.
924 Note that this is not necessarily the width of data type `int'; 829 Note that this is not necessarily the width of data type `int';
925 if using 16-bit ints on a 68000, this would still be 32. 830 if using 16-bit ints on a 68000, this would still be 32.
926 But on a machine with 16-bit registers, this would be 16. */ 831 But on a machine with 16-bit registers, this would be 16. */
927 #define BITS_PER_WORD 32 832 #define BITS_PER_WORD 32
1031 /* Describing Relative Costs of Operations */ 936 /* Describing Relative Costs of Operations */
1032 937
1033 /* Do not put function addr into constant pool */ 938 /* Do not put function addr into constant pool */
1034 #define NO_FUNCTION_CSE 1 939 #define NO_FUNCTION_CSE 1
1035 940
1036 /* A C expression for the cost of moving data from a register in class FROM to
1037 one in class TO. The classes are expressed using the enumeration values
1038 such as `GENERAL_REGS'. A value of 2 is the default; other values are
1039 interpreted relative to that.
1040
1041 It is not required that the cost always equal 2 when FROM is the same as TO;
1042 on some machines it is expensive to move between registers if they are not
1043 general registers. */
1044
1045 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1046 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2))
1047
1048 /* A C expression for the cost of moving data of mode M between a
1049 register and memory. A value of 2 is the default; this cost is
1050 relative to those in `REGISTER_MOVE_COST'.
1051
1052 If moving between registers and memory is more expensive than
1053 between two registers, you should define this macro to express the
1054 relative cost. */
1055
1056 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
1057 bfin_memory_move_cost ((MODE), (CLASS), (IN))
1058
1059 /* Specify the machine mode that this machine uses 941 /* Specify the machine mode that this machine uses
1060 for the index in the tablejump instruction. */ 942 for the index in the tablejump instruction. */
1061 #define CASE_VECTOR_MODE SImode 943 #define CASE_VECTOR_MODE SImode
1062 944
1063 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic 945 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic
1064 946
1065 /* Define if operations between registers always perform the operation 947 /* Define if operations between registers always perform the operation
1066 on the full register even if a narrower mode is specified. 948 on the full register even if a narrower mode is specified.
1067 #define WORD_REGISTER_OPERATIONS 949 #define WORD_REGISTER_OPERATIONS 1
1068 */ 950 */
1069 951
1070 /* Evaluates to true if A and B are mac flags that can be used 952 /* Evaluates to true if A and B are mac flags that can be used
1071 together in a single multiply insn. That is the case if they are 953 together in a single multiply insn. That is the case if they are
1072 both the same flag not involving M, or if one is a combination of 954 both the same flag not involving M, or if one is a combination of
1186 ASM_GLOBALIZE_LABEL1(FILE,NAME); \ 1068 ASM_GLOBALIZE_LABEL1(FILE,NAME); \
1187 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0) 1069 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0)
1188 1070
1189 #define ASM_COMMENT_START "//" 1071 #define ASM_COMMENT_START "//"
1190 1072
1073 #define PROFILE_BEFORE_PROLOGUE
1191 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1074 #define FUNCTION_PROFILER(FILE, LABELNO) \
1192 do { \ 1075 do { \
1193 fprintf (FILE, "\tCALL __mcount;\n"); \ 1076 fprintf (FILE, "\t[--SP] = RETS;\n"); \
1077 if (TARGET_LONG_CALLS) \
1078 { \
1079 fprintf (FILE, "\tP2.h = __mcount;\n"); \
1080 fprintf (FILE, "\tP2.l = __mcount;\n"); \
1081 fprintf (FILE, "\tCALL (P2);\n"); \
1082 } \
1083 else \
1084 fprintf (FILE, "\tCALL __mcount;\n"); \
1085 fprintf (FILE, "\tRETS = [SP++];\n"); \
1194 } while(0) 1086 } while(0)
1195 1087
1196 #undef NO_PROFILE_COUNTERS 1088 #undef NO_PROFILE_COUNTERS
1197 #define NO_PROFILE_COUNTERS 1 1089 #define NO_PROFILE_COUNTERS 1
1198 1090
1199 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO]) 1091 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "\t[--SP] = %s;\n", reg_names[REGNO])
1200 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO]) 1092 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "\t%s = [SP++];\n", reg_names[REGNO])
1201 1093
1202 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx; 1094 extern rtx bfin_cc_rtx, bfin_rets_rtx;
1203 1095
1204 /* This works for GAS and some other assemblers. */ 1096 /* This works for GAS and some other assemblers. */
1205 #define SET_ASM_OP ".set " 1097 #define SET_ASM_OP ".set "
1206 1098
1207 /* DBX register number for a given compiler register number */ 1099 /* DBX register number for a given compiler register number */
1215 1107
1216 #ifndef TARGET_SUPPORTS_SYNC_CALLS 1108 #ifndef TARGET_SUPPORTS_SYNC_CALLS
1217 #define TARGET_SUPPORTS_SYNC_CALLS 0 1109 #define TARGET_SUPPORTS_SYNC_CALLS 0
1218 #endif 1110 #endif
1219 1111
1112 struct bfin_cpu
1113 {
1114 const char *name;
1115 bfin_cpu_t type;
1116 int si_revision;
1117 unsigned int workarounds;
1118 };
1119
1120 extern const struct bfin_cpu bfin_cpus[];
1121
1220 #endif /* _BFIN_CONFIG */ 1122 #endif /* _BFIN_CONFIG */