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comparison gcc/config/frv/frv.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
comparison
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68:561a7518be6b 111:04ced10e8804
1 ;; Frv Machine Description 1 ;; Frv Machine Description
2 ;; Copyright (C) 1999, 2000, 2001, 2003, 2004, 2005, 2007, 2008, 2010 2 ;; Copyright (C) 1999-2017 Free Software Foundation, Inc.
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat, Inc. 3 ;; Contributed by Red Hat, Inc.
5 4
6 ;; This file is part of GCC. 5 ;; This file is part of GCC.
7 6
8 ;; GCC is free software; you can redistribute it and/or modify 7 ;; GCC is free software; you can redistribute it and/or modify
88 87
89 (define_mode_iterator IMODE [QI HI SI DI]) 88 (define_mode_iterator IMODE [QI HI SI DI])
90 (define_mode_attr IMODEsuffix [(QI "b") (HI "h") (SI "") (DI "d")]) 89 (define_mode_attr IMODEsuffix [(QI "b") (HI "h") (SI "") (DI "d")])
91 (define_mode_attr BREADsuffix [(QI "ub") (HI "uh") (SI "") (DI "d")]) 90 (define_mode_attr BREADsuffix [(QI "ub") (HI "uh") (SI "") (DI "d")])
92 91
93 ;; ::::::::::::::::::::
94 ;; ::
95 ;; :: Constraints
96 ;; ::
97 ;; ::::::::::::::::::::
98
99 ;; Standard Constraints
100 ;;
101 ;; `m' A memory operand is allowed, with any kind of address that the
102 ;; machine supports in general.
103 ;;
104 ;; `o' A memory operand is allowed, but only if the address is
105 ;; "offsettable". This means that adding a small integer (actually, the
106 ;; width in bytes of the operand, as determined by its machine mode) may be
107 ;; added to the address and the result is also a valid memory address.
108 ;;
109 ;; `V' A memory operand that is not offsettable. In other words,
110 ;; anything that would fit the `m' constraint but not the `o' constraint.
111 ;;
112 ;; `<' A memory operand with autodecrement addressing (either
113 ;; predecrement or postdecrement) is allowed.
114 ;;
115 ;; `>' A memory operand with autoincrement addressing (either
116 ;; preincrement or postincrement) is allowed.
117 ;;
118 ;; `r' A register operand is allowed provided that it is in a general
119 ;; register.
120 ;;
121 ;; `d', `a', `f', ...
122 ;; Other letters can be defined in machine-dependent fashion to stand for
123 ;; particular classes of registers. `d', `a' and `f' are defined on the
124 ;; 68000/68020 to stand for data, address and floating point registers.
125 ;;
126 ;; `i' An immediate integer operand (one with constant value) is allowed.
127 ;; This includes symbolic constants whose values will be known only at
128 ;; assembly time.
129 ;;
130 ;; `n' An immediate integer operand with a known numeric value is allowed.
131 ;; Many systems cannot support assembly-time constants for operands less
132 ;; than a word wide. Constraints for these operands should use `n' rather
133 ;; than `i'.
134 ;;
135 ;; 'I' First machine-dependent integer constant (6-bit signed ints).
136 ;; 'J' Second machine-dependent integer constant (10-bit signed ints).
137 ;; 'K' Third machine-dependent integer constant (-2048).
138 ;; 'L' Fourth machine-dependent integer constant (16-bit signed ints).
139 ;; 'M' Fifth machine-dependent integer constant (16-bit unsigned ints).
140 ;; 'N' Sixth machine-dependent integer constant (-2047..-1).
141 ;; 'O' Seventh machine-dependent integer constant (zero).
142 ;; 'P' Eighth machine-dependent integer constant (1..2047).
143 ;;
144 ;; Other letters in the range `I' through `P' may be defined in a
145 ;; machine-dependent fashion to permit immediate integer operands with
146 ;; explicit integer values in specified ranges. For example, on the 68000,
147 ;; `I' is defined to stand for the range of values 1 to 8. This is the
148 ;; range permitted as a shift count in the shift instructions.
149 ;;
150 ;; `E' An immediate floating operand (expression code `const_double') is
151 ;; allowed, but only if the target floating point format is the same as
152 ;; that of the host machine (on which the compiler is running).
153 ;;
154 ;; `F' An immediate floating operand (expression code `const_double') is
155 ;; allowed.
156 ;;
157 ;; 'G' First machine-dependent const_double.
158 ;; 'H' Second machine-dependent const_double.
159 ;;
160 ;; `s' An immediate integer operand whose value is not an explicit
161 ;; integer is allowed.
162 ;;
163 ;; This might appear strange; if an insn allows a constant operand with a
164 ;; value not known at compile time, it certainly must allow any known
165 ;; value. So why use `s' instead of `i'? Sometimes it allows better code
166 ;; to be generated.
167 ;;
168 ;; For example, on the 68000 in a fullword instruction it is possible to
169 ;; use an immediate operand; but if the immediate value is between -128 and
170 ;; 127, better code results from loading the value into a register and
171 ;; using the register. This is because the load into the register can be
172 ;; done with a `moveq' instruction. We arrange for this to happen by
173 ;; defining the letter `K' to mean "any integer outside the range -128 to
174 ;; 127", and then specifying `Ks' in the operand constraints.
175 ;;
176 ;; `g' Any register, memory or immediate integer operand is allowed,
177 ;; except for registers that are not general registers.
178 ;;
179 ;; `X' Any operand whatsoever is allowed, even if it does not satisfy
180 ;; `general_operand'. This is normally used in the constraint of a
181 ;; `match_scratch' when certain alternatives will not actually require a
182 ;; scratch register.
183 ;;
184 ;; `0' Match operand 0.
185 ;; `1' Match operand 1.
186 ;; `2' Match operand 2.
187 ;; `3' Match operand 3.
188 ;; `4' Match operand 4.
189 ;; `5' Match operand 5.
190 ;; `6' Match operand 6.
191 ;; `7' Match operand 7.
192 ;; `8' Match operand 8.
193 ;; `9' Match operand 9.
194 ;;
195 ;; An operand that matches the specified operand number is allowed. If a
196 ;; digit is used together with letters within the same alternative, the
197 ;; digit should come last.
198 ;;
199 ;; This is called a "matching constraint" and what it really means is that
200 ;; the assembler has only a single operand that fills two roles considered
201 ;; separate in the RTL insn. For example, an add insn has two input
202 ;; operands and one output operand in the RTL, but on most CISC machines an
203 ;; add instruction really has only two operands, one of them an
204 ;; input-output operand:
205 ;;
206 ;; addl #35,r12
207 ;;
208 ;; Matching constraints are used in these circumstances. More precisely,
209 ;; the two operands that match must include one input-only operand and one
210 ;; output-only operand. Moreover, the digit must be a smaller number than
211 ;; the number of the operand that uses it in the constraint.
212 ;;
213 ;; For operands to match in a particular case usually means that they are
214 ;; identical-looking RTL expressions. But in a few special cases specific
215 ;; kinds of dissimilarity are allowed. For example, `*x' as an input
216 ;; operand will match `*x++' as an output operand. For proper results in
217 ;; such cases, the output template should always use the output-operand's
218 ;; number when printing the operand.
219 ;;
220 ;; `p' An operand that is a valid memory address is allowed. This is for
221 ;; "load address" and "push address" instructions.
222 ;;
223 ;; `p' in the constraint must be accompanied by `address_operand' as the
224 ;; predicate in the `match_operand'. This predicate interprets the mode
225 ;; specified in the `match_operand' as the mode of the memory reference for
226 ;; which the address would be valid.
227 ;;
228 ;; `Q` First non constant, non register machine-dependent insns
229 ;; `R` Second non constant, non register machine-dependent insns
230 ;; `S` Third non constant, non register machine-dependent insns
231 ;; `T` Fourth non constant, non register machine-dependent insns
232 ;; `U` Fifth non constant, non register machine-dependent insns
233 ;;
234 ;; Letters in the range `Q' through `U' may be defined in a
235 ;; machine-dependent fashion to stand for arbitrary operand types. The
236 ;; machine description macro `EXTRA_CONSTRAINT' is passed the operand as
237 ;; its first argument and the constraint letter as its second operand.
238 ;;
239 ;; A typical use for this would be to distinguish certain types of memory
240 ;; references that affect other insn operands.
241 ;;
242 ;; Do not define these constraint letters to accept register references
243 ;; (`reg'); the reload pass does not expect this and would not handle it
244 ;; properly.
245
246 ;; Multiple Alternative Constraints
247 ;; `?' Disparage slightly the alternative that the `?' appears in, as a
248 ;; choice when no alternative applies exactly. The compiler regards this
249 ;; alternative as one unit more costly for each `?' that appears in it.
250 ;;
251 ;; `!' Disparage severely the alternative that the `!' appears in. This
252 ;; alternative can still be used if it fits without reloading, but if
253 ;; reloading is needed, some other alternative will be used.
254
255 ;; Constraint modifiers
256 ;; `=' Means that this operand is write-only for this instruction: the
257 ;; previous value is discarded and replaced by output data.
258 ;;
259 ;; `+' Means that this operand is both read and written by the
260 ;; instruction.
261 ;;
262 ;; When the compiler fixes up the operands to satisfy the constraints, it
263 ;; needs to know which operands are inputs to the instruction and which are
264 ;; outputs from it. `=' identifies an output; `+' identifies an operand
265 ;; that is both input and output; all other operands are assumed to be
266 ;; input only.
267 ;;
268 ;; `&' Means (in a particular alternative) that this operand is written
269 ;; before the instruction is finished using the input operands. Therefore,
270 ;; this operand may not lie in a register that is used as an input operand
271 ;; or as part of any memory address.
272 ;;
273 ;; `&' applies only to the alternative in which it is written. In
274 ;; constraints with multiple alternatives, sometimes one alternative
275 ;; requires `&' while others do not.
276 ;;
277 ;; `&' does not obviate the need to write `='.
278 ;;
279 ;; `%' Declares the instruction to be commutative for this operand and the
280 ;; following operand. This means that the compiler may interchange the two
281 ;; operands if that is the cheapest way to make all operands fit the
282 ;; constraints. This is often used in patterns for addition instructions
283 ;; that really have only two operands: the result must go in one of the
284 ;; arguments.
285 ;;
286 ;; `#' Says that all following characters, up to the next comma, are to be
287 ;; ignored as a constraint. They are significant only for choosing
288 ;; register preferences.
289 ;;
290 ;; `*' Says that the following character should be ignored when choosing
291 ;; register preferences. `*' has no effect on the meaning of the
292 ;; constraint as a constraint, and no effect on reloading.
293
294
295 ;; ::::::::::::::::::::
296 ;; ::
297 ;; :: Attributes
298 ;; ::
299 ;; ::::::::::::::::::::
300
301 ;; The `define_attr' expression is used to define each attribute required by
302 ;; the target machine. It looks like:
303 ;;
304 ;; (define_attr NAME LIST-OF-VALUES DEFAULT)
305
306 ;; NAME is a string specifying the name of the attribute being defined.
307
308 ;; LIST-OF-VALUES is either a string that specifies a comma-separated list of
309 ;; values that can be assigned to the attribute, or a null string to indicate
310 ;; that the attribute takes numeric values.
311
312 ;; DEFAULT is an attribute expression that gives the value of this attribute
313 ;; for insns that match patterns whose definition does not include an explicit
314 ;; value for this attribute.
315
316 ;; For each defined attribute, a number of definitions are written to the
317 ;; `insn-attr.h' file. For cases where an explicit set of values is specified
318 ;; for an attribute, the following are defined:
319
320 ;; * A `#define' is written for the symbol `HAVE_ATTR_NAME'.
321 ;;
322 ;; * An enumeral class is defined for `attr_NAME' with elements of the
323 ;; form `UPPER-NAME_UPPER-VALUE' where the attribute name and value are first
324 ;; converted to upper case.
325 ;;
326 ;; * A function `get_attr_NAME' is defined that is passed an insn and
327 ;; returns the attribute value for that insn.
328
329 ;; For example, if the following is present in the `md' file:
330 ;;
331 ;; (define_attr "type" "branch,fp,load,store,arith" ...)
332 ;;
333 ;; the following lines will be written to the file `insn-attr.h'.
334 ;;
335 ;; #define HAVE_ATTR_type
336 ;; enum attr_type {TYPE_BRANCH, TYPE_FP, TYPE_LOAD, TYPE_STORE, TYPE_ARITH};
337 ;; extern enum attr_type get_attr_type ();
338
339 ;; If the attribute takes numeric values, no `enum' type will be defined and
340 ;; the function to obtain the attribute's value will return `int'.
341
342 (define_attr "length" "" (const_int 4)) 92 (define_attr "length" "" (const_int 4))
343 93
344 ;; Processor type -- this attribute must exactly match the processor_type 94 ;; Processor type -- this attribute must exactly match the processor_type
345 ;; enumeration in frv-protos.h. 95 ;; enumeration in frv-protos.h.
346 96
1583 ;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and 1333 ;; registers after reload, you must define `SECONDARY_INPUT_RELOAD_CLASS' and
1584 ;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide 1334 ;; perhaps also `SECONDARY_OUTPUT_RELOAD_CLASS' to detect them, and provide
1585 ;; patterns `reload_inM' or `reload_outM' to handle them. 1335 ;; patterns `reload_inM' or `reload_outM' to handle them.
1586 1336
1587 ;; The constraints on a `moveM' must permit moving any hard register to any 1337 ;; The constraints on a `moveM' must permit moving any hard register to any
1588 ;; other hard register provided that `HARD_REGNO_MODE_OK' permits mode M in 1338 ;; other hard register provided that `TARGET_HARD_REGNO_MODE_OK' permits
1589 ;; both registers and `REGISTER_MOVE_COST' applied to their classes returns a 1339 ;; mode M in both registers and `REGISTER_MOVE_COST' applied to their
1590 ;; value of 2. 1340 ;; classes returns a value of 2.
1591 1341
1592 ;; It is obligatory to support floating point `moveM' instructions 1342 ;; It is obligatory to support floating point `moveM' instructions
1593 ;; into and out of any registers that can hold fixed point values, 1343 ;; into and out of any registers that can hold fixed point values,
1594 ;; because unions and structures (which have modes `SImode' or 1344 ;; because unions and structures (which have modes `SImode' or
1595 ;; `DImode') can be in those registers and they may have floating 1345 ;; `DImode') can be in those registers and they may have floating
1596 ;; point members. 1346 ;; point members.
1597 1347
1598 ;; There may also be a need to support fixed point `moveM' instructions in and 1348 ;; There may also be a need to support fixed point `moveM' instructions
1599 ;; out of floating point registers. Unfortunately, I have forgotten why this 1349 ;; in and out of floating point registers. Unfortunately, I have
1600 ;; was so, and I don't know whether it is still true. If `HARD_REGNO_MODE_OK' 1350 ;; forgotten why this was so, and I don't know whether it is still true.
1601 ;; rejects fixed point values in floating point registers, then the constraints 1351 ;; If `TARGET_HARD_REGNO_MODE_OK' rejects fixed point values in floating
1602 ;; of the fixed point `moveM' instructions must be designed to avoid ever 1352 ;; point registers, then the constraints of the fixed point `moveM'
1603 ;; trying to reload into a floating point register. 1353 ;; instructions must be designed to avoid ever trying to reload into a
1354 ;; floating point register.
1604 1355
1605 (define_expand "movqi" 1356 (define_expand "movqi"
1606 [(set (match_operand:QI 0 "general_operand" "") 1357 [(set (match_operand:QI 0 "general_operand" "")
1607 (match_operand:QI 1 "general_operand" ""))] 1358 (match_operand:QI 1 "general_operand" ""))]
1608 "" 1359 ""
2118 (set (match_dup 3) (match_dup 5))] 1869 (set (match_dup 3) (match_dup 5))]
2119 " 1870 "
2120 { 1871 {
2121 rtx op0 = operands[0]; 1872 rtx op0 = operands[0];
2122 rtx op1 = operands[1]; 1873 rtx op1 = operands[1];
2123 REAL_VALUE_TYPE rv;
2124 long l[2]; 1874 long l[2];
2125 1875
2126 REAL_VALUE_FROM_CONST_DOUBLE (rv, op1); 1876 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op1), l);
2127 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2128 1877
2129 operands[2] = gen_highpart (SImode, op0); 1878 operands[2] = gen_highpart (SImode, op0);
2130 operands[3] = gen_lowpart (SImode, op0); 1879 operands[3] = gen_lowpart (SImode, op0);
2131 operands[4] = GEN_INT (l[0]); 1880 operands[4] = GEN_INT (l[0]);
2132 operands[5] = GEN_INT (l[1]); 1881 operands[5] = GEN_INT (l[1]);
2243 rtx icc = operands[1]; 1992 rtx icc = operands[1];
2244 rtx icr = operands[2]; 1993 rtx icr = operands[2];
2245 1994
2246 start_sequence (); 1995 start_sequence ();
2247 1996
2248 emit_insn (gen_rtx_SET (VOIDmode, icr, 1997 emit_insn (gen_rtx_SET (icr, gen_rtx_LT (CC_CCRmode, icc, const0_rtx)));
2249 gen_rtx_LT (CC_CCRmode, icc, const0_rtx)));
2250 1998
2251 emit_insn (gen_movsi (dest, const1_rtx)); 1999 emit_insn (gen_movsi (dest, const1_rtx));
2252 2000
2253 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 2001 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2254 gen_rtx_NE (CC_CCRmode, icr, const0_rtx), 2002 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2255 gen_rtx_SET (VOIDmode, dest, 2003 gen_rtx_SET (dest,
2256 gen_rtx_NEG (SImode, dest)))); 2004 gen_rtx_NEG (SImode, dest))));
2257 2005
2258 emit_insn (gen_rtx_SET (VOIDmode, icr, 2006 emit_insn (gen_rtx_SET (icr, gen_rtx_EQ (CC_CCRmode, icc, const0_rtx)));
2259 gen_rtx_EQ (CC_CCRmode, icc, const0_rtx)));
2260 2007
2261 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 2008 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2262 gen_rtx_NE (CC_CCRmode, icr, const0_rtx), 2009 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2263 gen_rtx_SET (VOIDmode, dest, const0_rtx))); 2010 gen_rtx_SET (dest, const0_rtx)));
2264 2011
2265 operands[3] = get_insns (); 2012 operands[3] = get_insns ();
2266 end_sequence (); 2013 end_sequence ();
2267 }") 2014 }")
2268 2015
2311 rtx icc = operands[1]; 2058 rtx icc = operands[1];
2312 rtx icr = operands[2]; 2059 rtx icr = operands[2];
2313 2060
2314 start_sequence (); 2061 start_sequence ();
2315 2062
2316 emit_insn (gen_rtx_SET (VOIDmode, icr, 2063 emit_insn (gen_rtx_SET (icr, gen_rtx_GTU (CC_CCRmode, icc, const0_rtx)));
2317 gen_rtx_GTU (CC_CCRmode, icc, const0_rtx)));
2318 2064
2319 emit_insn (gen_movsi (dest, const1_rtx)); 2065 emit_insn (gen_movsi (dest, const1_rtx));
2320 2066
2321 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 2067 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2322 gen_rtx_NE (CC_CCRmode, icr, const0_rtx), 2068 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2323 gen_addsi3 (dest, dest, dest))); 2069 gen_addsi3 (dest, dest, dest)));
2324 2070
2325 emit_insn (gen_rtx_SET (VOIDmode, icr, 2071 emit_insn (gen_rtx_SET (icr, gen_rtx_LTU (CC_CCRmode, icc, const0_rtx)));
2326 gen_rtx_LTU (CC_CCRmode, icc, const0_rtx)));
2327 2072
2328 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 2073 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2329 gen_rtx_NE (CC_CCRmode, icr, const0_rtx), 2074 gen_rtx_NE (CC_CCRmode, icr, const0_rtx),
2330 gen_rtx_SET (VOIDmode, dest, const0_rtx))); 2075 gen_rtx_SET (dest, const0_rtx)));
2331 2076
2332 operands[3] = get_insns (); 2077 operands[3] = get_insns ();
2333 end_sequence (); 2078 end_sequence ();
2334 }") 2079 }")
2335 2080
2580 emit_move_insn (operands[0], const1_rtx); 2325 emit_move_insn (operands[0], const1_rtx);
2581 emit_insn (gen_rtx_COND_EXEC (VOIDmode, 2326 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
2582 gen_rtx_EQ (CC_CCRmode, 2327 gen_rtx_EQ (CC_CCRmode,
2583 operands[1], 2328 operands[1],
2584 const0_rtx), 2329 const0_rtx),
2585 gen_rtx_SET (VOIDmode, int_op0, 2330 gen_rtx_SET (int_op0, const0_rtx)));
2586 const0_rtx)));
2587 2331
2588 operands[2] = get_insns (); 2332 operands[2] = get_insns ();
2589 end_sequence (); 2333 end_sequence ();
2590 }") 2334 }")
2591 2335
7602 (match_operand:SI 2 "" "") 7346 (match_operand:SI 2 "" "")
7603 (match_operand:SI 3 "" "")] 7347 (match_operand:SI 3 "" "")]
7604 "" 7348 ""
7605 " 7349 "
7606 { 7350 {
7607 rtx insn; 7351 rtx_insn *insn = emit_insn (gen_symGOT2reg_i (operands[0], operands[1],
7608 7352 operands[2], operands[3]));
7609 insn = emit_insn (gen_symGOT2reg_i (operands[0], operands[1], operands[2], operands[3]));
7610 7353
7611 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1; 7354 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7612 7355
7613 set_unique_reg_note (insn, REG_EQUAL, operands[1]); 7356 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7614 7357
7686 (match_operand:SI 2 "" "") 7429 (match_operand:SI 2 "" "")
7687 (match_operand:SI 3 "" "")] 7430 (match_operand:SI 3 "" "")]
7688 "" 7431 ""
7689 " 7432 "
7690 { 7433 {
7691 rtx insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1], operands[2], operands[3])); 7434 rtx_insn *insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1],
7435 operands[2], operands[3]));
7692 7436
7693 set_unique_reg_note (insn, REG_EQUAL, operands[1]); 7437 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7694 7438
7695 DONE; 7439 DONE;
7696 }") 7440 }")
7712 (match_operand:SI 3 "" "") 7456 (match_operand:SI 3 "" "")
7713 (match_dup 4)] 7457 (match_dup 4)]
7714 "" 7458 ""
7715 " 7459 "
7716 { 7460 {
7717 rtx insn;
7718
7719 if (!can_create_pseudo_p ()) 7461 if (!can_create_pseudo_p ())
7720 operands[4] = operands[0]; 7462 operands[4] = operands[0];
7721 else 7463 else
7722 operands[4] = gen_reg_rtx (SImode); 7464 operands[4] = gen_reg_rtx (SImode);
7723 7465
7724 emit_insn (frv_gen_GPsym2reg (operands[4], operands[2])); 7466 emit_insn (frv_gen_GPsym2reg (operands[4], operands[2]));
7725 7467
7726 insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1], 7468 rtx_insn *insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1],
7727 operands[4], operands[3])); 7469 operands[4], operands[3]));
7728 7470
7729 set_unique_reg_note (insn, REG_EQUAL, operands[1]); 7471 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7730 7472
7731 DONE; 7473 DONE;
7732 }") 7474 }")
7738 (match_operand:SI 3 "" "") 7480 (match_operand:SI 3 "" "")
7739 (match_dup 4)] 7481 (match_dup 4)]
7740 "" 7482 ""
7741 " 7483 "
7742 { 7484 {
7743 rtx insn;
7744
7745 if (!can_create_pseudo_p ()) 7485 if (!can_create_pseudo_p ())
7746 { 7486 {
7747 emit_insn (gen_symGOT2reg (operands[0], operands[1], operands[2], 7487 emit_insn (gen_symGOT2reg (operands[0], operands[1], operands[2],
7748 GEN_INT (R_FRV_GOT12))); 7488 GEN_INT (R_FRV_GOT12)));
7749 DONE; 7489 DONE;
7751 7491
7752 operands[4] = gen_reg_rtx (SImode); 7492 operands[4] = gen_reg_rtx (SImode);
7753 7493
7754 emit_insn (frv_gen_GPsym2reg (operands[4], operands[2])); 7494 emit_insn (frv_gen_GPsym2reg (operands[4], operands[2]));
7755 7495
7756 insn = emit_insn (gen_symGOTOFF2reg_hilo (operands[0], operands[1], 7496 rtx_insn *insn = emit_insn (gen_symGOTOFF2reg_hilo (operands[0], operands[1],
7757 operands[4], operands[3])); 7497 operands[4], operands[3]));
7758 7498
7759 set_unique_reg_note (insn, REG_EQUAL, operands[1]); 7499 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7760 7500
7761 DONE; 7501 DONE;
7762 }") 7502 }")