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comparison gcc/config/i386/core2.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 561a7518be6b
children 84e7813d76e9
comparison
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68:561a7518be6b 111:04ced10e8804
1 ;; Scheduling for Core 2 and derived processors. 1 ;; Scheduling for Core 2 and derived processors.
2 ;; Copyright (C) 2004, 2005, 2007, 2008, 2010 Free Software Foundation, Inc. 2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify 6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by 7 ;; it under the terms of the GNU General Public License as published by
34 ;; The CPU domain, used for Core i7 bypass latencies 34 ;; The CPU domain, used for Core i7 bypass latencies
35 (define_attr "i7_domain" "int,float,simd" 35 (define_attr "i7_domain" "int,float,simd"
36 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint") 36 (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint")
37 (const_string "float") 37 (const_string "float")
38 (eq_attr "type" "sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul, 38 (eq_attr "type" "sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul,
39 sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt, 39 sse,ssemov,sseadd,sseadd1,ssemul,ssecmp,ssecomi,ssecvt,
40 ssecvt1,sseicvt,ssediv,sseins,ssemuladd,sse4arg") 40 ssecvt1,sseicvt,ssediv,sseins,ssemuladd,sse4arg")
41 (cond [(eq_attr "mode" "V4DF,V8SF,V2DF,V4SF,SF,DF") 41 (cond [(eq_attr "mode" "V4DF,V8SF,V2DF,V4SF,SF,DF")
42 (const_string "float") 42 (const_string "float")
43 (eq_attr "mode" "SI") 43 (eq_attr "mode" "SI")
44 (const_string "int")] 44 (const_string "int")]
100 ;; doesn't make sense because we don't know how these instructions are 100 ;; doesn't make sense because we don't know how these instructions are
101 ;; executed in the core. So we just model that they can only be decoded 101 ;; executed in the core. So we just model that they can only be decoded
102 ;; on decoder 0, and say that it takes a little while before the result 102 ;; on decoder 0, and say that it takes a little while before the result
103 ;; is available. 103 ;; is available.
104 (define_insn_reservation "c2_complex_insn" 6 104 (define_insn_reservation "c2_complex_insn" 6
105 (and (eq_attr "cpu" "core2,corei7") 105 (and (eq_attr "cpu" "core2,nehalem")
106 (eq_attr "type" "other,multi,str")) 106 (eq_attr "type" "other,multi,str"))
107 "c2_decoder0") 107 "c2_decoder0")
108 108
109 (define_insn_reservation "c2_call" 1 109 (define_insn_reservation "c2_call" 1
110 (and (eq_attr "cpu" "core2,corei7") 110 (and (eq_attr "cpu" "core2,nehalem")
111 (eq_attr "type" "call,callv")) 111 (eq_attr "type" "call,callv"))
112 "c2_decoder0") 112 "c2_decoder0")
113 113
114 ;; imov with memory operands does not use the integer units. 114 ;; imov with memory operands does not use the integer units.
115 ;; imovx always decodes to one uop, and also doesn't use the integer 115 ;; imovx always decodes to one uop, and also doesn't use the integer
116 ;; units if it has memory operands. 116 ;; units if it has memory operands.
117 (define_insn_reservation "c2_imov" 1 117 (define_insn_reservation "c2_imov" 1
118 (and (eq_attr "cpu" "core2,corei7") 118 (and (eq_attr "cpu" "core2,nehalem")
119 (and (eq_attr "memory" "none") 119 (and (eq_attr "memory" "none")
120 (eq_attr "type" "imov,imovx"))) 120 (eq_attr "type" "imov,imovx")))
121 "c2_decodern,(c2_p0|c2_p1|c2_p5)") 121 "c2_decodern,(c2_p0|c2_p1|c2_p5)")
122 122
123 (define_insn_reservation "c2_imov_load" 4 123 (define_insn_reservation "c2_imov_load" 4
124 (and (eq_attr "cpu" "core2,corei7") 124 (and (eq_attr "cpu" "core2,nehalem")
125 (and (eq_attr "memory" "load") 125 (and (eq_attr "memory" "load")
126 (eq_attr "type" "imov,imovx"))) 126 (eq_attr "type" "imov,imovx")))
127 "c2_decodern,c2_p2") 127 "c2_decodern,c2_p2")
128 128
129 (define_insn_reservation "c2_imov_store" 1 129 (define_insn_reservation "c2_imov_store" 1
130 (and (eq_attr "cpu" "core2,corei7") 130 (and (eq_attr "cpu" "core2,nehalem")
131 (and (eq_attr "memory" "store") 131 (and (eq_attr "memory" "store")
132 (eq_attr "type" "imov"))) 132 (eq_attr "type" "imov")))
133 "c2_decodern,c2_p4+c2_p3") 133 "c2_decodern,c2_p4+c2_p3")
134 134
135 (define_insn_reservation "c2_icmov" 2 135 (define_insn_reservation "c2_icmov" 2
136 (and (eq_attr "cpu" "core2,corei7") 136 (and (eq_attr "cpu" "core2,nehalem")
137 (and (eq_attr "memory" "none") 137 (and (eq_attr "memory" "none")
138 (eq_attr "type" "icmov"))) 138 (eq_attr "type" "icmov")))
139 "c2_decoder0,(c2_p0|c2_p1|c2_p5)*2") 139 "c2_decoder0,(c2_p0|c2_p1|c2_p5)*2")
140 140
141 (define_insn_reservation "c2_icmov_load" 2 141 (define_insn_reservation "c2_icmov_load" 2
142 (and (eq_attr "cpu" "core2,corei7") 142 (and (eq_attr "cpu" "core2,nehalem")
143 (and (eq_attr "memory" "load") 143 (and (eq_attr "memory" "load")
144 (eq_attr "type" "icmov"))) 144 (eq_attr "type" "icmov")))
145 "c2_decoder0,c2_p2,(c2_p0|c2_p1|c2_p5)*2") 145 "c2_decoder0,c2_p2,(c2_p0|c2_p1|c2_p5)*2")
146 146
147 (define_insn_reservation "c2_push_reg" 1 147 (define_insn_reservation "c2_push_reg" 1
148 (and (eq_attr "cpu" "core2,corei7") 148 (and (eq_attr "cpu" "core2,nehalem")
149 (and (eq_attr "memory" "store") 149 (and (eq_attr "memory" "store")
150 (eq_attr "type" "push"))) 150 (eq_attr "type" "push")))
151 "c2_decodern,c2_p4+c2_p3") 151 "c2_decodern,c2_p4+c2_p3")
152 152
153 (define_insn_reservation "c2_push_mem" 1 153 (define_insn_reservation "c2_push_mem" 1
154 (and (eq_attr "cpu" "core2,corei7") 154 (and (eq_attr "cpu" "core2,nehalem")
155 (and (eq_attr "memory" "both") 155 (and (eq_attr "memory" "both")
156 (eq_attr "type" "push"))) 156 (eq_attr "type" "push")))
157 "c2_decoder0,c2_p2,c2_p4+c2_p3") 157 "c2_decoder0,c2_p2,c2_p4+c2_p3")
158 158
159 ;; lea executes on port 0 with latency one and throughput 1. 159 ;; lea executes on port 0 with latency one and throughput 1.
160 (define_insn_reservation "c2_lea" 1 160 (define_insn_reservation "c2_lea" 1
161 (and (eq_attr "cpu" "core2,corei7") 161 (and (eq_attr "cpu" "core2,nehalem")
162 (and (eq_attr "memory" "none") 162 (and (eq_attr "memory" "none")
163 (eq_attr "type" "lea"))) 163 (eq_attr "type" "lea")))
164 "c2_decodern,c2_p0") 164 "c2_decodern,c2_p0")
165 165
166 ;; Shift and rotate decode as two uops which can go to port 0 or 5. 166 ;; Shift and rotate decode as two uops which can go to port 0 or 5.
167 ;; The load and store units need to be reserved when memory operands 167 ;; The load and store units need to be reserved when memory operands
168 ;; are involved. 168 ;; are involved.
169 (define_insn_reservation "c2_shift_rotate" 1 169 (define_insn_reservation "c2_shift_rotate" 1
170 (and (eq_attr "cpu" "core2,corei7") 170 (and (eq_attr "cpu" "core2,nehalem")
171 (and (eq_attr "memory" "none") 171 (and (eq_attr "memory" "none")
172 (eq_attr "type" "ishift,ishift1,rotate,rotate1"))) 172 (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
173 "c2_decodern,(c2_p0|c2_p5)") 173 "c2_decodern,(c2_p0|c2_p5)")
174 174
175 (define_insn_reservation "c2_shift_rotate_mem" 4 175 (define_insn_reservation "c2_shift_rotate_mem" 4
176 (and (eq_attr "cpu" "core2,corei7") 176 (and (eq_attr "cpu" "core2,nehalem")
177 (and (eq_attr "memory" "!none") 177 (and (eq_attr "memory" "!none")
178 (eq_attr "type" "ishift,ishift1,rotate,rotate1"))) 178 (eq_attr "type" "ishift,ishift1,rotate,rotate1")))
179 "c2_decoder0,c2_p2,(c2_p0|c2_p5),c2_p4+c2_p3") 179 "c2_decoder0,c2_p2,(c2_p0|c2_p5),c2_p4+c2_p3")
180 180
181 ;; See comments in ppro.md for the corresponding reservation. 181 ;; See comments in ppro.md for the corresponding reservation.
182 (define_insn_reservation "c2_branch" 1 182 (define_insn_reservation "c2_branch" 1
183 (and (eq_attr "cpu" "core2,corei7") 183 (and (eq_attr "cpu" "core2,nehalem")
184 (and (eq_attr "memory" "none") 184 (and (eq_attr "memory" "none")
185 (eq_attr "type" "ibr"))) 185 (eq_attr "type" "ibr")))
186 "c2_decodern,c2_p5") 186 "c2_decodern,c2_p5")
187 187
188 ;; ??? Indirect branches probably have worse latency than this. 188 ;; ??? Indirect branches probably have worse latency than this.
189 (define_insn_reservation "c2_indirect_branch" 6 189 (define_insn_reservation "c2_indirect_branch" 6
190 (and (eq_attr "cpu" "core2,corei7") 190 (and (eq_attr "cpu" "core2,nehalem")
191 (and (eq_attr "memory" "!none") 191 (and (eq_attr "memory" "!none")
192 (eq_attr "type" "ibr"))) 192 (eq_attr "type" "ibr")))
193 "c2_decoder0,c2_p2+c2_p5") 193 "c2_decoder0,c2_p2+c2_p5")
194 194
195 (define_insn_reservation "c2_leave" 4 195 (define_insn_reservation "c2_leave" 4
196 (and (eq_attr "cpu" "core2,corei7") 196 (and (eq_attr "cpu" "core2,nehalem")
197 (eq_attr "type" "leave")) 197 (eq_attr "type" "leave"))
198 "c2_decoder0,c2_p2+(c2_p0|c2_p1),(c2_p0|c2_p1)") 198 "c2_decoder0,c2_p2+(c2_p0|c2_p1),(c2_p0|c2_p1)")
199 199
200 ;; mul and imul with two/three operands only execute on port 1 for HImode 200 ;; mul and imul with two/three operands only execute on port 1 for HImode
201 ;; and SImode, port 0 for DImode. 201 ;; and SImode, port 0 for DImode.
202 (define_insn_reservation "c2_imul_hisi" 3 202 (define_insn_reservation "c2_imul_hisi" 3
203 (and (eq_attr "cpu" "core2,corei7") 203 (and (eq_attr "cpu" "core2,nehalem")
204 (and (eq_attr "memory" "none") 204 (and (eq_attr "memory" "none")
205 (and (eq_attr "mode" "HI,SI") 205 (and (eq_attr "mode" "HI,SI")
206 (eq_attr "type" "imul")))) 206 (eq_attr "type" "imul"))))
207 "c2_decodern,c2_p1") 207 "c2_decodern,c2_p1")
208 208
209 (define_insn_reservation "c2_imul_hisi_mem" 3 209 (define_insn_reservation "c2_imul_hisi_mem" 3
210 (and (eq_attr "cpu" "core2,corei7") 210 (and (eq_attr "cpu" "core2,nehalem")
211 (and (eq_attr "memory" "!none") 211 (and (eq_attr "memory" "!none")
212 (and (eq_attr "mode" "HI,SI") 212 (and (eq_attr "mode" "HI,SI")
213 (eq_attr "type" "imul")))) 213 (eq_attr "type" "imul"))))
214 "c2_decoder0,c2_p2+c2_p1") 214 "c2_decoder0,c2_p2+c2_p1")
215 215
216 (define_insn_reservation "c2_imul_di" 5 216 (define_insn_reservation "c2_imul_di" 5
217 (and (eq_attr "cpu" "core2,corei7") 217 (and (eq_attr "cpu" "core2,nehalem")
218 (and (eq_attr "memory" "none") 218 (and (eq_attr "memory" "none")
219 (and (eq_attr "mode" "DI") 219 (and (eq_attr "mode" "DI")
220 (eq_attr "type" "imul")))) 220 (eq_attr "type" "imul"))))
221 "c2_decodern,c2_p0") 221 "c2_decodern,c2_p0")
222 222
223 (define_insn_reservation "c2_imul_di_mem" 5 223 (define_insn_reservation "c2_imul_di_mem" 5
224 (and (eq_attr "cpu" "core2,corei7") 224 (and (eq_attr "cpu" "core2,nehalem")
225 (and (eq_attr "memory" "!none") 225 (and (eq_attr "memory" "!none")
226 (and (eq_attr "mode" "DI") 226 (and (eq_attr "mode" "DI")
227 (eq_attr "type" "imul")))) 227 (eq_attr "type" "imul"))))
228 "c2_decoder0,c2_p2+c2_p0") 228 "c2_decoder0,c2_p2+c2_p0")
229 229
230 ;; div and idiv are very similar, so we model them the same. 230 ;; div and idiv are very similar, so we model them the same.
231 ;; QI, HI, and SI have issue latency 12, 21, and 37, respectively. 231 ;; QI, HI, and SI have issue latency 12, 21, and 37, respectively.
232 ;; These issue latencies are modelled via the c2_div automaton. 232 ;; These issue latencies are modelled via the c2_div automaton.
233 (define_insn_reservation "c2_idiv_QI" 19 233 (define_insn_reservation "c2_idiv_QI" 19
234 (and (eq_attr "cpu" "core2,corei7") 234 (and (eq_attr "cpu" "core2,nehalem")
235 (and (eq_attr "memory" "none") 235 (and (eq_attr "memory" "none")
236 (and (eq_attr "mode" "QI") 236 (and (eq_attr "mode" "QI")
237 (eq_attr "type" "idiv")))) 237 (eq_attr "type" "idiv"))))
238 "c2_decoder0,(c2_p0+c2_idiv)*2,(c2_p0|c2_p1)+c2_idiv,c2_idiv*9") 238 "c2_decoder0,(c2_p0+c2_idiv)*2,(c2_p0|c2_p1)+c2_idiv,c2_idiv*9")
239 239
240 (define_insn_reservation "c2_idiv_QI_load" 19 240 (define_insn_reservation "c2_idiv_QI_load" 19
241 (and (eq_attr "cpu" "core2,corei7") 241 (and (eq_attr "cpu" "core2,nehalem")
242 (and (eq_attr "memory" "load") 242 (and (eq_attr "memory" "load")
243 (and (eq_attr "mode" "QI") 243 (and (eq_attr "mode" "QI")
244 (eq_attr "type" "idiv")))) 244 (eq_attr "type" "idiv"))))
245 "c2_decoder0,c2_p2+c2_p0+c2_idiv,c2_p0+c2_idiv,(c2_p0|c2_p1)+c2_idiv,c2_idiv*9") 245 "c2_decoder0,c2_p2+c2_p0+c2_idiv,c2_p0+c2_idiv,(c2_p0|c2_p1)+c2_idiv,c2_idiv*9")
246 246
247 (define_insn_reservation "c2_idiv_HI" 23 247 (define_insn_reservation "c2_idiv_HI" 23
248 (and (eq_attr "cpu" "core2,corei7") 248 (and (eq_attr "cpu" "core2,nehalem")
249 (and (eq_attr "memory" "none") 249 (and (eq_attr "memory" "none")
250 (and (eq_attr "mode" "HI") 250 (and (eq_attr "mode" "HI")
251 (eq_attr "type" "idiv")))) 251 (eq_attr "type" "idiv"))))
252 "c2_decoder0,(c2_p0+c2_idiv)*3,(c2_p0|c2_p1)+c2_idiv,c2_idiv*17") 252 "c2_decoder0,(c2_p0+c2_idiv)*3,(c2_p0|c2_p1)+c2_idiv,c2_idiv*17")
253 253
254 (define_insn_reservation "c2_idiv_HI_load" 23 254 (define_insn_reservation "c2_idiv_HI_load" 23
255 (and (eq_attr "cpu" "core2,corei7") 255 (and (eq_attr "cpu" "core2,nehalem")
256 (and (eq_attr "memory" "load") 256 (and (eq_attr "memory" "load")
257 (and (eq_attr "mode" "HI") 257 (and (eq_attr "mode" "HI")
258 (eq_attr "type" "idiv")))) 258 (eq_attr "type" "idiv"))))
259 "c2_decoder0,c2_p2+c2_p0+c2_idiv,c2_p0+c2_idiv,(c2_p0|c2_p1)+c2_idiv,c2_idiv*18") 259 "c2_decoder0,c2_p2+c2_p0+c2_idiv,c2_p0+c2_idiv,(c2_p0|c2_p1)+c2_idiv,c2_idiv*18")
260 260
261 (define_insn_reservation "c2_idiv_SI" 39 261 (define_insn_reservation "c2_idiv_SI" 39
262 (and (eq_attr "cpu" "core2,corei7") 262 (and (eq_attr "cpu" "core2,nehalem")
263 (and (eq_attr "memory" "none") 263 (and (eq_attr "memory" "none")
264 (and (eq_attr "mode" "SI") 264 (and (eq_attr "mode" "SI")
265 (eq_attr "type" "idiv")))) 265 (eq_attr "type" "idiv"))))
266 "c2_decoder0,(c2_p0+c2_idiv)*3,(c2_p0|c2_p1)+c2_idiv,c2_idiv*33") 266 "c2_decoder0,(c2_p0+c2_idiv)*3,(c2_p0|c2_p1)+c2_idiv,c2_idiv*33")
267 267
268 (define_insn_reservation "c2_idiv_SI_load" 39 268 (define_insn_reservation "c2_idiv_SI_load" 39
269 (and (eq_attr "cpu" "core2,corei7") 269 (and (eq_attr "cpu" "core2,nehalem")
270 (and (eq_attr "memory" "load") 270 (and (eq_attr "memory" "load")
271 (and (eq_attr "mode" "SI") 271 (and (eq_attr "mode" "SI")
272 (eq_attr "type" "idiv")))) 272 (eq_attr "type" "idiv"))))
273 "c2_decoder0,c2_p2+c2_p0+c2_idiv,c2_p0+c2_idiv,(c2_p0|c2_p1)+c2_idiv,c2_idiv*34") 273 "c2_decoder0,c2_p2+c2_p0+c2_idiv,c2_p0+c2_idiv,(c2_p0|c2_p1)+c2_idiv,c2_idiv*34")
274 274
275 ;; x87 floating point operations. 275 ;; x87 floating point operations.
276 276
277 (define_insn_reservation "c2_fxch" 0 277 (define_insn_reservation "c2_fxch" 0
278 (and (eq_attr "cpu" "core2,corei7") 278 (and (eq_attr "cpu" "core2,nehalem")
279 (eq_attr "type" "fxch")) 279 (eq_attr "type" "fxch"))
280 "c2_decodern") 280 "c2_decodern")
281 281
282 (define_insn_reservation "c2_fop" 3 282 (define_insn_reservation "c2_fop" 3
283 (and (eq_attr "cpu" "core2,corei7") 283 (and (eq_attr "cpu" "core2,nehalem")
284 (and (eq_attr "memory" "none,unknown") 284 (and (eq_attr "memory" "none,unknown")
285 (eq_attr "type" "fop"))) 285 (eq_attr "type" "fop")))
286 "c2_decodern,c2_p1") 286 "c2_decodern,c2_p1")
287 287
288 (define_insn_reservation "c2_fop_load" 5 288 (define_insn_reservation "c2_fop_load" 5
289 (and (eq_attr "cpu" "core2,corei7") 289 (and (eq_attr "cpu" "core2,nehalem")
290 (and (eq_attr "memory" "load") 290 (and (eq_attr "memory" "load")
291 (eq_attr "type" "fop"))) 291 (eq_attr "type" "fop")))
292 "c2_decoder0,c2_p2+c2_p1,c2_p1") 292 "c2_decoder0,c2_p2+c2_p1,c2_p1")
293 293
294 (define_insn_reservation "c2_fop_store" 3 294 (define_insn_reservation "c2_fop_store" 3
295 (and (eq_attr "cpu" "core2,corei7") 295 (and (eq_attr "cpu" "core2,nehalem")
296 (and (eq_attr "memory" "store") 296 (and (eq_attr "memory" "store")
297 (eq_attr "type" "fop"))) 297 (eq_attr "type" "fop")))
298 "c2_decoder0,c2_p0,c2_p0,c2_p0+c2_p4+c2_p3") 298 "c2_decoder0,c2_p0,c2_p0,c2_p0+c2_p4+c2_p3")
299 299
300 (define_insn_reservation "c2_fop_both" 5 300 (define_insn_reservation "c2_fop_both" 5
301 (and (eq_attr "cpu" "core2,corei7") 301 (and (eq_attr "cpu" "core2,nehalem")
302 (and (eq_attr "memory" "both") 302 (and (eq_attr "memory" "both")
303 (eq_attr "type" "fop"))) 303 (eq_attr "type" "fop")))
304 "c2_decoder0,c2_p2+c2_p0,c2_p0+c2_p4+c2_p3") 304 "c2_decoder0,c2_p2+c2_p0,c2_p0+c2_p4+c2_p3")
305 305
306 (define_insn_reservation "c2_fsgn" 1 306 (define_insn_reservation "c2_fsgn" 1
307 (and (eq_attr "cpu" "core2,corei7") 307 (and (eq_attr "cpu" "core2,nehalem")
308 (eq_attr "type" "fsgn")) 308 (eq_attr "type" "fsgn"))
309 "c2_decodern,c2_p0") 309 "c2_decodern,c2_p0")
310 310
311 (define_insn_reservation "c2_fistp" 5 311 (define_insn_reservation "c2_fistp" 5
312 (and (eq_attr "cpu" "core2,corei7") 312 (and (eq_attr "cpu" "core2,nehalem")
313 (eq_attr "type" "fistp")) 313 (eq_attr "type" "fistp"))
314 "c2_decoder0,c2_p0*2,c2_p4+c2_p3") 314 "c2_decoder0,c2_p0*2,c2_p4+c2_p3")
315 315
316 (define_insn_reservation "c2_fcmov" 2 316 (define_insn_reservation "c2_fcmov" 2
317 (and (eq_attr "cpu" "core2,corei7") 317 (and (eq_attr "cpu" "core2,nehalem")
318 (eq_attr "type" "fcmov")) 318 (eq_attr "type" "fcmov"))
319 "c2_decoder0,c2_p0*2") 319 "c2_decoder0,c2_p0*2")
320 320
321 (define_insn_reservation "c2_fcmp" 1 321 (define_insn_reservation "c2_fcmp" 1
322 (and (eq_attr "cpu" "core2,corei7") 322 (and (eq_attr "cpu" "core2,nehalem")
323 (and (eq_attr "memory" "none") 323 (and (eq_attr "memory" "none")
324 (eq_attr "type" "fcmp"))) 324 (eq_attr "type" "fcmp")))
325 "c2_decodern,c2_p1") 325 "c2_decodern,c2_p1")
326 326
327 (define_insn_reservation "c2_fcmp_load" 4 327 (define_insn_reservation "c2_fcmp_load" 4
328 (and (eq_attr "cpu" "core2,corei7") 328 (and (eq_attr "cpu" "core2,nehalem")
329 (and (eq_attr "memory" "load") 329 (and (eq_attr "memory" "load")
330 (eq_attr "type" "fcmp"))) 330 (eq_attr "type" "fcmp")))
331 "c2_decoder0,c2_p2+c2_p1") 331 "c2_decoder0,c2_p2+c2_p1")
332 332
333 (define_insn_reservation "c2_fmov" 1 333 (define_insn_reservation "c2_fmov" 1
334 (and (eq_attr "cpu" "core2,corei7") 334 (and (eq_attr "cpu" "core2,nehalem")
335 (and (eq_attr "memory" "none") 335 (and (eq_attr "memory" "none")
336 (eq_attr "type" "fmov"))) 336 (eq_attr "type" "fmov")))
337 "c2_decodern,c2_p0") 337 "c2_decodern,c2_p0")
338 338
339 (define_insn_reservation "c2_fmov_load" 1 339 (define_insn_reservation "c2_fmov_load" 1
340 (and (eq_attr "cpu" "core2,corei7") 340 (and (eq_attr "cpu" "core2,nehalem")
341 (and (eq_attr "memory" "load") 341 (and (eq_attr "memory" "load")
342 (and (eq_attr "mode" "!XF") 342 (and (eq_attr "mode" "!XF")
343 (eq_attr "type" "fmov")))) 343 (eq_attr "type" "fmov"))))
344 "c2_decodern,c2_p2") 344 "c2_decodern,c2_p2")
345 345
346 (define_insn_reservation "c2_fmov_XF_load" 3 346 (define_insn_reservation "c2_fmov_XF_load" 3
347 (and (eq_attr "cpu" "core2,corei7") 347 (and (eq_attr "cpu" "core2,nehalem")
348 (and (eq_attr "memory" "load") 348 (and (eq_attr "memory" "load")
349 (and (eq_attr "mode" "XF") 349 (and (eq_attr "mode" "XF")
350 (eq_attr "type" "fmov")))) 350 (eq_attr "type" "fmov"))))
351 "c2_decoder0,(c2_p2+c2_p0)*2") 351 "c2_decoder0,(c2_p2+c2_p0)*2")
352 352
353 (define_insn_reservation "c2_fmov_store" 1 353 (define_insn_reservation "c2_fmov_store" 1
354 (and (eq_attr "cpu" "core2,corei7") 354 (and (eq_attr "cpu" "core2,nehalem")
355 (and (eq_attr "memory" "store") 355 (and (eq_attr "memory" "store")
356 (and (eq_attr "mode" "!XF") 356 (and (eq_attr "mode" "!XF")
357 (eq_attr "type" "fmov")))) 357 (eq_attr "type" "fmov"))))
358 "c2_decodern,c2_p3+c2_p4") 358 "c2_decodern,c2_p3+c2_p4")
359 359
360 (define_insn_reservation "c2_fmov_XF_store" 3 360 (define_insn_reservation "c2_fmov_XF_store" 3
361 (and (eq_attr "cpu" "core2,corei7") 361 (and (eq_attr "cpu" "core2,nehalem")
362 (and (eq_attr "memory" "store") 362 (and (eq_attr "memory" "store")
363 (and (eq_attr "mode" "XF") 363 (and (eq_attr "mode" "XF")
364 (eq_attr "type" "fmov")))) 364 (eq_attr "type" "fmov"))))
365 "c2_decoder0,(c2_p3+c2_p4),(c2_p3+c2_p4)") 365 "c2_decoder0,(c2_p3+c2_p4),(c2_p3+c2_p4)")
366 366
367 ;; fmul executes on port 0 with latency 5. It has issue latency 2, 367 ;; fmul executes on port 0 with latency 5. It has issue latency 2,
368 ;; but we don't model this. 368 ;; but we don't model this.
369 (define_insn_reservation "c2_fmul" 5 369 (define_insn_reservation "c2_fmul" 5
370 (and (eq_attr "cpu" "core2,corei7") 370 (and (eq_attr "cpu" "core2,nehalem")
371 (and (eq_attr "memory" "none") 371 (and (eq_attr "memory" "none")
372 (eq_attr "type" "fmul"))) 372 (eq_attr "type" "fmul")))
373 "c2_decoder0,c2_p0*2") 373 "c2_decoder0,c2_p0*2")
374 374
375 (define_insn_reservation "c2_fmul_load" 6 375 (define_insn_reservation "c2_fmul_load" 6
376 (and (eq_attr "cpu" "core2,corei7") 376 (and (eq_attr "cpu" "core2,nehalem")
377 (and (eq_attr "memory" "load") 377 (and (eq_attr "memory" "load")
378 (eq_attr "type" "fmul"))) 378 (eq_attr "type" "fmul")))
379 "c2_decoder0,c2_p2+c2_p0,c2_p0") 379 "c2_decoder0,c2_p2+c2_p0,c2_p0")
380 380
381 ;; fdiv latencies depend on the mode of the operands. XFmode gives 381 ;; fdiv latencies depend on the mode of the operands. XFmode gives
382 ;; a latency of 38 cycles, DFmode gives 32, and SFmode gives latency 18. 382 ;; a latency of 38 cycles, DFmode gives 32, and SFmode gives latency 18.
383 ;; Division by a power of 2 takes only 9 cycles, but we cannot model 383 ;; Division by a power of 2 takes only 9 cycles, but we cannot model
384 ;; that. Throughput is equal to latency - 1, which we model using the 384 ;; that. Throughput is equal to latency - 1, which we model using the
385 ;; c2_div automaton. 385 ;; c2_div automaton.
386 (define_insn_reservation "c2_fdiv_SF" 18 386 (define_insn_reservation "c2_fdiv_SF" 18
387 (and (eq_attr "cpu" "core2,corei7") 387 (and (eq_attr "cpu" "core2,nehalem")
388 (and (eq_attr "memory" "none") 388 (and (eq_attr "memory" "none")
389 (and (eq_attr "mode" "SF") 389 (and (eq_attr "mode" "SF")
390 (eq_attr "type" "fdiv,fpspc")))) 390 (eq_attr "type" "fdiv,fpspc"))))
391 "c2_decodern,c2_p0+c2_fdiv,c2_fdiv*16") 391 "c2_decodern,c2_p0+c2_fdiv,c2_fdiv*16")
392 392
393 (define_insn_reservation "c2_fdiv_SF_load" 19 393 (define_insn_reservation "c2_fdiv_SF_load" 19
394 (and (eq_attr "cpu" "core2,corei7") 394 (and (eq_attr "cpu" "core2,nehalem")
395 (and (eq_attr "memory" "load") 395 (and (eq_attr "memory" "load")
396 (and (eq_attr "mode" "SF") 396 (and (eq_attr "mode" "SF")
397 (eq_attr "type" "fdiv,fpspc")))) 397 (eq_attr "type" "fdiv,fpspc"))))
398 "c2_decoder0,c2_p2+c2_p0+c2_fdiv,c2_fdiv*16") 398 "c2_decoder0,c2_p2+c2_p0+c2_fdiv,c2_fdiv*16")
399 399
400 (define_insn_reservation "c2_fdiv_DF" 32 400 (define_insn_reservation "c2_fdiv_DF" 32
401 (and (eq_attr "cpu" "core2,corei7") 401 (and (eq_attr "cpu" "core2,nehalem")
402 (and (eq_attr "memory" "none") 402 (and (eq_attr "memory" "none")
403 (and (eq_attr "mode" "DF") 403 (and (eq_attr "mode" "DF")
404 (eq_attr "type" "fdiv,fpspc")))) 404 (eq_attr "type" "fdiv,fpspc"))))
405 "c2_decodern,c2_p0+c2_fdiv,c2_fdiv*30") 405 "c2_decodern,c2_p0+c2_fdiv,c2_fdiv*30")
406 406
407 (define_insn_reservation "c2_fdiv_DF_load" 33 407 (define_insn_reservation "c2_fdiv_DF_load" 33
408 (and (eq_attr "cpu" "core2,corei7") 408 (and (eq_attr "cpu" "core2,nehalem")
409 (and (eq_attr "memory" "load") 409 (and (eq_attr "memory" "load")
410 (and (eq_attr "mode" "DF") 410 (and (eq_attr "mode" "DF")
411 (eq_attr "type" "fdiv,fpspc")))) 411 (eq_attr "type" "fdiv,fpspc"))))
412 "c2_decoder0,c2_p2+c2_p0+c2_fdiv,c2_fdiv*30") 412 "c2_decoder0,c2_p2+c2_p0+c2_fdiv,c2_fdiv*30")
413 413
414 (define_insn_reservation "c2_fdiv_XF" 38 414 (define_insn_reservation "c2_fdiv_XF" 38
415 (and (eq_attr "cpu" "core2,corei7") 415 (and (eq_attr "cpu" "core2,nehalem")
416 (and (eq_attr "memory" "none") 416 (and (eq_attr "memory" "none")
417 (and (eq_attr "mode" "XF") 417 (and (eq_attr "mode" "XF")
418 (eq_attr "type" "fdiv,fpspc")))) 418 (eq_attr "type" "fdiv,fpspc"))))
419 "c2_decodern,c2_p0+c2_fdiv,c2_fdiv*36") 419 "c2_decodern,c2_p0+c2_fdiv,c2_fdiv*36")
420 420
421 (define_insn_reservation "c2_fdiv_XF_load" 39 421 (define_insn_reservation "c2_fdiv_XF_load" 39
422 (and (eq_attr "cpu" "core2,corei7") 422 (and (eq_attr "cpu" "core2,nehalem")
423 (and (eq_attr "memory" "load") 423 (and (eq_attr "memory" "load")
424 (and (eq_attr "mode" "XF") 424 (and (eq_attr "mode" "XF")
425 (eq_attr "type" "fdiv,fpspc")))) 425 (eq_attr "type" "fdiv,fpspc"))))
426 "c2_decoder0,c2_p2+c2_p0+c2_fdiv,c2_fdiv*36") 426 "c2_decoder0,c2_p2+c2_p0+c2_fdiv,c2_fdiv*36")
427 427
428 ;; MMX instructions. 428 ;; MMX instructions.
429 429
430 (define_insn_reservation "c2_mmx_add" 1 430 (define_insn_reservation "c2_mmx_add" 1
431 (and (eq_attr "cpu" "core2,corei7") 431 (and (eq_attr "cpu" "core2,nehalem")
432 (and (eq_attr "memory" "none") 432 (and (eq_attr "memory" "none")
433 (eq_attr "type" "mmxadd,sseiadd"))) 433 (eq_attr "type" "mmxadd,sseiadd")))
434 "c2_decodern,c2_p0|c2_p5") 434 "c2_decodern,c2_p0|c2_p5")
435 435
436 (define_insn_reservation "c2_mmx_add_load" 2 436 (define_insn_reservation "c2_mmx_add_load" 2
437 (and (eq_attr "cpu" "core2,corei7") 437 (and (eq_attr "cpu" "core2,nehalem")
438 (and (eq_attr "memory" "load") 438 (and (eq_attr "memory" "load")
439 (eq_attr "type" "mmxadd,sseiadd"))) 439 (eq_attr "type" "mmxadd,sseiadd")))
440 "c2_decodern,c2_p2+c2_p0|c2_p5") 440 "c2_decodern,c2_p2+c2_p0|c2_p5")
441 441
442 (define_insn_reservation "c2_mmx_shft" 1 442 (define_insn_reservation "c2_mmx_shft" 1
443 (and (eq_attr "cpu" "core2,corei7") 443 (and (eq_attr "cpu" "core2,nehalem")
444 (and (eq_attr "memory" "none") 444 (and (eq_attr "memory" "none")
445 (eq_attr "type" "mmxshft"))) 445 (eq_attr "type" "mmxshft")))
446 "c2_decodern,c2_p0|c2_p5") 446 "c2_decodern,c2_p0|c2_p5")
447 447
448 (define_insn_reservation "c2_mmx_shft_load" 2 448 (define_insn_reservation "c2_mmx_shft_load" 2
449 (and (eq_attr "cpu" "core2,corei7") 449 (and (eq_attr "cpu" "core2,nehalem")
450 (and (eq_attr "memory" "load") 450 (and (eq_attr "memory" "load")
451 (eq_attr "type" "mmxshft"))) 451 (eq_attr "type" "mmxshft")))
452 "c2_decoder0,c2_p2+c2_p1") 452 "c2_decoder0,c2_p2+c2_p1")
453 453
454 (define_insn_reservation "c2_mmx_sse_shft" 1 454 (define_insn_reservation "c2_mmx_sse_shft" 1
455 (and (eq_attr "cpu" "core2,corei7") 455 (and (eq_attr "cpu" "core2,nehalem")
456 (and (eq_attr "memory" "none") 456 (and (eq_attr "memory" "none")
457 (and (eq_attr "type" "sseishft") 457 (and (eq_attr "type" "sseishft")
458 (eq_attr "length_immediate" "!0")))) 458 (eq_attr "length_immediate" "!0"))))
459 "c2_decodern,c2_p1") 459 "c2_decodern,c2_p1")
460 460
461 (define_insn_reservation "c2_mmx_sse_shft_load" 2 461 (define_insn_reservation "c2_mmx_sse_shft_load" 2
462 (and (eq_attr "cpu" "core2,corei7") 462 (and (eq_attr "cpu" "core2,nehalem")
463 (and (eq_attr "memory" "load") 463 (and (eq_attr "memory" "load")
464 (and (eq_attr "type" "sseishft") 464 (and (eq_attr "type" "sseishft")
465 (eq_attr "length_immediate" "!0")))) 465 (eq_attr "length_immediate" "!0"))))
466 "c2_decodern,c2_p1") 466 "c2_decodern,c2_p1")
467 467
468 (define_insn_reservation "c2_mmx_sse_shft1" 2 468 (define_insn_reservation "c2_mmx_sse_shft1" 2
469 (and (eq_attr "cpu" "core2,corei7") 469 (and (eq_attr "cpu" "core2,nehalem")
470 (and (eq_attr "memory" "none") 470 (and (eq_attr "memory" "none")
471 (and (eq_attr "type" "sseishft") 471 (and (eq_attr "type" "sseishft")
472 (eq_attr "length_immediate" "0")))) 472 (eq_attr "length_immediate" "0"))))
473 "c2_decodern,c2_p1") 473 "c2_decodern,c2_p1")
474 474
475 (define_insn_reservation "c2_mmx_sse_shft1_load" 3 475 (define_insn_reservation "c2_mmx_sse_shft1_load" 3
476 (and (eq_attr "cpu" "core2,corei7") 476 (and (eq_attr "cpu" "core2,nehalem")
477 (and (eq_attr "memory" "load") 477 (and (eq_attr "memory" "load")
478 (and (eq_attr "type" "sseishft") 478 (and (eq_attr "type" "sseishft")
479 (eq_attr "length_immediate" "0")))) 479 (eq_attr "length_immediate" "0"))))
480 "c2_decodern,c2_p1") 480 "c2_decodern,c2_p1")
481 481
482 (define_insn_reservation "c2_mmx_mul" 3 482 (define_insn_reservation "c2_mmx_mul" 3
483 (and (eq_attr "cpu" "core2,corei7") 483 (and (eq_attr "cpu" "core2,nehalem")
484 (and (eq_attr "memory" "none") 484 (and (eq_attr "memory" "none")
485 (eq_attr "type" "mmxmul,sseimul"))) 485 (eq_attr "type" "mmxmul,sseimul")))
486 "c2_decodern,c2_p1") 486 "c2_decodern,c2_p1")
487 487
488 (define_insn_reservation "c2_mmx_mul_load" 3 488 (define_insn_reservation "c2_mmx_mul_load" 3
489 (and (eq_attr "cpu" "core2,corei7") 489 (and (eq_attr "cpu" "core2,nehalem")
490 (and (eq_attr "memory" "none") 490 (and (eq_attr "memory" "none")
491 (eq_attr "type" "mmxmul,sseimul"))) 491 (eq_attr "type" "mmxmul,sseimul")))
492 "c2_decoder0,c2_p2+c2_p1") 492 "c2_decoder0,c2_p2+c2_p1")
493 493
494 (define_insn_reservation "c2_sse_mmxcvt" 4 494 (define_insn_reservation "c2_sse_mmxcvt" 4
495 (and (eq_attr "cpu" "core2,corei7") 495 (and (eq_attr "cpu" "core2,nehalem")
496 (and (eq_attr "mode" "DI") 496 (and (eq_attr "mode" "DI")
497 (eq_attr "type" "mmxcvt"))) 497 (eq_attr "type" "mmxcvt")))
498 "c2_decodern,c2_p1") 498 "c2_decodern,c2_p1")
499 499
500 ;; FIXME: These are Pentium III only, but we cannot tell here if 500 ;; FIXME: These are Pentium III only, but we cannot tell here if
501 ;; we're generating code for PentiumPro/Pentium II or Pentium III 501 ;; we're generating code for PentiumPro/Pentium II or Pentium III
502 ;; (define_insn_reservation "c2_sse_mmxshft" 2 502 ;; (define_insn_reservation "c2_sse_mmxshft" 2
503 ;; (and (eq_attr "cpu" "core2,corei7") 503 ;; (and (eq_attr "cpu" "core2,nehalem")
504 ;; (and (eq_attr "mode" "TI") 504 ;; (and (eq_attr "mode" "TI")
505 ;; (eq_attr "type" "mmxshft"))) 505 ;; (eq_attr "type" "mmxshft")))
506 ;; "c2_decodern,c2_p0") 506 ;; "c2_decodern,c2_p0")
507 507
508 ;; The sfence instruction. 508 ;; The sfence instruction.
509 (define_insn_reservation "c2_sse_sfence" 3 509 (define_insn_reservation "c2_sse_sfence" 3
510 (and (eq_attr "cpu" "core2,corei7") 510 (and (eq_attr "cpu" "core2,nehalem")
511 (and (eq_attr "memory" "unknown") 511 (and (eq_attr "memory" "unknown")
512 (eq_attr "type" "sse"))) 512 (eq_attr "type" "sse")))
513 "c2_decoder0,c2_p4+c2_p3") 513 "c2_decoder0,c2_p4+c2_p3")
514 514
515 ;; FIXME: This reservation is all wrong when we're scheduling sqrtss. 515 ;; FIXME: This reservation is all wrong when we're scheduling sqrtss.
516 (define_insn_reservation "c2_sse_SFDF" 3 516 (define_insn_reservation "c2_sse_SFDF" 3
517 (and (eq_attr "cpu" "core2,corei7") 517 (and (eq_attr "cpu" "core2,nehalem")
518 (and (eq_attr "mode" "SF,DF") 518 (and (eq_attr "mode" "SF,DF")
519 (eq_attr "type" "sse"))) 519 (eq_attr "type" "sse")))
520 "c2_decodern,c2_p0") 520 "c2_decodern,c2_p0")
521 521
522 (define_insn_reservation "c2_sse_V4SF" 4 522 (define_insn_reservation "c2_sse_V4SF" 4
523 (and (eq_attr "cpu" "core2,corei7") 523 (and (eq_attr "cpu" "core2,nehalem")
524 (and (eq_attr "mode" "V4SF") 524 (and (eq_attr "mode" "V4SF")
525 (eq_attr "type" "sse"))) 525 (eq_attr "type" "sse")))
526 "c2_decoder0,c2_p1*2") 526 "c2_decoder0,c2_p1*2")
527 527
528 (define_insn_reservation "c2_sse_addcmp" 3 528 (define_insn_reservation "c2_sse_addcmp" 3
529 (and (eq_attr "cpu" "core2,corei7") 529 (and (eq_attr "cpu" "core2,nehalem")
530 (and (eq_attr "memory" "none") 530 (and (eq_attr "memory" "none")
531 (eq_attr "type" "sseadd,ssecmp,ssecomi"))) 531 (eq_attr "type" "sseadd,sseadd1,ssecmp,ssecomi")))
532 "c2_decodern,c2_p1") 532 "c2_decodern,c2_p1")
533 533
534 (define_insn_reservation "c2_sse_addcmp_load" 3 534 (define_insn_reservation "c2_sse_addcmp_load" 3
535 (and (eq_attr "cpu" "core2,corei7") 535 (and (eq_attr "cpu" "core2,nehalem")
536 (and (eq_attr "memory" "load") 536 (and (eq_attr "memory" "load")
537 (eq_attr "type" "sseadd,ssecmp,ssecomi"))) 537 (eq_attr "type" "sseadd,sseadd1,ssecmp,ssecomi")))
538 "c2_decodern,c2_p2+c2_p1") 538 "c2_decodern,c2_p2+c2_p1")
539 539
540 (define_insn_reservation "c2_sse_mul_SF" 4 540 (define_insn_reservation "c2_sse_mul_SF" 4
541 (and (eq_attr "cpu" "core2,corei7") 541 (and (eq_attr "cpu" "core2,nehalem")
542 (and (eq_attr "memory" "none") 542 (and (eq_attr "memory" "none")
543 (and (eq_attr "mode" "SF,V4SF") 543 (and (eq_attr "mode" "SF,V4SF")
544 (eq_attr "type" "ssemul")))) 544 (eq_attr "type" "ssemul"))))
545 "c2_decodern,c2_p0") 545 "c2_decodern,c2_p0")
546 546
547 (define_insn_reservation "c2_sse_mul_SF_load" 4 547 (define_insn_reservation "c2_sse_mul_SF_load" 4
548 (and (eq_attr "cpu" "core2,corei7") 548 (and (eq_attr "cpu" "core2,nehalem")
549 (and (eq_attr "memory" "load") 549 (and (eq_attr "memory" "load")
550 (and (eq_attr "mode" "SF,V4SF") 550 (and (eq_attr "mode" "SF,V4SF")
551 (eq_attr "type" "ssemul")))) 551 (eq_attr "type" "ssemul"))))
552 "c2_decodern,c2_p2+c2_p0") 552 "c2_decodern,c2_p2+c2_p0")
553 553
554 (define_insn_reservation "c2_sse_mul_DF" 5 554 (define_insn_reservation "c2_sse_mul_DF" 5
555 (and (eq_attr "cpu" "core2,corei7") 555 (and (eq_attr "cpu" "core2,nehalem")
556 (and (eq_attr "memory" "none") 556 (and (eq_attr "memory" "none")
557 (and (eq_attr "mode" "DF,V2DF") 557 (and (eq_attr "mode" "DF,V2DF")
558 (eq_attr "type" "ssemul")))) 558 (eq_attr "type" "ssemul"))))
559 "c2_decodern,c2_p0") 559 "c2_decodern,c2_p0")
560 560
561 (define_insn_reservation "c2_sse_mul_DF_load" 5 561 (define_insn_reservation "c2_sse_mul_DF_load" 5
562 (and (eq_attr "cpu" "core2,corei7") 562 (and (eq_attr "cpu" "core2,nehalem")
563 (and (eq_attr "memory" "load") 563 (and (eq_attr "memory" "load")
564 (and (eq_attr "mode" "DF,V2DF") 564 (and (eq_attr "mode" "DF,V2DF")
565 (eq_attr "type" "ssemul")))) 565 (eq_attr "type" "ssemul"))))
566 "c2_decodern,c2_p2+c2_p0") 566 "c2_decodern,c2_p2+c2_p0")
567 567
568 (define_insn_reservation "c2_sse_div_SF" 18 568 (define_insn_reservation "c2_sse_div_SF" 18
569 (and (eq_attr "cpu" "core2,corei7") 569 (and (eq_attr "cpu" "core2,nehalem")
570 (and (eq_attr "memory" "none") 570 (and (eq_attr "memory" "none")
571 (and (eq_attr "mode" "SF,V4SF") 571 (and (eq_attr "mode" "SF,V4SF")
572 (eq_attr "type" "ssediv")))) 572 (eq_attr "type" "ssediv"))))
573 "c2_decodern,c2_p0,c2_ssediv*17") 573 "c2_decodern,c2_p0,c2_ssediv*17")
574 574
575 (define_insn_reservation "c2_sse_div_SF_load" 18 575 (define_insn_reservation "c2_sse_div_SF_load" 18
576 (and (eq_attr "cpu" "core2,corei7") 576 (and (eq_attr "cpu" "core2,nehalem")
577 (and (eq_attr "memory" "none") 577 (and (eq_attr "memory" "none")
578 (and (eq_attr "mode" "SF,V4SF") 578 (and (eq_attr "mode" "SF,V4SF")
579 (eq_attr "type" "ssediv")))) 579 (eq_attr "type" "ssediv"))))
580 "c2_decodern,(c2_p2+c2_p0),c2_ssediv*17") 580 "c2_decodern,(c2_p2+c2_p0),c2_ssediv*17")
581 581
582 (define_insn_reservation "c2_sse_div_DF" 32 582 (define_insn_reservation "c2_sse_div_DF" 32
583 (and (eq_attr "cpu" "core2,corei7") 583 (and (eq_attr "cpu" "core2,nehalem")
584 (and (eq_attr "memory" "none") 584 (and (eq_attr "memory" "none")
585 (and (eq_attr "mode" "DF,V2DF") 585 (and (eq_attr "mode" "DF,V2DF")
586 (eq_attr "type" "ssediv")))) 586 (eq_attr "type" "ssediv"))))
587 "c2_decodern,c2_p0,c2_ssediv*31") 587 "c2_decodern,c2_p0,c2_ssediv*31")
588 588
589 (define_insn_reservation "c2_sse_div_DF_load" 32 589 (define_insn_reservation "c2_sse_div_DF_load" 32
590 (and (eq_attr "cpu" "core2,corei7") 590 (and (eq_attr "cpu" "core2,nehalem")
591 (and (eq_attr "memory" "none") 591 (and (eq_attr "memory" "none")
592 (and (eq_attr "mode" "DF,V2DF") 592 (and (eq_attr "mode" "DF,V2DF")
593 (eq_attr "type" "ssediv")))) 593 (eq_attr "type" "ssediv"))))
594 "c2_decodern,(c2_p2+c2_p0),c2_ssediv*31") 594 "c2_decodern,(c2_p2+c2_p0),c2_ssediv*31")
595 595
596 ;; FIXME: these have limited throughput 596 ;; FIXME: these have limited throughput
597 (define_insn_reservation "c2_sse_icvt_SF" 4 597 (define_insn_reservation "c2_sse_icvt_SF" 4
598 (and (eq_attr "cpu" "core2,corei7") 598 (and (eq_attr "cpu" "core2,nehalem")
599 (and (eq_attr "memory" "none") 599 (and (eq_attr "memory" "none")
600 (and (eq_attr "mode" "SF") 600 (and (eq_attr "mode" "SF")
601 (eq_attr "type" "sseicvt")))) 601 (eq_attr "type" "sseicvt"))))
602 "c2_decodern,c2_p1") 602 "c2_decodern,c2_p1")
603 603
604 (define_insn_reservation "c2_sse_icvt_SF_load" 4 604 (define_insn_reservation "c2_sse_icvt_SF_load" 4
605 (and (eq_attr "cpu" "core2,corei7") 605 (and (eq_attr "cpu" "core2,nehalem")
606 (and (eq_attr "memory" "!none") 606 (and (eq_attr "memory" "!none")
607 (and (eq_attr "mode" "SF") 607 (and (eq_attr "mode" "SF")
608 (eq_attr "type" "sseicvt")))) 608 (eq_attr "type" "sseicvt"))))
609 "c2_decodern,c2_p2+c2_p1") 609 "c2_decodern,c2_p2+c2_p1")
610 610
611 (define_insn_reservation "c2_sse_icvt_DF" 4 611 (define_insn_reservation "c2_sse_icvt_DF" 4
612 (and (eq_attr "cpu" "core2,corei7") 612 (and (eq_attr "cpu" "core2,nehalem")
613 (and (eq_attr "memory" "none") 613 (and (eq_attr "memory" "none")
614 (and (eq_attr "mode" "DF") 614 (and (eq_attr "mode" "DF")
615 (eq_attr "type" "sseicvt")))) 615 (eq_attr "type" "sseicvt"))))
616 "c2_decoder0,c2_p0+c2_p1") 616 "c2_decoder0,c2_p0+c2_p1")
617 617
618 (define_insn_reservation "c2_sse_icvt_DF_load" 4 618 (define_insn_reservation "c2_sse_icvt_DF_load" 4
619 (and (eq_attr "cpu" "core2,corei7") 619 (and (eq_attr "cpu" "core2,nehalem")
620 (and (eq_attr "memory" "!none") 620 (and (eq_attr "memory" "!none")
621 (and (eq_attr "mode" "DF") 621 (and (eq_attr "mode" "DF")
622 (eq_attr "type" "sseicvt")))) 622 (eq_attr "type" "sseicvt"))))
623 "c2_decoder0,(c2_p2+c2_p1)") 623 "c2_decoder0,(c2_p2+c2_p1)")
624 624
625 (define_insn_reservation "c2_sse_icvt_SI" 3 625 (define_insn_reservation "c2_sse_icvt_SI" 3
626 (and (eq_attr "cpu" "core2,corei7") 626 (and (eq_attr "cpu" "core2,nehalem")
627 (and (eq_attr "memory" "none") 627 (and (eq_attr "memory" "none")
628 (and (eq_attr "mode" "SI") 628 (and (eq_attr "mode" "SI")
629 (eq_attr "type" "sseicvt")))) 629 (eq_attr "type" "sseicvt"))))
630 "c2_decodern,c2_p1") 630 "c2_decodern,c2_p1")
631 631
632 (define_insn_reservation "c2_sse_icvt_SI_load" 3 632 (define_insn_reservation "c2_sse_icvt_SI_load" 3
633 (and (eq_attr "cpu" "core2,corei7") 633 (and (eq_attr "cpu" "core2,nehalem")
634 (and (eq_attr "memory" "!none") 634 (and (eq_attr "memory" "!none")
635 (and (eq_attr "mode" "SI") 635 (and (eq_attr "mode" "SI")
636 (eq_attr "type" "sseicvt")))) 636 (eq_attr "type" "sseicvt"))))
637 "c2_decodern,(c2_p2+c2_p1)") 637 "c2_decodern,(c2_p2+c2_p1)")
638 638
639 (define_insn_reservation "c2_sse_mov" 1 639 (define_insn_reservation "c2_sse_mov" 1
640 (and (eq_attr "cpu" "core2,corei7") 640 (and (eq_attr "cpu" "core2,nehalem")
641 (and (eq_attr "memory" "none") 641 (and (eq_attr "memory" "none")
642 (eq_attr "type" "ssemov"))) 642 (eq_attr "type" "ssemov")))
643 "c2_decodern,(c2_p0|c2_p1|c2_p5)") 643 "c2_decodern,(c2_p0|c2_p1|c2_p5)")
644 644
645 (define_insn_reservation "c2_sse_mov_load" 2 645 (define_insn_reservation "c2_sse_mov_load" 2
646 (and (eq_attr "cpu" "core2,corei7") 646 (and (eq_attr "cpu" "core2,nehalem")
647 (and (eq_attr "memory" "load") 647 (and (eq_attr "memory" "load")
648 (eq_attr "type" "ssemov"))) 648 (eq_attr "type" "ssemov")))
649 "c2_decodern,c2_p2") 649 "c2_decodern,c2_p2")
650 650
651 (define_insn_reservation "c2_sse_mov_store" 1 651 (define_insn_reservation "c2_sse_mov_store" 1
652 (and (eq_attr "cpu" "core2,corei7") 652 (and (eq_attr "cpu" "core2,nehalem")
653 (and (eq_attr "memory" "store") 653 (and (eq_attr "memory" "store")
654 (eq_attr "type" "ssemov"))) 654 (eq_attr "type" "ssemov")))
655 "c2_decodern,c2_p4+c2_p3") 655 "c2_decodern,c2_p4+c2_p3")
656 656
657 ;; All other instructions are modelled as simple instructions. 657 ;; All other instructions are modelled as simple instructions.
661 ;; 661 ;;
662 ;; reg-reg instructions produce 1 uop so they can be decoded on any of 662 ;; reg-reg instructions produce 1 uop so they can be decoded on any of
663 ;; the three decoders. Loads benefit from micro-op fusion and can be 663 ;; the three decoders. Loads benefit from micro-op fusion and can be
664 ;; treated in the same way. 664 ;; treated in the same way.
665 (define_insn_reservation "c2_insn" 1 665 (define_insn_reservation "c2_insn" 1
666 (and (eq_attr "cpu" "core2,corei7") 666 (and (eq_attr "cpu" "core2,nehalem")
667 (and (eq_attr "memory" "none,unknown") 667 (and (eq_attr "memory" "none,unknown")
668 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp"))) 668 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp")))
669 "c2_decodern,(c2_p0|c2_p1|c2_p5)") 669 "c2_decodern,(c2_p0|c2_p1|c2_p5)")
670 670
671 (define_insn_reservation "c2_insn_load" 4 671 (define_insn_reservation "c2_insn_load" 4
672 (and (eq_attr "cpu" "core2,corei7") 672 (and (eq_attr "cpu" "core2,nehalem")
673 (and (eq_attr "memory" "load") 673 (and (eq_attr "memory" "load")
674 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp"))) 674 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp")))
675 "c2_decodern,c2_p2,(c2_p0|c2_p1|c2_p5)") 675 "c2_decodern,c2_p2,(c2_p0|c2_p1|c2_p5)")
676 676
677 ;; register-memory instructions have three uops, so they have to be 677 ;; register-memory instructions have three uops, so they have to be
678 ;; decoded on c2_decoder0. 678 ;; decoded on c2_decoder0.
679 (define_insn_reservation "c2_insn_store" 1 679 (define_insn_reservation "c2_insn_store" 1
680 (and (eq_attr "cpu" "core2,corei7") 680 (and (eq_attr "cpu" "core2,nehalem")
681 (and (eq_attr "memory" "store") 681 (and (eq_attr "memory" "store")
682 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp"))) 682 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,sseishft1,mmx,mmxcmp")))
683 "c2_decoder0,(c2_p0|c2_p1|c2_p5),c2_p4+c2_p3") 683 "c2_decoder0,(c2_p0|c2_p1|c2_p5),c2_p4+c2_p3")
684 684
685 ;; read-modify-store instructions produce 4 uops so they have to be 685 ;; read-modify-store instructions produce 4 uops so they have to be
686 ;; decoded on c2_decoder0 as well. 686 ;; decoded on c2_decoder0 as well.
687 (define_insn_reservation "c2_insn_both" 4 687 (define_insn_reservation "c2_insn_both" 4
688 (and (eq_attr "cpu" "core2,corei7") 688 (and (eq_attr "cpu" "core2,nehalem")
689 (and (eq_attr "memory" "both") 689 (and (eq_attr "memory" "both")
690 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp"))) 690 (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,pop,sseishft1,mmx,mmxcmp")))
691 "c2_decoder0,c2_p2,(c2_p0|c2_p1|c2_p5),c2_p4+c2_p3") 691 "c2_decoder0,c2_p2,(c2_p0|c2_p1|c2_p5),c2_p4+c2_p3")