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comparison gcc/config/m68k/m68k.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 77e2b8dfacca
children 84e7813d76e9
comparison
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68:561a7518be6b 111:04ced10e8804
1 ;;- Machine description for GNU compiler, Motorola 68000 Version 1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001, 2 ;; Copyright (C) 1987-2017 Free Software Foundation, Inc.
3 ;; 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 ;; Free Software Foundation, Inc.
5 3
6 ;; This file is part of GCC. 4 ;; This file is part of GCC.
7 5
8 ;; GCC is free software; you can redistribute it and/or modify 6 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by 7 ;; it under the terms of the GNU General Public License as published by
122 120
123 ;; UNSPEC_VOLATILE usage: 121 ;; UNSPEC_VOLATILE usage:
124 122
125 (define_constants 123 (define_constants
126 [(UNSPECV_BLOCKAGE 0) 124 [(UNSPECV_BLOCKAGE 0)
125 (UNSPECV_CAS_1 1)
126 (UNSPECV_CAS_2 2)
127 (UNSPECV_TAS_1 3)
128 (UNSPECV_TAS_2 4)
127 ]) 129 ])
128 130
129 ;; Registers by name. 131 ;; Registers by name.
130 (define_constants 132 (define_constants
131 [(D0_REG 0) 133 [(D0_REG 0)
248 ;; Alternative is OK for ColdFire. 250 ;; Alternative is OK for ColdFire.
249 (define_attr "ok_for_coldfire" "yes,no" (const_string "yes")) 251 (define_attr "ok_for_coldfire" "yes,no" (const_string "yes"))
250 252
251 ;; Define 'enabled' attribute. 253 ;; Define 'enabled' attribute.
252 (define_attr "enabled" "" 254 (define_attr "enabled" ""
253 (cond [(and (ne (symbol_ref "TARGET_COLDFIRE") (const_int 0)) 255 (cond [(and (match_test "TARGET_COLDFIRE")
254 (eq_attr "ok_for_coldfire" "no")) 256 (eq_attr "ok_for_coldfire" "no"))
255 (const_int 0)] 257 (const_int 0)]
256 (const_int 1))) 258 (const_int 1)))
257 259
260 ;; Mode macros for integer operations.
261 (define_mode_iterator I [QI HI SI])
262 (define_mode_attr sz [(QI "%.b") (HI "%.w") (SI "%.l")])
263
258 ;; Mode macros for floating point operations. 264 ;; Mode macros for floating point operations.
259 ;; Valid floating point modes 265 ;; Valid floating point modes
260 (define_mode_iterator FP [SF DF (XF "TARGET_68881")]) 266 (define_mode_iterator FP [SF DF (XF "TARGET_68881")])
261 ;; Mnemonic infix to round result 267 ;; Mnemonic infix to round result
262 (define_mode_attr round [(SF "%$") (DF "%&") (XF "")]) 268 (define_mode_attr round [(SF "%$") (DF "%&") (XF "")])
481 "" 487 ""
482 "") 488 "")
483 489
484 490
485 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes. 491 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
492 ;;
493 ;; In theory we ought to be able to use some 'S' constraints and
494 ;; operand predicates that allow PC-rel addressing modes in the
495 ;; comparison patterns and expanders below. But we would have to be
496 ;; cognizant of the fact that PC-rel addresses are not allowed for
497 ;; both operands and determining whether or not we emit the operands in
498 ;; order or reversed is not trivial to do just based on the constraints
499 ;; and operand predicates. So to be safe, just don't allow the PC-rel
500 ;; versions in the various comparison expanders, patterns, for comparisons.
486 (define_insn "" 501 (define_insn ""
487 [(set (cc0) 502 [(set (cc0)
488 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>") 503 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mr,ma,>")
489 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))] 504 (match_operand:SI 1 "general_operand" "mr,ma,KTr,Ksr,>")))]
490 "!TARGET_COLDFIRE" 505 "!TARGET_COLDFIRE"
491 { 506 {
492 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 507 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
493 return "cmpm%.l %1,%0"; 508 return "cmpm%.l %1,%0";
494 if (REG_P (operands[1]) 509 if (REG_P (operands[1])
521 } 536 }
522 [(set_attr "type" "cmp_l")]) 537 [(set_attr "type" "cmp_l")])
523 538
524 (define_expand "cbranchhi4" 539 (define_expand "cbranchhi4"
525 [(set (cc0) 540 [(set (cc0)
526 (compare (match_operand:HI 1 "nonimmediate_src_operand" "") 541 (compare (match_operand:HI 1 "nonimmediate_operand" "")
527 (match_operand:HI 2 "m68k_subword_comparison_operand" ""))) 542 (match_operand:HI 2 "m68k_subword_comparison_operand" "")))
528 (set (pc) 543 (set (pc)
529 (if_then_else (match_operator 0 "ordered_comparison_operator" 544 (if_then_else (match_operator 0 "ordered_comparison_operator"
530 [(cc0) (const_int 0)]) 545 [(cc0) (const_int 0)])
531 (label_ref (match_operand 3 "")) 546 (label_ref (match_operand 3 ""))
543 "" 558 ""
544 "") 559 "")
545 560
546 (define_insn "" 561 (define_insn ""
547 [(set (cc0) 562 [(set (cc0)
548 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>") 563 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
549 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))] 564 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
550 "!TARGET_COLDFIRE" 565 "!TARGET_COLDFIRE"
551 { 566 {
552 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 567 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
553 return "cmpm%.w %1,%0"; 568 return "cmpm%.w %1,%0";
554 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1])) 569 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
560 return "cmp%.w %d1,%d0"; 575 return "cmp%.w %d1,%d0";
561 }) 576 })
562 577
563 (define_expand "cbranchqi4" 578 (define_expand "cbranchqi4"
564 [(set (cc0) 579 [(set (cc0)
565 (compare (match_operand:QI 1 "nonimmediate_src_operand" "") 580 (compare (match_operand:QI 1 "nonimmediate_operand" "")
566 (match_operand:QI 2 "m68k_subword_comparison_operand" ""))) 581 (match_operand:QI 2 "m68k_subword_comparison_operand" "")))
567 (set (pc) 582 (set (pc)
568 (if_then_else (match_operator 0 "ordered_comparison_operator" 583 (if_then_else (match_operator 0 "ordered_comparison_operator"
569 [(cc0) (const_int 0)]) 584 [(cc0) (const_int 0)])
570 (label_ref (match_operand 3 "")) 585 (label_ref (match_operand 3 ""))
572 "" 587 ""
573 "") 588 "")
574 589
575 (define_expand "cstoreqi4" 590 (define_expand "cstoreqi4"
576 [(set (cc0) 591 [(set (cc0)
577 (compare (match_operand:QI 2 "nonimmediate_src_operand" "") 592 (compare (match_operand:QI 2 "nonimmediate_operand" "")
578 (match_operand:QI 3 "m68k_subword_comparison_operand" ""))) 593 (match_operand:QI 3 "m68k_subword_comparison_operand" "")))
579 (set (match_operand:QI 0 "register_operand") 594 (set (match_operand:QI 0 "register_operand")
580 (match_operator:QI 1 "ordered_comparison_operator" 595 (match_operator:QI 1 "ordered_comparison_operator"
581 [(cc0) (const_int 0)]))] 596 [(cc0) (const_int 0)]))]
582 "" 597 ""
583 "") 598 "")
584 599
585 (define_insn "" 600 (define_insn ""
586 [(set (cc0) 601 [(set (cc0)
587 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>") 602 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,dm,>")
588 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))] 603 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
589 "!TARGET_COLDFIRE" 604 "!TARGET_COLDFIRE"
590 { 605 {
591 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 606 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
592 return "cmpm%.b %1,%0"; 607 return "cmpm%.b %1,%0";
593 if (REG_P (operands[1]) 608 if (REG_P (operands[1])
689 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") 704 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
690 (const_int 1) 705 (const_int 1)
691 (minus:SI (const_int 31) 706 (minus:SI (const_int 31)
692 (match_operand:SI 1 "general_operand" "di"))) 707 (match_operand:SI 1 "general_operand" "di")))
693 (const_int 0)))] 708 (const_int 0)))]
694 "" 709 "!(CONST_INT_P (operands[1]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
695 { 710 {
696 return output_btst (operands, operands[1], operands[0], insn, 31); 711 return output_btst (operands, operands[1], operands[0], insn, 31);
697 }) 712 })
698 713
699 ;; The following two patterns are like the previous two 714 ;; The following two patterns are like the previous two
748 (define_insn "" 763 (define_insn ""
749 [(set 764 [(set
750 (cc0) 765 (cc0)
751 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "do") 766 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "do")
752 (const_int 1) 767 (const_int 1)
753 (match_operand:SI 1 "const_int_operand" "n")) 768 (match_operand:SI 1 "const_int_operand" "n"))
754 (const_int 0)))] 769 (const_int 0)))]
755 "!TARGET_COLDFIRE" 770 "!TARGET_COLDFIRE
771 && !(REG_P (operands[0]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
756 { 772 {
757 if (GET_CODE (operands[0]) == MEM) 773 if (GET_CODE (operands[0]) == MEM)
758 { 774 {
759 operands[0] = adjust_address (operands[0], QImode, 775 operands[0] = adjust_address (operands[0], QImode,
760 INTVAL (operands[1]) / 8); 776 INTVAL (operands[1]) / 8);
773 (cc0) 789 (cc0)
774 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "dQ") 790 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "dQ")
775 (const_int 1) 791 (const_int 1)
776 (match_operand:SI 1 "const_int_operand" "n")) 792 (match_operand:SI 1 "const_int_operand" "n"))
777 (const_int 0)))] 793 (const_int 0)))]
778 "TARGET_COLDFIRE" 794 "TARGET_COLDFIRE
795 && !(REG_P (operands[0]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
779 { 796 {
780 if (GET_CODE (operands[0]) == MEM) 797 if (GET_CODE (operands[0]) == MEM)
781 { 798 {
782 operands[0] = adjust_address (operands[0], QImode, 799 operands[0] = adjust_address (operands[0], QImode,
783 INTVAL (operands[1]) / 8); 800 INTVAL (operands[1]) / 8);
1117 { 1134 {
1118 if (emit_move_sequence (operands, SFmode, operands[2])) 1135 if (emit_move_sequence (operands, SFmode, operands[2]))
1119 DONE; 1136 DONE;
1120 1137
1121 /* We don't want the clobber emitted, so handle this ourselves. */ 1138 /* We don't want the clobber emitted, so handle this ourselves. */
1122 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 1139 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1123 DONE; 1140 DONE;
1124 }) 1141 })
1125 1142
1126 (define_expand "reload_outsf" 1143 (define_expand "reload_outsf"
1127 [(set (match_operand:SF 0 "general_operand" "") 1144 [(set (match_operand:SF 0 "general_operand" "")
1131 { 1148 {
1132 if (emit_move_sequence (operands, SFmode, operands[2])) 1149 if (emit_move_sequence (operands, SFmode, operands[2]))
1133 DONE; 1150 DONE;
1134 1151
1135 /* We don't want the clobber emitted, so handle this ourselves. */ 1152 /* We don't want the clobber emitted, so handle this ourselves. */
1136 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 1153 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1137 DONE; 1154 DONE;
1138 }) 1155 })
1139 1156
1140 (define_expand "movsf" 1157 (define_expand "movsf"
1141 [(set (match_operand:SF 0 "nonimmediate_operand" "") 1158 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1201 ,f"))] 1218 ,f"))]
1202 "TARGET_COLDFIRE_FPU" 1219 "TARGET_COLDFIRE_FPU"
1203 { 1220 {
1204 if (which_alternative == 4 || which_alternative == 5) { 1221 if (which_alternative == 4 || which_alternative == 5) {
1205 rtx xoperands[2]; 1222 rtx xoperands[2];
1206 REAL_VALUE_TYPE r;
1207 long l; 1223 long l;
1208 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); 1224 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), l);
1209 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1210 xoperands[0] = operands[0]; 1225 xoperands[0] = operands[0];
1211 xoperands[1] = GEN_INT (l); 1226 xoperands[1] = GEN_INT (l);
1212 if (which_alternative == 5) { 1227 if (which_alternative == 5) {
1213 if (l == 0) { 1228 if (l == 0) {
1214 if (ADDRESS_REG_P (xoperands[0])) 1229 if (ADDRESS_REG_P (xoperands[0]))
1260 { 1275 {
1261 if (emit_move_sequence (operands, DFmode, operands[2])) 1276 if (emit_move_sequence (operands, DFmode, operands[2]))
1262 DONE; 1277 DONE;
1263 1278
1264 /* We don't want the clobber emitted, so handle this ourselves. */ 1279 /* We don't want the clobber emitted, so handle this ourselves. */
1265 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 1280 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1266 DONE; 1281 DONE;
1267 }) 1282 })
1268 1283
1269 (define_expand "reload_outdf" 1284 (define_expand "reload_outdf"
1270 [(set (match_operand:DF 0 "general_operand" "") 1285 [(set (match_operand:DF 0 "general_operand" "")
1274 { 1289 {
1275 if (emit_move_sequence (operands, DFmode, operands[2])) 1290 if (emit_move_sequence (operands, DFmode, operands[2]))
1276 DONE; 1291 DONE;
1277 1292
1278 /* We don't want the clobber emitted, so handle this ourselves. */ 1293 /* We don't want the clobber emitted, so handle this ourselves. */
1279 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 1294 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1280 DONE; 1295 DONE;
1281 }) 1296 })
1282 1297
1283 (define_expand "movdf" 1298 (define_expand "movdf"
1284 [(set (match_operand:DF 0 "nonimmediate_operand" "") 1299 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1343 [(set (match_operand:DF 0 "nonimmediate_operand" "=f, <Q>U,r,f,r,r,m,f") 1358 [(set (match_operand:DF 0 "nonimmediate_operand" "=f, <Q>U,r,f,r,r,m,f")
1344 (match_operand:DF 1 "general_operand" " f<Q>U,f, f,r,r,m,r,E"))] 1359 (match_operand:DF 1 "general_operand" " f<Q>U,f, f,r,r,m,r,E"))]
1345 "TARGET_COLDFIRE_FPU" 1360 "TARGET_COLDFIRE_FPU"
1346 { 1361 {
1347 rtx xoperands[3]; 1362 rtx xoperands[3];
1348 REAL_VALUE_TYPE r;
1349 long l[2]; 1363 long l[2];
1350 1364
1351 switch (which_alternative) 1365 switch (which_alternative)
1352 { 1366 {
1353 default: 1367 default:
1359 case 3: 1373 case 3:
1360 return "move%.l %R1,%-;move%.l %1,%-;fdmove%.d %+,%0"; 1374 return "move%.l %R1,%-;move%.l %1,%-;fdmove%.d %+,%0";
1361 case 4: case 5: case 6: 1375 case 4: case 5: case 6:
1362 return output_move_double (operands); 1376 return output_move_double (operands);
1363 case 7: 1377 case 7:
1364 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); 1378 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), l);
1365 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
1366 xoperands[0] = operands[0]; 1379 xoperands[0] = operands[0];
1367 xoperands[1] = GEN_INT (l[0]); 1380 xoperands[1] = GEN_INT (l[0]);
1368 xoperands[2] = GEN_INT (l[1]); 1381 xoperands[2] = GEN_INT (l[1]);
1369 if (operands[1] == CONST0_RTX (DFmode)) 1382 if (operands[1] == CONST0_RTX (DFmode))
1370 output_asm_insn ("clr%.l %-;clr%.l %-;fdmove%.d %+,%0", 1383 output_asm_insn ("clr%.l %-;clr%.l %-;fdmove%.d %+,%0",
1381 }) 1394 })
1382 1395
1383 ;; ??? The XFmode patterns are schizophrenic about whether constants are 1396 ;; ??? The XFmode patterns are schizophrenic about whether constants are
1384 ;; allowed. Most but not all have predicates and constraint that disallow 1397 ;; allowed. Most but not all have predicates and constraint that disallow
1385 ;; constants. Most but not all have output templates that handle constants. 1398 ;; constants. Most but not all have output templates that handle constants.
1386 ;; See also LEGITIMATE_CONSTANT_P. 1399 ;; See also TARGET_LEGITIMATE_CONSTANT_P.
1387 1400
1388 (define_expand "movxf" 1401 (define_expand "movxf"
1389 [(set (match_operand:XF 0 "nonimmediate_operand" "") 1402 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1390 (match_operand:XF 1 "general_operand" ""))] 1403 (match_operand:XF 1 "general_operand" ""))]
1391 "" 1404 ""
1564 ;; truncation instructions 1577 ;; truncation instructions
1565 (define_insn "truncsiqi2" 1578 (define_insn "truncsiqi2"
1566 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d") 1579 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1567 (truncate:QI 1580 (truncate:QI
1568 (match_operand:SI 1 "general_src_operand" "doJS,i")))] 1581 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1569 "" 1582 "!TARGET_COLDFIRE"
1570 { 1583 {
1571 if (GET_CODE (operands[0]) == REG) 1584 if (GET_CODE (operands[0]) == REG)
1572 { 1585 {
1573 /* Must clear condition codes, since the move.l bases them on 1586 /* Must clear condition codes, since the move.l bases them on
1574 the entire 32 bits, not just the desired 8 bits. */ 1587 the entire 32 bits, not just the desired 8 bits. */
1582 1595
1583 (define_insn "trunchiqi2" 1596 (define_insn "trunchiqi2"
1584 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d") 1597 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1585 (truncate:QI 1598 (truncate:QI
1586 (match_operand:HI 1 "general_src_operand" "doJS,i")))] 1599 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1587 "" 1600 "!TARGET_COLDFIRE"
1588 { 1601 {
1589 if (GET_CODE (operands[0]) == REG 1602 if (GET_CODE (operands[0]) == REG
1590 && (GET_CODE (operands[1]) == MEM 1603 && (GET_CODE (operands[1]) == MEM
1591 || GET_CODE (operands[1]) == CONST_INT)) 1604 || GET_CODE (operands[1]) == CONST_INT))
1592 { 1605 {
1609 1622
1610 (define_insn "truncsihi2" 1623 (define_insn "truncsihi2"
1611 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d") 1624 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
1612 (truncate:HI 1625 (truncate:HI
1613 (match_operand:SI 1 "general_src_operand" "roJS,i")))] 1626 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1614 "" 1627 "!TARGET_COLDFIRE"
1615 { 1628 {
1616 if (GET_CODE (operands[0]) == REG) 1629 if (GET_CODE (operands[0]) == REG)
1617 { 1630 {
1618 /* Must clear condition codes, since the move.l bases them on 1631 /* Must clear condition codes, since the move.l bases them on
1619 the entire 32 bits, not just the desired 8 bits. */ 1632 the entire 32 bits, not just the desired 8 bits. */
1860 1873
1861 ;; Special case when one can avoid register clobbering, copy and test 1874 ;; Special case when one can avoid register clobbering, copy and test
1862 ;; Maybe there is a way to make that the general case, by forcing the 1875 ;; Maybe there is a way to make that the general case, by forcing the
1863 ;; result of the SI tree to be in the lower register of the DI target 1876 ;; result of the SI tree to be in the lower register of the DI target
1864 1877
1878 ;; Don't allow memory for operand 1 as that would require an earlyclobber
1879 ;; which results in worse code
1865 (define_insn "extendplussidi" 1880 (define_insn "extendplussidi"
1866 [(set (match_operand:DI 0 "register_operand" "=d") 1881 [(set (match_operand:DI 0 "register_operand" "=d")
1867 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn") 1882 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rn")
1868 (match_operand:SI 2 "general_operand" "rmn"))))] 1883 (match_operand:SI 2 "general_operand" "rmn"))))]
1869 "" 1884 ""
1870 { 1885 {
1871 CC_STATUS_INIT; 1886 CC_STATUS_INIT;
1872 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1887 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2399 gcc_assert (GET_CODE (operands[0]) == MEM); 2414 gcc_assert (GET_CODE (operands[0]) == MEM);
2400 CC_STATUS_INIT; 2415 CC_STATUS_INIT;
2401 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) 2416 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2402 { 2417 {
2403 operands[1] = gen_rtx_MEM (SImode, 2418 operands[1] = gen_rtx_MEM (SImode,
2404 plus_constant (XEXP(operands[0], 0), -8)); 2419 plus_constant (Pmode,
2420 XEXP(operands[0], 0), -8));
2405 return "move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1"; 2421 return "move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1";
2406 } 2422 }
2407 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 2423 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2408 { 2424 {
2409 operands[1] = XEXP(operands[0], 0); 2425 operands[1] = XEXP(operands[0], 0);
2897 gcc_assert (GET_CODE (operands[0]) == MEM); 2913 gcc_assert (GET_CODE (operands[0]) == MEM);
2898 CC_STATUS_INIT; 2914 CC_STATUS_INIT;
2899 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) 2915 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2900 { 2916 {
2901 operands[1] 2917 operands[1]
2902 = gen_rtx_MEM (SImode, plus_constant (XEXP (operands[0], 0), -8)); 2918 = gen_rtx_MEM (SImode, plus_constant (Pmode,
2919 XEXP (operands[0], 0), -8));
2903 return "move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1"; 2920 return "move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1";
2904 } 2921 }
2905 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 2922 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2906 { 2923 {
2907 operands[1] = XEXP(operands[0], 0); 2924 operands[1] = XEXP(operands[0], 0);
3585 return ""; 3602 return "";
3586 }) 3603 })
3587 3604
3588 ;; logical-and instructions 3605 ;; logical-and instructions
3589 3606
3590 ;; "anddi3" is mainly here to help combine().
3591 (define_insn "anddi3"
3592 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3593 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3594 (match_operand:DI 2 "general_operand" "dn,don")))]
3595 "!TARGET_COLDFIRE"
3596 {
3597 CC_STATUS_INIT;
3598 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3599 if (CONSTANT_P (operands[2]))
3600 {
3601 rtx hi, lo;
3602
3603 split_double (operands[2], &hi, &lo);
3604
3605 switch (INTVAL (hi))
3606 {
3607 case 0 :
3608 output_asm_insn ("clr%.l %0", operands);
3609 break;
3610 case -1 :
3611 break;
3612 default :
3613 {
3614 rtx xoperands[3];
3615
3616 xoperands[0] = operands[0];
3617 xoperands[2] = hi;
3618 output_asm_insn (output_andsi3 (xoperands), xoperands);
3619 }
3620 }
3621 if (GET_CODE (operands[0]) == REG)
3622 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3623 else
3624 operands[0] = adjust_address (operands[0], SImode, 4);
3625 switch (INTVAL (lo))
3626 {
3627 case 0 :
3628 output_asm_insn ("clr%.l %0", operands);
3629 break;
3630 case -1 :
3631 break;
3632 default :
3633 {
3634 rtx xoperands[3];
3635
3636 xoperands[0] = operands[0];
3637 xoperands[2] = lo;
3638 output_asm_insn (output_andsi3 (xoperands), xoperands);
3639 }
3640 }
3641 return "";
3642 }
3643 if (GET_CODE (operands[0]) != REG)
3644 {
3645 operands[1] = adjust_address (operands[0], SImode, 4);
3646 return "and%.l %2,%0\;and%.l %R2,%1";
3647 }
3648 if (GET_CODE (operands[2]) != REG)
3649 {
3650 operands[1] = adjust_address (operands[2], SImode, 4);
3651 return "and%.l %2,%0\;and%.l %1,%R0";
3652 }
3653 return "and%.l %2,%0\;and%.l %R2,%R0";
3654 })
3655
3656 ;; Prevent AND from being made with sp. This doesn't exist in the machine 3607 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3657 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we 3608 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3658 ;; can't allocate pseudos into it. 3609 ;; can't allocate pseudos into it.
3659 3610
3660 (define_expand "andsi3" 3611 (define_expand "andsi3"
3768 return "or%.b %1,%0"; 3719 return "or%.b %1,%0";
3769 else 3720 else
3770 return "or%.w %1,%0"; 3721 return "or%.w %1,%0";
3771 }) 3722 })
3772 3723
3773 ;; "iordi3" is mainly here to help combine().
3774 (define_insn "iordi3"
3775 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3776 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3777 (match_operand:DI 2 "general_operand" "dn,don")))]
3778 "!TARGET_COLDFIRE"
3779 {
3780 CC_STATUS_INIT;
3781 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3782 if (CONSTANT_P (operands[2]))
3783 {
3784 rtx hi, lo;
3785
3786 split_double (operands[2], &hi, &lo);
3787
3788 switch (INTVAL (hi))
3789 {
3790 case 0 :
3791 break;
3792 case -1 :
3793 /* FIXME : a scratch register would be welcome here if operand[0]
3794 is not a register */
3795 output_asm_insn ("move%.l #-1,%0", operands);
3796 break;
3797 default :
3798 {
3799 rtx xoperands[3];
3800
3801 xoperands[0] = operands[0];
3802 xoperands[2] = hi;
3803 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3804 }
3805 }
3806 if (GET_CODE (operands[0]) == REG)
3807 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3808 else
3809 operands[0] = adjust_address (operands[0], SImode, 4);
3810 switch (INTVAL (lo))
3811 {
3812 case 0 :
3813 break;
3814 case -1 :
3815 /* FIXME : a scratch register would be welcome here if operand[0]
3816 is not a register */
3817 output_asm_insn ("move%.l #-1,%0", operands);
3818 break;
3819 default :
3820 {
3821 rtx xoperands[3];
3822
3823 xoperands[0] = operands[0];
3824 xoperands[2] = lo;
3825 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3826 }
3827 }
3828 return "";
3829 }
3830 if (GET_CODE (operands[0]) != REG)
3831 {
3832 operands[1] = adjust_address (operands[0], SImode, 4);
3833 return "or%.l %2,%0\;or%.l %R2,%1";
3834 }
3835 if (GET_CODE (operands[2]) != REG)
3836 {
3837 operands[1] = adjust_address (operands[2], SImode, 4);
3838 return "or%.l %2,%0\;or%.l %1,%R0";
3839 }
3840 return "or%.l %2,%0\;or%.l %R2,%R0";
3841 })
3842
3843 (define_expand "iorsi3" 3724 (define_expand "iorsi3"
3844 [(set (match_operand:SI 0 "nonimmediate_operand" "") 3725 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3845 (ior:SI (match_operand:SI 1 "general_operand" "") 3726 (ior:SI (match_operand:SI 1 "general_operand" "")
3846 (match_operand:SI 2 "general_src_operand" "")))] 3727 (match_operand:SI 2 "general_src_operand" "")))]
3847 "" 3728 ""
3945 return "or%.w %1,%0"; 3826 return "or%.w %1,%0";
3946 }) 3827 })
3947 3828
3948 ;; xor instructions 3829 ;; xor instructions
3949 3830
3950 ;; "xordi3" is mainly here to help combine().
3951 (define_insn "xordi3"
3952 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
3953 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3954 (match_operand:DI 2 "general_operand" "dn")))]
3955 "!TARGET_COLDFIRE"
3956 {
3957 CC_STATUS_INIT;
3958 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3959
3960 if (CONSTANT_P (operands[2]))
3961 {
3962 rtx hi, lo;
3963
3964 split_double (operands[2], &hi, &lo);
3965
3966 switch (INTVAL (hi))
3967 {
3968 case 0 :
3969 break;
3970 case -1 :
3971 output_asm_insn ("not%.l %0", operands);
3972 break;
3973 default :
3974 /* FIXME : a scratch register would be welcome here if
3975 -128 <= INTVAL (hi) < -1 */
3976 {
3977 rtx xoperands[3];
3978
3979 xoperands[0] = operands[0];
3980 xoperands[2] = hi;
3981 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3982 }
3983 }
3984 if (GET_CODE (operands[0]) == REG)
3985 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3986 else
3987 operands[0] = adjust_address (operands[0], SImode, 4);
3988 switch (INTVAL (lo))
3989 {
3990 case 0 :
3991 break;
3992 case -1 :
3993 output_asm_insn ("not%.l %0", operands);
3994 break;
3995 default :
3996 /* FIXME : a scratch register would be welcome here if
3997 -128 <= INTVAL (lo) < -1 */
3998 operands[2] = lo;
3999 /* FIXME : this should be merged with xorsi3 */
4000 {
4001 rtx xoperands[3];
4002
4003 xoperands[0] = operands[0];
4004 xoperands[2] = lo;
4005 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4006 }
4007 }
4008 return "";
4009 }
4010 if (GET_CODE (operands[0]) != REG)
4011 {
4012 operands[1] = adjust_address (operands[0], SImode, 4);
4013 return "eor%.l %2,%0\;eor%.l %R2,%1";
4014 }
4015 if (GET_CODE (operands[2]) != REG)
4016 {
4017 operands[1] = adjust_address (operands[2], SImode, 4);
4018 return "eor%.l %2,%0\;eor%.l %1,%R0";
4019 }
4020 return "eor%.l %2,%0\;eor%.l %R2,%R0";
4021 })
4022
4023 (define_expand "xorsi3" 3831 (define_expand "xorsi3"
4024 [(set (match_operand:SI 0 "nonimmediate_operand" "") 3832 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4025 (xor:SI (match_operand:SI 1 "general_operand" "") 3833 (xor:SI (match_operand:SI 1 "general_operand" "")
4026 (match_operand:SI 2 "general_operand" "")))] 3834 (match_operand:SI 2 "general_operand" "")))]
4027 "" 3835 ""
4028 "") 3836 "")
4029 3837
4030 (define_insn "xorsi3_internal" 3838 (define_insn "xorsi3_internal"
4031 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m") 3839 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,o,m")
4032 (xor:SI (match_operand:SI 1 "general_operand" "%0,0") 3840 (xor:SI (match_operand:SI 1 "general_operand" "%0, 0,0")
4033 (match_operand:SI 2 "general_operand" "di,dKT")))] 3841 (match_operand:SI 2 "general_operand" "di,dK,dKT")))]
4034 3842
4035 "!TARGET_COLDFIRE" 3843 "!TARGET_COLDFIRE"
4036 { 3844 {
4037 return output_xorsi3 (operands); 3845 return output_xorsi3 (operands);
4038 }) 3846 })
4455 } 4263 }
4456 [(set_attr "type" "bitrw,fneg")]) 4264 [(set_attr "type" "bitrw,fneg")])
4457 4265
4458 ;; bit indexing instructions 4266 ;; bit indexing instructions
4459 4267
4268 (define_expand "clzsi2"
4269 [(set (match_operand:SI 0 "register_operand" "")
4270 (clz:SI (match_operand:SI 1 "general_operand" "")))]
4271 "ISA_HAS_FF1 || (TARGET_68020 && TARGET_BITFIELD)"
4272 {
4273 if (ISA_HAS_FF1)
4274 operands[1] = force_reg (SImode, operands[1]);
4275 })
4276
4277 (define_insn "*clzsi2_68k"
4278 [(set (match_operand:SI 0 "register_operand" "=d")
4279 (clz:SI (match_operand:SI 1 "general_operand" "do")))]
4280 "TARGET_68020 && TARGET_BITFIELD"
4281 {
4282 CC_STATUS_INIT;
4283 return "bfffo %1{#0:#0},%0";
4284 })
4285
4460 ;; ColdFire ff1 instruction implements clz. 4286 ;; ColdFire ff1 instruction implements clz.
4461 (define_insn "clzsi2" 4287 (define_insn "*clzsi2_cf"
4462 [(set (match_operand:SI 0 "register_operand" "=d") 4288 [(set (match_operand:SI 0 "register_operand" "=d")
4463 (clz:SI (match_operand:SI 1 "register_operand" "0")))] 4289 (clz:SI (match_operand:SI 1 "register_operand" "0")))]
4464 "ISA_HAS_FF1" 4290 "ISA_HAS_FF1"
4465 "ff1 %0" 4291 {
4292 CC_STATUS_INIT;
4293 return "ff1 %0";
4294 }
4466 [(set_attr "type" "ext")]) 4295 [(set_attr "type" "ext")])
4467 4296
4468 ;; one complement instructions 4297 ;; one complement instructions
4469
4470 ;; "one_cmpldi2" is mainly here to help combine().
4471 (define_insn "one_cmpldi2"
4472 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
4473 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4474 "!TARGET_COLDFIRE"
4475 {
4476 CC_STATUS_INIT;
4477 if (GET_CODE (operands[0]) == REG)
4478 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4479 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4480 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4481 operands[1] = operands[0];
4482 else
4483 operands[1] = adjust_address (operands[0], SImode, 4);
4484 return "not%.l %1\;not%.l %0";
4485 })
4486 4298
4487 (define_expand "one_cmplsi2" 4299 (define_expand "one_cmplsi2"
4488 [(set (match_operand:SI 0 "nonimmediate_operand" "") 4300 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4489 (not:SI (match_operand:SI 1 "general_operand" "")))] 4301 (not:SI (match_operand:SI 1 "general_operand" "")))]
4490 "" 4302 ""
4533 "!TARGET_COLDFIRE" 4345 "!TARGET_COLDFIRE"
4534 "not%.b %0") 4346 "not%.b %0")
4535 4347
4536 ;; arithmetic shift instructions 4348 ;; arithmetic shift instructions
4537 ;; We don't need the shift memory by 1 bit instruction 4349 ;; We don't need the shift memory by 1 bit instruction
4538 4350 (define_insn_and_split "ashldi_extsi"
4539 (define_insn "ashldi_extsi"
4540 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro") 4351 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
4541 (ashift:DI 4352 (ashift:DI
4542 (match_operator:DI 2 "extend_operator" 4353 (match_operator:DI 2 "extend_operator"
4543 [(match_operand:SI 1 "general_operand" "rm")]) 4354 [(match_operand:SI 1 "general_operand" "rm")])
4544 (const_int 32)))] 4355 (const_int 32)))]
4545 "" 4356 ""
4546 { 4357 "#"
4547 CC_STATUS_INIT; 4358 "&& reload_completed"
4548 if (GET_CODE (operands[0]) == REG) 4359 [(set (match_dup 3) (match_dup 1))
4549 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 4360 (set (match_dup 2) (const_int 0))]
4550 else 4361 "split_di(operands, 1, operands + 2, operands + 3);")
4551 operands[2] = adjust_address (operands[0], SImode, 4);
4552 if (ADDRESS_REG_P (operands[0]))
4553 return "move%.l %1,%0\;sub%.l %2,%2";
4554 else
4555 return "move%.l %1,%0\;clr%.l %2";
4556 })
4557 4362
4558 (define_insn "ashldi_sexthi" 4363 (define_insn "ashldi_sexthi"
4559 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d") 4364 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
4560 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm")) 4365 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4561 (const_int 32))) 4366 (const_int 32)))
4739 "#") 4544 "#")
4740 4545
4741 (define_expand "ashldi3" 4546 (define_expand "ashldi3"
4742 [(set (match_operand:DI 0 "register_operand" "") 4547 [(set (match_operand:DI 0 "register_operand" "")
4743 (ashift:DI (match_operand:DI 1 "register_operand" "") 4548 (ashift:DI (match_operand:DI 1 "register_operand" "")
4744 (match_operand 2 "const_int_operand" "")))] 4549 (match_operand:SI 2 "const_int_operand" "")))]
4745 "!TARGET_COLDFIRE" 4550 "!TARGET_COLDFIRE"
4746 { 4551 {
4747 /* ??? This is a named pattern like this is not allowed to FAIL based 4552 /* ??? This is a named pattern like this is not allowed to FAIL based
4748 on its operands. */ 4553 on its operands. */
4749 if (GET_CODE (operands[2]) != CONST_INT 4554 if (GET_CODE (operands[2]) != CONST_INT
5008 }) 4813 })
5009 4814
5010 (define_expand "ashrdi3" 4815 (define_expand "ashrdi3"
5011 [(set (match_operand:DI 0 "register_operand" "") 4816 [(set (match_operand:DI 0 "register_operand" "")
5012 (ashiftrt:DI (match_operand:DI 1 "register_operand" "") 4817 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5013 (match_operand 2 "const_int_operand" "")))] 4818 (match_operand:SI 2 "const_int_operand" "")))]
5014 "!TARGET_COLDFIRE" 4819 "!TARGET_COLDFIRE"
5015 { 4820 {
5016 /* ??? This is a named pattern like this is not allowed to FAIL based 4821 /* ??? This is a named pattern like this is not allowed to FAIL based
5017 on its operands. */ 4822 on its operands. */
5018 if (GET_CODE (operands[2]) != CONST_INT 4823 if (GET_CODE (operands[2]) != CONST_INT
5277 "#") 5082 "#")
5278 5083
5279 (define_expand "lshrdi3" 5084 (define_expand "lshrdi3"
5280 [(set (match_operand:DI 0 "register_operand" "") 5085 [(set (match_operand:DI 0 "register_operand" "")
5281 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 5086 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5282 (match_operand 2 "const_int_operand" "")))] 5087 (match_operand:SI 2 "const_int_operand" "")))]
5283 "!TARGET_COLDFIRE" 5088 "!TARGET_COLDFIRE"
5284 { 5089 {
5285 /* ??? This is a named pattern like this is not allowed to FAIL based 5090 /* ??? This is a named pattern like this is not allowed to FAIL based
5286 on its operands. */ 5091 on its operands. */
5287 if (GET_CODE (operands[2]) != CONST_INT 5092 if (GET_CODE (operands[2]) != CONST_INT
5406 } 5211 }
5407 else 5212 else
5408 return "rol%.w %2,%0"; 5213 return "rol%.w %2,%0";
5409 }) 5214 })
5410 5215
5411 (define_insn "" 5216 (define_insn "*rotlhi3_lowpart"
5412 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 5217 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5413 (rotate:HI (match_dup 0) 5218 (rotate:HI (match_dup 0)
5414 (match_operand:HI 1 "general_operand" "dIP")))] 5219 (match_operand:HI 1 "general_operand" "dIP")))]
5415 "!TARGET_COLDFIRE" 5220 "!TARGET_COLDFIRE"
5416 { 5221 {
5417 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8) 5222 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= 8)
5418 { 5223 {
5419 operands[2] = GEN_INT (16 - INTVAL (operands[2])); 5224 operands[1] = GEN_INT (16 - INTVAL (operands[1]));
5420 return "ror%.w %2,%0"; 5225 return "ror%.w %1,%0";
5421 } 5226 }
5422 else 5227 else
5423 return "rol%.w %2,%0"; 5228 return "rol%.w %1,%0";
5424 }) 5229 })
5425 5230
5426 (define_insn "rotlqi3" 5231 (define_insn "rotlqi3"
5427 [(set (match_operand:QI 0 "register_operand" "=d") 5232 [(set (match_operand:QI 0 "register_operand" "=d")
5428 (rotate:QI (match_operand:QI 1 "register_operand" "0") 5233 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5436 } 5241 }
5437 else 5242 else
5438 return "rol%.b %2,%0"; 5243 return "rol%.b %2,%0";
5439 }) 5244 })
5440 5245
5441 (define_insn "" 5246 (define_insn "*rotlqi3_lowpart"
5442 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 5247 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5443 (rotate:QI (match_dup 0) 5248 (rotate:QI (match_dup 0)
5444 (match_operand:QI 1 "general_operand" "dI")))] 5249 (match_operand:QI 1 "general_operand" "dI")))]
5445 "!TARGET_COLDFIRE" 5250 "!TARGET_COLDFIRE"
5446 { 5251 {
5447 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4) 5252 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= 4)
5448 { 5253 {
5449 operands[2] = GEN_INT (8 - INTVAL (operands[2])); 5254 operands[1] = GEN_INT (8 - INTVAL (operands[1]));
5450 return "ror%.b %2,%0"; 5255 return "ror%.b %1,%0";
5451 } 5256 }
5452 else 5257 else
5453 return "rol%.b %2,%0"; 5258 return "rol%.b %1,%0";
5454 }) 5259 })
5455 5260
5456 (define_insn "rotrsi3" 5261 (define_insn "rotrsi3"
5457 [(set (match_operand:SI 0 "register_operand" "=d") 5262 [(set (match_operand:SI 0 "register_operand" "=d")
5458 (rotatert:SI (match_operand:SI 1 "register_operand" "0") 5263 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5465 (rotatert:HI (match_operand:HI 1 "register_operand" "0") 5270 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5466 (match_operand:HI 2 "general_operand" "dI")))] 5271 (match_operand:HI 2 "general_operand" "dI")))]
5467 "!TARGET_COLDFIRE" 5272 "!TARGET_COLDFIRE"
5468 "ror%.w %2,%0") 5273 "ror%.w %2,%0")
5469 5274
5470 (define_insn "" 5275 (define_insn "rotrhi_lowpart"
5471 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 5276 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5472 (rotatert:HI (match_dup 0) 5277 (rotatert:HI (match_dup 0)
5473 (match_operand:HI 1 "general_operand" "dI")))] 5278 (match_operand:HI 1 "general_operand" "dI")))]
5474 "!TARGET_COLDFIRE" 5279 "!TARGET_COLDFIRE"
5475 "ror%.w %1,%0") 5280 "ror%.w %1,%0")
5485 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 5290 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5486 (rotatert:QI (match_dup 0) 5291 (rotatert:QI (match_dup 0)
5487 (match_operand:QI 1 "general_operand" "dI")))] 5292 (match_operand:QI 1 "general_operand" "dI")))]
5488 "!TARGET_COLDFIRE" 5293 "!TARGET_COLDFIRE"
5489 "ror%.b %1,%0") 5294 "ror%.b %1,%0")
5295
5296 (define_expand "bswapsi2"
5297 [(set (match_operand:SI 0 "register_operand")
5298 (bswap:SI (match_operand:SI 1 "register_operand")))]
5299 "!TARGET_COLDFIRE"
5300 {
5301 rtx x = operands[0];
5302 emit_move_insn (x, operands[1]);
5303 emit_insn (gen_rotrhi_lowpart (gen_lowpart (HImode, x), GEN_INT (8)));
5304 emit_insn (gen_rotlsi3 (x, x, GEN_INT (16)));
5305 emit_insn (gen_rotrhi_lowpart (gen_lowpart (HImode, x), GEN_INT (8)));
5306 DONE;
5307 })
5490 5308
5491 5309
5492 ;; Bit set/clear in memory byte. 5310 ;; Bit set/clear in memory byte.
5493 5311
5494 ;; set bit, bit number is int 5312 ;; set bit, bit number is int
5513 (match_dup 0)))] 5331 (match_dup 0)))]
5514 "" 5332 ""
5515 { 5333 {
5516 CC_STATUS_INIT; 5334 CC_STATUS_INIT;
5517 return "bset %1,%0"; 5335 return "bset %1,%0";
5336 }
5337 [(set_attr "type" "bitrw")])
5338
5339 (define_insn "*bsetdreg"
5340 [(set (match_operand:SI 0 "register_operand" "=d")
5341 (ior:SI (ashift:SI (const_int 1)
5342 (and:SI (match_operand:SI 1 "register_operand" "d")
5343 (const_int 31)))
5344 (match_operand:SI 2 "register_operand" "0")))]
5345 ""
5346 {
5347 CC_STATUS_INIT;
5348 return "bset %1,%0";
5349 }
5350 [(set_attr "type" "bitrw")])
5351
5352 (define_insn "*bchgdreg"
5353 [(set (match_operand:SI 0 "register_operand" "=d")
5354 (xor:SI (ashift:SI (const_int 1)
5355 (and:SI (match_operand:SI 1 "register_operand" "d")
5356 (const_int 31)))
5357 (match_operand:SI 2 "register_operand" "0")))]
5358 ""
5359 {
5360 CC_STATUS_INIT;
5361 return "bchg %1,%0";
5362 }
5363 [(set_attr "type" "bitrw")])
5364
5365 (define_insn "*bclrdreg"
5366 [(set (match_operand:SI 0 "register_operand" "=d")
5367 (and:SI (rotate:SI (const_int -2)
5368 (and:SI (match_operand:SI 1 "register_operand" "d")
5369 (const_int 31)))
5370 (match_operand:SI 2 "register_operand" "0")))]
5371 ""
5372 {
5373 CC_STATUS_INIT;
5374 return "bclr %1,%0";
5518 } 5375 }
5519 [(set_attr "type" "bitrw")]) 5376 [(set_attr "type" "bitrw")])
5520 5377
5521 ;; clear bit, bit number is int 5378 ;; clear bit, bit number is int
5522 (define_insn "bclrmemqi" 5379 (define_insn "bclrmemqi"
5557 ; alignment of structure members is specified. 5414 ; alignment of structure members is specified.
5558 ; 5415 ;
5559 ; The move is allowed to be odd byte aligned, because that's still faster 5416 ; The move is allowed to be odd byte aligned, because that's still faster
5560 ; than an odd byte aligned bit-field instruction. 5417 ; than an odd byte aligned bit-field instruction.
5561 ; 5418 ;
5562 (define_insn "" 5419 (define_insn "*insv_32_mem"
5563 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") 5420 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5564 (const_int 32) 5421 (const_int 32)
5565 (match_operand:SI 1 "const_int_operand" "n")) 5422 (match_operand:SI 1 "const_int_operand" "n"))
5566 (match_operand:SI 2 "general_src_operand" "rmSi"))] 5423 (match_operand:SI 2 "general_src_operand" "rmSi"))]
5567 "TARGET_68020 && TARGET_BITFIELD 5424 "TARGET_68020 && TARGET_BITFIELD
5568 && (INTVAL (operands[1]) % 8) == 0 5425 && (INTVAL (operands[1]) % 8) == 0
5569 && ! mode_dependent_address_p (XEXP (operands[0], 0))" 5426 && ! mode_dependent_address_p (XEXP (operands[0], 0),
5427 MEM_ADDR_SPACE (operands[0]))"
5570 { 5428 {
5571 operands[0] 5429 operands[0]
5572 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8); 5430 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
5573 5431
5574 return "move%.l %2,%0"; 5432 return "move%.l %2,%0";
5575 }) 5433 })
5576 5434
5577 (define_insn "" 5435 (define_insn "*insv_8_16_reg"
5578 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do") 5436 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5579 (match_operand:SI 1 "const_int_operand" "n") 5437 (match_operand:SI 1 "const_int_operand" "n")
5580 (match_operand:SI 2 "const_int_operand" "n")) 5438 (match_operand:SI 2 "const_int_operand" "n"))
5581 (match_operand:SI 3 "register_operand" "d"))] 5439 (match_operand:SI 3 "register_operand" "d"))]
5582 "TARGET_68020 && TARGET_BITFIELD 5440 "TARGET_68020 && TARGET_BITFIELD
5441 && IN_RANGE (INTVAL (operands[2]), 0, 31)
5583 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) 5442 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5584 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 5443 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0"
5585 && (GET_CODE (operands[0]) == REG 5444 {
5586 || ! mode_dependent_address_p (XEXP (operands[0], 0)))" 5445 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5587 { 5446 return "bfins %3,%0{%b2:%b1}";
5588 if (REG_P (operands[0]))
5589 {
5590 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5591 return "bfins %3,%0{%b2:%b1}";
5592 }
5593 else
5594 operands[0] = adjust_address (operands[0],
5595 INTVAL (operands[1]) == 8 ? QImode : HImode,
5596 INTVAL (operands[2]) / 8);
5597
5598 if (GET_CODE (operands[3]) == MEM)
5599 operands[3] = adjust_address (operands[3],
5600 INTVAL (operands[1]) == 8 ? QImode : HImode,
5601 (32 - INTVAL (operands[1])) / 8);
5602 5447
5603 if (INTVAL (operands[1]) == 8) 5448 if (INTVAL (operands[1]) == 8)
5604 return "move%.b %3,%0"; 5449 return "move%.b %3,%0";
5605 return "move%.w %3,%0"; 5450 return "move%.w %3,%0";
5606 }) 5451 })
5611 ; alignment of structure members is specified. 5456 ; alignment of structure members is specified.
5612 ; 5457 ;
5613 ; The move is allowed to be odd byte aligned, because that's still faster 5458 ; The move is allowed to be odd byte aligned, because that's still faster
5614 ; than an odd byte aligned bit-field instruction. 5459 ; than an odd byte aligned bit-field instruction.
5615 ; 5460 ;
5616 (define_insn "" 5461 (define_insn "*extzv_32_mem"
5617 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 5462 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5618 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS") 5463 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5619 (const_int 32) 5464 (const_int 32)
5620 (match_operand:SI 2 "const_int_operand" "n")))] 5465 (match_operand:SI 2 "const_int_operand" "n")))]
5621 "TARGET_68020 && TARGET_BITFIELD 5466 "TARGET_68020 && TARGET_BITFIELD
5622 && (INTVAL (operands[2]) % 8) == 0 5467 && (INTVAL (operands[2]) % 8) == 0
5623 && ! mode_dependent_address_p (XEXP (operands[1], 0))" 5468 && ! mode_dependent_address_p (XEXP (operands[1], 0),
5469 MEM_ADDR_SPACE (operands[1]))"
5624 { 5470 {
5625 operands[1] 5471 operands[1]
5626 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8); 5472 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5627 5473
5628 return "move%.l %1,%0"; 5474 return "move%.l %1,%0";
5629 }) 5475 })
5630 5476
5631 (define_insn "" 5477 (define_insn "*extzv_8_16_reg"
5632 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d") 5478 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
5633 (zero_extract:SI (match_operand:SI 1 "register_operand" "do") 5479 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5634 (match_operand:SI 2 "const_int_operand" "n") 5480 (match_operand:SI 2 "const_int_operand" "n")
5635 (match_operand:SI 3 "const_int_operand" "n")))] 5481 (match_operand:SI 3 "const_int_operand" "n")))]
5636 "TARGET_68020 && TARGET_BITFIELD 5482 "TARGET_68020 && TARGET_BITFIELD
5483 && IN_RANGE (INTVAL (operands[3]), 0, 31)
5637 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 5484 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5638 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 5485 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
5639 && (GET_CODE (operands[1]) == REG
5640 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5641 { 5486 {
5642 cc_status.flags |= CC_NOT_NEGATIVE; 5487 cc_status.flags |= CC_NOT_NEGATIVE;
5643 if (REG_P (operands[1])) 5488 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5644 { 5489 return "bfextu %1{%b3:%b2},%0";
5645 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5646 return "bfextu %1{%b3:%b2},%0";
5647 }
5648 else
5649 operands[1]
5650 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
5651 5490
5652 output_asm_insn ("clr%.l %0", operands); 5491 output_asm_insn ("clr%.l %0", operands);
5653 if (GET_CODE (operands[0]) == MEM)
5654 operands[0] = adjust_address (operands[0],
5655 INTVAL (operands[2]) == 8 ? QImode : HImode,
5656 (32 - INTVAL (operands[1])) / 8);
5657
5658 if (INTVAL (operands[2]) == 8) 5492 if (INTVAL (operands[2]) == 8)
5659 return "move%.b %1,%0"; 5493 return "move%.b %1,%0";
5660 return "move%.w %1,%0"; 5494 return "move%.w %1,%0";
5661 }) 5495 })
5662 5496
5665 ; alignment of structure members is specified. 5499 ; alignment of structure members is specified.
5666 ; 5500 ;
5667 ; The move is allowed to be odd byte aligned, because that's still faster 5501 ; The move is allowed to be odd byte aligned, because that's still faster
5668 ; than an odd byte aligned bit-field instruction. 5502 ; than an odd byte aligned bit-field instruction.
5669 ; 5503 ;
5670 (define_insn "" 5504 (define_insn "*extv_32_mem"
5671 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 5505 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5672 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS") 5506 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5673 (const_int 32) 5507 (const_int 32)
5674 (match_operand:SI 2 "const_int_operand" "n")))] 5508 (match_operand:SI 2 "const_int_operand" "n")))]
5675 "TARGET_68020 && TARGET_BITFIELD 5509 "TARGET_68020 && TARGET_BITFIELD
5676 && (INTVAL (operands[2]) % 8) == 0 5510 && (INTVAL (operands[2]) % 8) == 0
5677 && ! mode_dependent_address_p (XEXP (operands[1], 0))" 5511 && ! mode_dependent_address_p (XEXP (operands[1], 0),
5512 MEM_ADDR_SPACE (operands[1]))"
5678 { 5513 {
5679 operands[1] 5514 operands[1]
5680 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8); 5515 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5681 5516
5682 return "move%.l %1,%0"; 5517 return "move%.l %1,%0";
5683 }) 5518 })
5684 5519
5685 (define_insn "" 5520 (define_insn "*extv_8_16_reg"
5686 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 5521 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5687 (sign_extract:SI (match_operand:SI 1 "register_operand" "do") 5522 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5688 (match_operand:SI 2 "const_int_operand" "n") 5523 (match_operand:SI 2 "const_int_operand" "n")
5689 (match_operand:SI 3 "const_int_operand" "n")))] 5524 (match_operand:SI 3 "const_int_operand" "n")))]
5690 "TARGET_68020 && TARGET_BITFIELD 5525 "TARGET_68020 && TARGET_BITFIELD
5526 && IN_RANGE (INTVAL (operands[3]), 0, 31)
5691 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 5527 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5692 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 5528 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
5693 && (GET_CODE (operands[1]) == REG 5529 {
5694 || ! mode_dependent_address_p (XEXP (operands[1], 0)))" 5530 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5695 { 5531 return "bfexts %1{%b3:%b2},%0";
5696 if (REG_P (operands[1]))
5697 {
5698 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5699 return "bfexts %1{%b3:%b2},%0";
5700 }
5701 else
5702 operands[1]
5703 = adjust_address (operands[1],
5704 INTVAL (operands[2]) == 8 ? QImode : HImode,
5705 INTVAL (operands[3]) / 8);
5706 5532
5707 if (INTVAL (operands[2]) == 8) 5533 if (INTVAL (operands[2]) == 8)
5708 return "move%.b %1,%0\;extb%.l %0"; 5534 return "move%.b %1,%0\;extb%.l %0";
5709 return "move%.w %1,%0\;ext%.l %0"; 5535 return "move%.w %1,%0\;ext%.l %0";
5710 }) 5536 })
5719 (match_operand:SI 2 "const_int_operand" "") 5545 (match_operand:SI 2 "const_int_operand" "")
5720 (match_operand:SI 3 "const_int_operand" "")))] 5546 (match_operand:SI 3 "const_int_operand" "")))]
5721 "TARGET_68020 && TARGET_BITFIELD" 5547 "TARGET_68020 && TARGET_BITFIELD"
5722 "") 5548 "")
5723 5549
5724 (define_insn "" 5550 (define_insn "*extv_bfexts_mem"
5725 [(set (match_operand:SI 0 "register_operand" "=d") 5551 [(set (match_operand:SI 0 "register_operand" "=d")
5726 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o") 5552 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5727 (match_operand:SI 2 "nonmemory_operand" "dn") 5553 (match_operand:SI 2 "nonmemory_operand" "dn")
5728 (match_operand:SI 3 "nonmemory_operand" "dn")))] 5554 (match_operand:SI 3 "nonmemory_operand" "dn")))]
5729 "TARGET_68020 && TARGET_BITFIELD" 5555 "TARGET_68020 && TARGET_BITFIELD"
5735 (match_operand:SI 2 "const_int_operand" "") 5561 (match_operand:SI 2 "const_int_operand" "")
5736 (match_operand:SI 3 "const_int_operand" "")))] 5562 (match_operand:SI 3 "const_int_operand" "")))]
5737 "TARGET_68020 && TARGET_BITFIELD" 5563 "TARGET_68020 && TARGET_BITFIELD"
5738 "") 5564 "")
5739 5565
5740 (define_insn "" 5566 (define_insn "*extzv_bfextu_mem"
5741 [(set (match_operand:SI 0 "register_operand" "=d") 5567 [(set (match_operand:SI 0 "register_operand" "=d")
5742 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o") 5568 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5743 (match_operand:SI 2 "nonmemory_operand" "dn") 5569 (match_operand:SI 2 "nonmemory_operand" "dn")
5744 (match_operand:SI 3 "nonmemory_operand" "dn")))] 5570 (match_operand:SI 3 "nonmemory_operand" "dn")))]
5745 "TARGET_68020 && TARGET_BITFIELD" 5571 "TARGET_68020 && TARGET_BITFIELD"
5754 CC_STATUS_INIT; 5580 CC_STATUS_INIT;
5755 } 5581 }
5756 return "bfextu %1{%b3:%b2},%0"; 5582 return "bfextu %1{%b3:%b2},%0";
5757 }) 5583 })
5758 5584
5759 (define_insn "" 5585 (define_insn "*insv_bfchg_mem"
5760 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") 5586 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5761 (match_operand:SI 1 "nonmemory_operand" "dn") 5587 (match_operand:SI 1 "nonmemory_operand" "dn")
5762 (match_operand:SI 2 "nonmemory_operand" "dn")) 5588 (match_operand:SI 2 "nonmemory_operand" "dn"))
5763 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)) 5589 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5764 (match_operand 3 "const_int_operand" "n")))] 5590 (match_operand 3 "const_int_operand" "n")))]
5769 { 5595 {
5770 CC_STATUS_INIT; 5596 CC_STATUS_INIT;
5771 return "bfchg %0{%b2:%b1}"; 5597 return "bfchg %0{%b2:%b1}";
5772 }) 5598 })
5773 5599
5774 (define_insn "" 5600 (define_insn "*insv_bfclr_mem"
5775 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") 5601 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5776 (match_operand:SI 1 "nonmemory_operand" "dn") 5602 (match_operand:SI 1 "nonmemory_operand" "dn")
5777 (match_operand:SI 2 "nonmemory_operand" "dn")) 5603 (match_operand:SI 2 "nonmemory_operand" "dn"))
5778 (const_int 0))] 5604 (const_int 0))]
5779 "TARGET_68020 && TARGET_BITFIELD" 5605 "TARGET_68020 && TARGET_BITFIELD"
5780 { 5606 {
5781 CC_STATUS_INIT; 5607 CC_STATUS_INIT;
5782 return "bfclr %0{%b2:%b1}"; 5608 return "bfclr %0{%b2:%b1}";
5783 }) 5609 })
5784 5610
5785 (define_insn "" 5611 (define_insn "*insv_bfset_mem"
5786 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") 5612 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5787 (match_operand:SI 1 "general_operand" "dn") 5613 (match_operand:SI 1 "general_operand" "dn")
5788 (match_operand:SI 2 "general_operand" "dn")) 5614 (match_operand:SI 2 "general_operand" "dn"))
5789 (const_int -1))] 5615 (const_int -1))]
5790 "TARGET_68020 && TARGET_BITFIELD" 5616 "TARGET_68020 && TARGET_BITFIELD"
5795 5621
5796 (define_expand "insv" 5622 (define_expand "insv"
5797 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "") 5623 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
5798 (match_operand:SI 1 "const_int_operand" "") 5624 (match_operand:SI 1 "const_int_operand" "")
5799 (match_operand:SI 2 "const_int_operand" "")) 5625 (match_operand:SI 2 "const_int_operand" ""))
5800 (match_operand:SI 3 "register_operand" ""))] 5626 (match_operand:SI 3 "reg_or_pow2_m1_operand" ""))]
5801 "TARGET_68020 && TARGET_BITFIELD" 5627 "TARGET_68020 && TARGET_BITFIELD"
5802 "") 5628 "
5803 5629 {
5804 (define_insn "" 5630 /* Special case initializing a field to all ones. */
5631 if (GET_CODE (operands[3]) == CONST_INT)
5632 {
5633 if (exact_log2 (INTVAL (operands[3]) + 1) != INTVAL (operands[1]))
5634 operands[3] = force_reg (SImode, operands[3]);
5635 else
5636 operands[3] = constm1_rtx;
5637
5638 }
5639 }")
5640
5641 (define_insn "*insv_bfins_mem"
5805 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") 5642 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5806 (match_operand:SI 1 "nonmemory_operand" "dn") 5643 (match_operand:SI 1 "nonmemory_operand" "dn")
5807 (match_operand:SI 2 "nonmemory_operand" "dn")) 5644 (match_operand:SI 2 "nonmemory_operand" "dn"))
5808 (match_operand:SI 3 "register_operand" "d"))] 5645 (match_operand:SI 3 "register_operand" "d"))]
5809 "TARGET_68020 && TARGET_BITFIELD" 5646 "TARGET_68020 && TARGET_BITFIELD"
5810 "bfins %3,%0{%b2:%b1}") 5647 "bfins %3,%0{%b2:%b1}")
5811 5648
5812 ;; Now recognize bit-field insns that operate on registers 5649 ;; Now recognize bit-field insns that operate on registers
5813 ;; (or at least were intended to do so). 5650 ;; (or at least were intended to do so).
5814 5651
5815 (define_insn "" 5652 (define_insn "*extv_bfexts_reg"
5816 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 5653 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5817 (sign_extract:SI (match_operand:SI 1 "register_operand" "d") 5654 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5818 (match_operand:SI 2 "const_int_operand" "n") 5655 (match_operand:SI 2 "const_int_operand" "n")
5819 (match_operand:SI 3 "const_int_operand" "n")))] 5656 (match_operand:SI 3 "const_int_operand" "n")))]
5820 "TARGET_68020 && TARGET_BITFIELD" 5657 "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[3]), 0, 31)"
5821 "bfexts %1{%b3:%b2},%0") 5658 "bfexts %1{%b3:%b2},%0")
5822 5659
5823 (define_insn "" 5660 (define_insn "*extv_bfextu_reg"
5824 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 5661 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5825 (zero_extract:SI (match_operand:SI 1 "register_operand" "d") 5662 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5826 (match_operand:SI 2 "const_int_operand" "n") 5663 (match_operand:SI 2 "const_int_operand" "n")
5827 (match_operand:SI 3 "const_int_operand" "n")))] 5664 (match_operand:SI 3 "const_int_operand" "n")))]
5828 "TARGET_68020 && TARGET_BITFIELD" 5665 "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[3]), 0, 31)"
5829 { 5666 {
5830 if (GET_CODE (operands[2]) == CONST_INT) 5667 if (GET_CODE (operands[2]) == CONST_INT)
5831 { 5668 {
5832 if (INTVAL (operands[2]) != 32) 5669 if (INTVAL (operands[2]) != 32)
5833 cc_status.flags |= CC_NOT_NEGATIVE; 5670 cc_status.flags |= CC_NOT_NEGATIVE;
5837 CC_STATUS_INIT; 5674 CC_STATUS_INIT;
5838 } 5675 }
5839 return "bfextu %1{%b3:%b2},%0"; 5676 return "bfextu %1{%b3:%b2},%0";
5840 }) 5677 })
5841 5678
5842 (define_insn "" 5679 (define_insn "*insv_bfclr_reg"
5843 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d") 5680 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5844 (match_operand:SI 1 "const_int_operand" "n") 5681 (match_operand:SI 1 "const_int_operand" "n")
5845 (match_operand:SI 2 "const_int_operand" "n")) 5682 (match_operand:SI 2 "const_int_operand" "n"))
5846 (const_int 0))] 5683 (const_int 0))]
5847 "TARGET_68020 && TARGET_BITFIELD" 5684 "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[2]), 0, 31)"
5848 { 5685 {
5849 CC_STATUS_INIT; 5686 CC_STATUS_INIT;
5850 return "bfclr %0{%b2:%b1}"; 5687 return "bfclr %0{%b2:%b1}";
5851 }) 5688 })
5852 5689
5853 (define_insn "" 5690 (define_insn "*insv_bfset_reg"
5854 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d") 5691 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5855 (match_operand:SI 1 "const_int_operand" "n") 5692 (match_operand:SI 1 "const_int_operand" "n")
5856 (match_operand:SI 2 "const_int_operand" "n")) 5693 (match_operand:SI 2 "const_int_operand" "n"))
5857 (const_int -1))] 5694 (const_int -1))]
5858 "TARGET_68020 && TARGET_BITFIELD" 5695 "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[2]), 0, 31)"
5859 { 5696 {
5860 CC_STATUS_INIT; 5697 CC_STATUS_INIT;
5861 return "bfset %0{%b2:%b1}"; 5698 return "bfset %0{%b2:%b1}";
5862 }) 5699 })
5863 5700
5864 (define_insn "" 5701 (define_insn "*insv_bfins_reg"
5865 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d") 5702 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5866 (match_operand:SI 1 "const_int_operand" "n") 5703 (match_operand:SI 1 "const_int_operand" "n")
5867 (match_operand:SI 2 "const_int_operand" "n")) 5704 (match_operand:SI 2 "const_int_operand" "n"))
5868 (match_operand:SI 3 "register_operand" "d"))] 5705 (match_operand:SI 3 "register_operand" "d"))]
5869 "TARGET_68020 && TARGET_BITFIELD" 5706 "TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[2]), 0, 31)"
5870 { 5707 {
5871 #if 0 5708 #if 0
5872 /* These special cases are now recognized by a specific pattern. */ 5709 /* These special cases are now recognized by a specific pattern. */
5873 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT 5710 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5874 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16) 5711 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5880 return "bfins %3,%0{%b2:%b1}"; 5717 return "bfins %3,%0{%b2:%b1}";
5881 }) 5718 })
5882 5719
5883 ;; Special patterns for optimizing bit-field instructions. 5720 ;; Special patterns for optimizing bit-field instructions.
5884 5721
5885 (define_insn "" 5722 (define_insn "*tst_bftst_mem"
5886 [(set (cc0) 5723 [(set (cc0)
5887 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") 5724 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5888 (match_operand:SI 1 "const_int_operand" "n") 5725 (match_operand:SI 1 "const_int_operand" "n")
5889 (match_operand:SI 2 "general_operand" "dn")) 5726 (match_operand:SI 2 "general_operand" "dn"))
5890 (const_int 0)))] 5727 (const_int 0)))]
5906 return "bftst %0{%b2:%b1}"; 5743 return "bftst %0{%b2:%b1}";
5907 }) 5744 })
5908 5745
5909 5746
5910 ;;; now handle the register cases 5747 ;;; now handle the register cases
5911 (define_insn "" 5748 (define_insn "*tst_bftst_reg"
5912 [(set (cc0) 5749 [(set (cc0)
5913 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") 5750 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5914 (match_operand:SI 1 "const_int_operand" "n") 5751 (match_operand:SI 1 "const_int_operand" "n")
5915 (match_operand:SI 2 "general_operand" "dn")) 5752 (match_operand:SI 2 "general_operand" "dn"))
5916 (const_int 0)))] 5753 (const_int 0)))]
5917 "TARGET_68020 && TARGET_BITFIELD" 5754 "TARGET_68020 && TARGET_BITFIELD
5755 && !(CONST_INT_P (operands[2]) && !IN_RANGE (INTVAL (operands[2]), 0, 31))"
5918 { 5756 {
5919 if (operands[1] == const1_rtx 5757 if (operands[1] == const1_rtx
5920 && GET_CODE (operands[2]) == CONST_INT) 5758 && GET_CODE (operands[2]) == CONST_INT)
5921 { 5759 {
5922 int width = GET_CODE (operands[0]) == REG ? 31 : 7; 5760 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
6175 6013
6176 ;; Basic conditional jump instructions. 6014 ;; Basic conditional jump instructions.
6177 6015
6178 (define_insn "beq0_di" 6016 (define_insn "beq0_di"
6179 [(set (pc) 6017 [(set (pc)
6180 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>") 6018 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*a,o,<>")
6181 (const_int 0)) 6019 (const_int 0))
6182 (label_ref (match_operand 1 "" ",")) 6020 (label_ref (match_operand 1 "" ",,"))
6183 (pc))) 6021 (pc)))
6184 (clobber (match_scratch:SI 2 "=d,d"))] 6022 (clobber (match_scratch:SI 2 "=d,&d,d"))]
6185 "" 6023 ""
6186 { 6024 {
6187 CC_STATUS_INIT; 6025 CC_STATUS_INIT;
6188 if (which_alternative == 1) 6026 if (which_alternative == 2)
6189 return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1"; 6027 return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1";
6190 if ((cc_prev_status.value1 6028 if ((cc_prev_status.value1
6191 && rtx_equal_p (cc_prev_status.value1, operands[0])) 6029 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6192 || (cc_prev_status.value2 6030 || (cc_prev_status.value2
6193 && rtx_equal_p (cc_prev_status.value2, operands[0]))) 6031 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6220 return ""; 6058 return "";
6221 }) 6059 })
6222 6060
6223 (define_insn "bne0_di" 6061 (define_insn "bne0_di"
6224 [(set (pc) 6062 [(set (pc)
6225 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a") 6063 (if_then_else (ne (match_operand:DI 0 "general_operand" "d,o,*a")
6226 (const_int 0)) 6064 (const_int 0))
6227 (label_ref (match_operand 1 "" ",")) 6065 (label_ref (match_operand 1 "" ",,"))
6228 (pc))) 6066 (pc)))
6229 (clobber (match_scratch:SI 2 "=d,X"))] 6067 (clobber (match_scratch:SI 2 "=d,&d,X"))]
6230 "" 6068 ""
6231 { 6069 {
6232 if ((cc_prev_status.value1 6070 if ((cc_prev_status.value1
6233 && rtx_equal_p (cc_prev_status.value1, operands[0])) 6071 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6234 || (cc_prev_status.value2 6072 || (cc_prev_status.value2
6321 (pc)))] 6159 (pc)))]
6322 "" 6160 ""
6323 { 6161 {
6324 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0"); 6162 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
6325 } 6163 }
6326 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))]) 6164 [(set_attr "type" "bcc")])
6327 6165
6328 (define_insn "bne" 6166 (define_insn "bne"
6329 [(set (pc) 6167 [(set (pc)
6330 (if_then_else (ne (cc0) 6168 (if_then_else (ne (cc0)
6331 (const_int 0)) 6169 (const_int 0))
6333 (pc)))] 6171 (pc)))]
6334 "" 6172 ""
6335 { 6173 {
6336 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0"); 6174 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
6337 } 6175 }
6338 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))]) 6176 [(set_attr "type" "bcc")])
6339 6177
6340 (define_insn "bgt" 6178 (define_insn "bgt"
6341 [(set (pc) 6179 [(set (pc)
6342 (if_then_else (gt (cc0) 6180 (if_then_else (gt (cc0)
6343 (const_int 0)) 6181 (const_int 0))
6351 return 0; 6189 return 0;
6352 } 6190 }
6353 6191
6354 OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0); 6192 OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
6355 } 6193 }
6356 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))]) 6194 [(set_attr "type" "bcc")])
6357 6195
6358 (define_insn "bgtu" 6196 (define_insn "bgtu"
6359 [(set (pc) 6197 [(set (pc)
6360 (if_then_else (gtu (cc0) 6198 (if_then_else (gtu (cc0)
6361 (const_int 0)) 6199 (const_int 0))
6387 return 0; 6225 return 0;
6388 } 6226 }
6389 6227
6390 OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0"); 6228 OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
6391 } 6229 }
6392 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))]) 6230 [(set_attr "type" "bcc")])
6393 6231
6394 (define_insn "bltu" 6232 (define_insn "bltu"
6395 [(set (pc) 6233 [(set (pc)
6396 (if_then_else (ltu (cc0) 6234 (if_then_else (ltu (cc0)
6397 (const_int 0)) 6235 (const_int 0))
6853 (define_expand "tablejump" 6691 (define_expand "tablejump"
6854 [(parallel [(set (pc) (match_operand 0 "" "")) 6692 [(parallel [(set (pc) (match_operand 0 "" ""))
6855 (use (label_ref (match_operand 1 "" "")))])] 6693 (use (label_ref (match_operand 1 "" "")))])]
6856 "" 6694 ""
6857 { 6695 {
6858 #ifdef CASE_VECTOR_PC_RELATIVE 6696 #if CASE_VECTOR_PC_RELATIVE
6859 operands[0] = gen_rtx_PLUS (SImode, pc_rtx, 6697 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6860 gen_rtx_SIGN_EXTEND (SImode, operands[0])); 6698 TARGET_LONG_JUMP_TABLE_OFFSETS
6699 ? operands[0]
6700 : gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6861 #endif 6701 #endif
6862 }) 6702 })
6863 6703
6864 ;; Jump to variable address from dispatch table of absolute addresses. 6704 ;; Jump to variable address from dispatch table of absolute addresses.
6865 (define_insn "*tablejump_internal" 6705 (define_insn "*tablejump_internal"
6870 return MOTOROLA ? "jmp (%0)" : "jmp %0@"; 6710 return MOTOROLA ? "jmp (%0)" : "jmp %0@";
6871 } 6711 }
6872 [(set_attr "type" "jmp")]) 6712 [(set_attr "type" "jmp")])
6873 6713
6874 ;; Jump to variable address from dispatch table of relative addresses. 6714 ;; Jump to variable address from dispatch table of relative addresses.
6875 (define_insn "" 6715 (define_insn "*tablejump_pcrel_si"
6716 [(set (pc)
6717 (plus:SI (pc)
6718 (match_operand:SI 0 "register_operand" "r")))
6719 (use (label_ref (match_operand 1 "" "")))]
6720 "TARGET_LONG_JUMP_TABLE_OFFSETS"
6721 {
6722 #ifdef ASM_RETURN_CASE_JUMP
6723 ASM_RETURN_CASE_JUMP;
6724 #else
6725 return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)";
6726 #endif
6727 })
6728
6729 (define_insn "*tablejump_pcrel_hi"
6876 [(set (pc) 6730 [(set (pc)
6877 (plus:SI (pc) 6731 (plus:SI (pc)
6878 (sign_extend:SI (match_operand:HI 0 "register_operand" "r")))) 6732 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6879 (use (label_ref (match_operand 1 "" "")))] 6733 (use (label_ref (match_operand 1 "" "")))]
6880 "" 6734 "!TARGET_LONG_JUMP_TABLE_OFFSETS"
6881 { 6735 {
6882 #ifdef ASM_RETURN_CASE_JUMP 6736 #ifdef ASM_RETURN_CASE_JUMP
6883 ASM_RETURN_CASE_JUMP; 6737 ASM_RETURN_CASE_JUMP;
6884 #else 6738 #else
6885 if (TARGET_COLDFIRE) 6739 if (TARGET_COLDFIRE)
7109 (match_operand 2 "" "")])] 6963 (match_operand 2 "" "")])]
7110 "NEEDS_UNTYPED_CALL" 6964 "NEEDS_UNTYPED_CALL"
7111 { 6965 {
7112 int i; 6966 int i;
7113 6967
7114 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); 6968 emit_call_insn (gen_call (operands[0], const0_rtx));
7115 6969
7116 for (i = 0; i < XVECLEN (operands[2], 0); i++) 6970 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7117 { 6971 {
7118 rtx set = XVECEXP (operands[2], 0, i); 6972 rtx set = XVECEXP (operands[2], 0, i);
7119 emit_move_insn (SET_DEST (set), SET_SRC (set)); 6973 emit_move_insn (SET_DEST (set), SET_SRC (set));
7241 (set (reg:SI SP_REG) 7095 (set (reg:SI SP_REG)
7242 (plus:SI (reg:SI SP_REG) 7096 (plus:SI (reg:SI SP_REG)
7243 (match_operand:SI 1 "const_int_operand")))])] 7097 (match_operand:SI 1 "const_int_operand")))])]
7244 "TARGET_68020 || INTVAL (operands[1]) >= -0x8004" 7098 "TARGET_68020 || INTVAL (operands[1]) >= -0x8004"
7245 { 7099 {
7246 operands[2] = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, -4)); 7100 operands[2] = gen_frame_mem (SImode,
7101 plus_constant (Pmode, stack_pointer_rtx, -4));
7247 }) 7102 })
7248 7103
7249 (define_insn "*link" 7104 (define_insn "*link"
7250 [(set (match_operand:SI 0 "register_operand" "+r") 7105 [(set (match_operand:SI 0 "register_operand" "+r")
7251 (plus:SI (reg:SI SP_REG) (const_int -4))) 7106 (plus:SI (reg:SI SP_REG) (const_int -4)))
7804 "" 7659 ""
7805 "#" 7660 "#"
7806 [(set_attr "type" "ib")]) 7661 [(set_attr "type" "ib")])
7807 7662
7808 (include "cf.md") 7663 (include "cf.md")
7664 (include "sync.md")
7665
7666 ;; Convert
7667 ;;
7668 ;; move.l 4(%a0),%a0
7669 ;; clr.b (%a0,%a1.l)
7670 ;;
7671 ;; into
7672 ;;
7673 ;; add.l 4(%a0),%a1
7674 ;; clr.b (%a1)
7675 ;;
7676 ;; The latter is smaller. It is faster on all models except m68060.
7677
7678 (define_peephole2
7679 [(set (match_operand:SI 0 "register_operand" "")
7680 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "")
7681 (match_operand:SI 2 "const_int_operand" ""))))
7682 (set (mem:QI (plus:SI (match_operand:SI 3 "register_operand" "")
7683 (match_operand:SI 4 "register_operand" "")))
7684 (const_int 0))]
7685 "(optimize_size || !TUNE_68060)
7686 && (operands[0] == operands[3] || operands[0] == operands[4])
7687 && ADDRESS_REG_P (operands[1])
7688 && ADDRESS_REG_P ((operands[0] == operands[3]) ? operands[4] : operands[3])
7689 && peep2_reg_dead_p (2, operands[3])
7690 && peep2_reg_dead_p (2, operands[4])"
7691 [(set (match_dup 5)
7692 (plus:SI (match_dup 5)
7693 (mem:SI (plus:SI (match_dup 1)
7694 (match_dup 2)))))
7695 (set (mem:QI (match_dup 5))
7696 (const_int 0))]
7697 "operands[5] = (operands[0] == operands[3]) ? operands[4] : operands[3];")
7698
7699 ;; We want to turn
7700 ;; moveq const,dX
7701 ;; cmp.l dX,dY
7702 ;; je/jne
7703 ;;
7704 ;; into
7705 ;; addq/subq -const,dY
7706 ;; cmp.l dY, 0
7707 ;; je/jne
7708 ;;
7709 ;; dX and dY must both be dead at the end of the sequence and the constant
7710 ;; must be valid for addq/subq.
7711 ;;
7712 ;; Essentially we're making it trivial for final to realize the comparison
7713 ;; is not needed
7714 ;;
7715 ;; Testing has shown a variant where the operands are reversed in the
7716 ;; comparison never hits, so I have not included that variant.
7717 ;;
7718
7719 (define_peephole2
7720 [(set (match_operand:SI 0 "register_operand" "")
7721 (match_operand:SI 1 "addq_subq_operand" ""))
7722 (set (cc0) (compare (match_operand:SI 2 "register_operand" "")
7723 (match_dup 0)))
7724 (set (pc) (if_then_else (match_operator 5 "equality_comparison_operator"
7725 [(cc0) (const_int 0)])
7726 (match_operand 3 "pc_or_label_operand")
7727 (match_operand 4 "pc_or_label_operand")))]
7728 "peep2_reg_dead_p (2, operands[0])
7729 && peep2_reg_dead_p (2, operands[2])
7730 && (operands[3] == pc_rtx || operands[4] == pc_rtx)
7731 && DATA_REG_P (operands[2])
7732 && !rtx_equal_p (operands[0], operands[2])"
7733 [(set (match_dup 2) (plus:SI (match_dup 2) (match_dup 6)))
7734 (set (cc0) (compare (match_dup 2) (const_int 0)))
7735 (set (pc) (if_then_else (match_op_dup 5 [(cc0) (const_int 0)])
7736 (match_dup 3)
7737 (match_dup 4)))]
7738 "operands[6] = GEN_INT (-INTVAL (operands[1]));")
7739
7740 (define_peephole2
7741 [(set (match_operand:SI 0 "register_operand" "")
7742 (match_operand:SI 1 "pow2_m1_operand" ""))
7743 (set (cc0) (compare (match_operand:SI 2 "register_operand" "")
7744 (match_operand:SI 3 "register_operand" "")))
7745 (set (pc) (if_then_else (gtu (cc0) (const_int 0))
7746 (match_operand 4 "pc_or_label_operand")
7747 (match_operand 5 "pc_or_label_operand")))]
7748 "INTVAL (operands[1]) <= 255
7749 && operands[0] == operands[3]
7750 && peep2_reg_dead_p (2, operands[0])
7751 && peep2_reg_dead_p (2, operands[2])
7752 && (operands[4] == pc_rtx || operands[5] == pc_rtx)
7753 && (optimize_size || TUNE_68040_60)
7754 && DATA_REG_P (operands[2])"
7755 [(set (match_dup 7) (lshiftrt:SI (match_dup 7) (match_dup 6)))
7756 (set (cc0) (compare (match_dup 7) (const_int 0)))
7757 (set (pc) (if_then_else (ne (cc0) (const_int 0))
7758 (match_dup 4) (match_dup 5)))]
7759 "
7760 {
7761 operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
7762 operands[7] = operands[2];
7763 }")
7764
7765 (define_peephole2
7766 [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
7767 (match_operand:SI 1 "pow2_m1_operand" "")))
7768 (set (pc) (if_then_else (gtu (cc0) (const_int 0))
7769 (match_operand 2 "pc_or_label_operand")
7770 (match_operand 3 "pc_or_label_operand")))]
7771 "INTVAL (operands[1]) <= 255
7772 && peep2_reg_dead_p (1, operands[0])
7773 && (operands[2] == pc_rtx || operands[3] == pc_rtx)
7774 && (optimize_size || TUNE_68040_60)
7775 && DATA_REG_P (operands[0])"
7776 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 4)))
7777 (set (cc0) (compare (match_dup 0) (const_int 0)))
7778 (set (pc) (if_then_else (ne (cc0) (const_int 0))
7779 (match_dup 2) (match_dup 3)))]
7780 "{ operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); }")
7781
7782 (define_peephole2
7783 [(set (match_operand:SI 0 "register_operand" "")
7784 (match_operand:SI 1 "pow2_m1_operand" ""))
7785 (set (cc0) (compare (match_operand:SI 2 "register_operand" "")
7786 (match_operand:SI 3 "register_operand" "")))
7787 (set (pc) (if_then_else (leu (cc0) (const_int 0))
7788 (match_operand 4 "pc_or_label_operand")
7789 (match_operand 5 "pc_or_label_operand")))]
7790 "INTVAL (operands[1]) <= 255
7791 && operands[0] == operands[3]
7792 && peep2_reg_dead_p (2, operands[0])
7793 && peep2_reg_dead_p (2, operands[2])
7794 && (operands[4] == pc_rtx || operands[5] == pc_rtx)
7795 && (optimize_size || TUNE_68040_60)
7796 && DATA_REG_P (operands[2])"
7797 [(set (match_dup 7) (lshiftrt:SI (match_dup 7) (match_dup 6)))
7798 (set (cc0) (compare (match_dup 7) (const_int 0)))
7799 (set (pc) (if_then_else (eq (cc0) (const_int 0))
7800 (match_dup 4) (match_dup 5)))]
7801 "
7802 {
7803 operands[6] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1));
7804 operands[7] = operands[2];
7805 }")
7806 (define_peephole2
7807 [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
7808 (match_operand:SI 1 "pow2_m1_operand" "")))
7809 (set (pc) (if_then_else (leu (cc0) (const_int 0))
7810 (match_operand 2 "pc_or_label_operand")
7811 (match_operand 3 "pc_or_label_operand")))]
7812 "INTVAL (operands[1]) <= 255
7813 && peep2_reg_dead_p (1, operands[0])
7814 && (operands[2] == pc_rtx || operands[3] == pc_rtx)
7815 && (optimize_size || TUNE_68040_60)
7816 && DATA_REG_P (operands[0])"
7817 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 4)))
7818 (set (cc0) (compare (match_dup 0) (const_int 0)))
7819 (set (pc) (if_then_else (eq (cc0) (const_int 0))
7820 (match_dup 2) (match_dup 3)))]
7821 "{ operands[4] = GEN_INT (exact_log2 (INTVAL (operands[1]) + 1)); }")
7822
7823 ;; When optimizing for size or for the original 68000 or 68010, we can
7824 ;; improve some relational tests against 65536 (which get canonicalized
7825 ;; internally against 65535).
7826 ;; The rotate in the output pattern will turn into a swap.
7827 (define_peephole2
7828 [(set (cc0) (compare (match_operand:SI 0 "register_operand" "")
7829 (const_int 65535)))
7830 (set (pc) (if_then_else (match_operator 1 "swap_peephole_relational_operator"
7831 [(cc0) (const_int 0)])
7832 (match_operand 2 "pc_or_label_operand")
7833 (match_operand 3 "pc_or_label_operand")))]
7834 "peep2_reg_dead_p (1, operands[0])
7835 && (operands[2] == pc_rtx || operands[3] == pc_rtx)
7836 && (optimize_size || TUNE_68000_10)
7837 && DATA_REG_P (operands[0])"
7838 [(set (match_dup 0) (rotate:SI (match_dup 0) (const_int 16)))
7839 (set (cc0) (compare (subreg:HI (match_dup 0) 2) (const_int 0)))
7840 (set (pc) (if_then_else (match_op_dup 1 [(cc0) (const_int 0)])
7841 (match_dup 2) (match_dup 3)))]
7842 "")