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comparison gcc/config/mips/24k.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents a06113de4d67
children 84e7813d76e9
comparison
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68:561a7518be6b 111:04ced10e8804
6 ;; The 24kf1_1 is 24k with 1:1 clocked fpu. 6 ;; The 24kf1_1 is 24k with 1:1 clocked fpu.
7 ;; 7 ;;
8 ;; References: 8 ;; References:
9 ;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04." 9 ;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04."
10 ;; 10 ;;
11 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc. 11 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
12 ;; 12 ;;
13 ;; This file is part of GCC. 13 ;; This file is part of GCC.
14 ;; 14 ;;
15 ;; GCC is free software; you can redistribute it and/or modify it 15 ;; GCC is free software; you can redistribute it and/or modify it
16 ;; under the terms of the GNU General Public License as published 16 ;; under the terms of the GNU General Public License as published
92 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5") 92 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5")
93 93
94 ;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles 94 ;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles
95 (define_insn_reservation "r24k_int_mfhilo" 5 95 (define_insn_reservation "r24k_int_mfhilo" 5
96 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 96 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
97 (eq_attr "type" "mfhilo")) 97 (eq_attr "type" "mfhi,mflo"))
98 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 98 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
99 99
100 ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass 100 ;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
101 (define_insn_reservation "r24k_int_mthilo" 1 101 (define_insn_reservation "r24k_int_mthilo" 1
102 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 102 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
103 (eq_attr "type" "mthilo")) 103 (eq_attr "type" "mthi,mtlo"))
104 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 104 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
105 105
106 ;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and 106 ;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and
107 ;; 8bit, but is tricky to identify. 107 ;; 8bit, but is tricky to identify.
108 (define_insn_reservation "r24k_int_div" 36 108 (define_insn_reservation "r24k_int_div" 36
120 120
121 121
122 ;; 6. Store 122 ;; 6. Store
123 (define_insn_reservation "r24k_int_store" 1 123 (define_insn_reservation "r24k_int_store" 1
124 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 124 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
125 (and (eq_attr "type" "store") 125 (eq_attr "type" "store"))
126 (eq_attr "mode" "!unknown")))
127 "r24k_iss+r24k_ixu_arith")
128
129 ;; 6.1 Special case - matches the cprestore pattern which don't set the mode
130 ;; attrib. This avoids being set as r24k_int_store and have it checked
131 ;; against store_data_bypass_p, which would then fail because cprestore
132 ;; does not have a normal SET pattern.
133 (define_insn_reservation "r24k_unknown_store" 1
134 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
135 (and (eq_attr "type" "store")
136 (eq_attr "mode" "unknown")))
137 "r24k_iss+r24k_ixu_arith") 126 "r24k_iss+r24k_ixu_arith")
138 127
139 128
140 ;; 7. Multiple instructions 129 ;; 7. Multiple instructions
141 (define_insn_reservation "r24k_int_multi" 1 130 (define_insn_reservation "r24k_int_multi" 1
147 ;; 8. Unknowns - Currently these include blockage, consttable and alignment 136 ;; 8. Unknowns - Currently these include blockage, consttable and alignment
148 ;; rtls. They do not really affect scheduling latency, (blockage affects 137 ;; rtls. They do not really affect scheduling latency, (blockage affects
149 ;; scheduling via log links, but not used here). 138 ;; scheduling via log links, but not used here).
150 (define_insn_reservation "r24k_int_unknown" 0 139 (define_insn_reservation "r24k_int_unknown" 0
151 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1") 140 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
152 (eq_attr "type" "unknown")) 141 (eq_attr "type" "unknown,atomic,syncloop"))
153 "r24k_iss") 142 "r24k_iss")
154 143
155 144
156 ;; 9. Prefetch 145 ;; 9. Prefetch
157 (define_insn_reservation "r24k_int_prefetch" 1 146 (define_insn_reservation "r24k_int_prefetch" 1
167 ;; load->next use : 2 cycles (Default) 156 ;; load->next use : 2 cycles (Default)
168 ;; load->load base: 3 cycles 157 ;; load->load base: 3 cycles
169 ;; load->store base: 3 cycles 158 ;; load->store base: 3 cycles
170 ;; load->prefetch: 3 cycles 159 ;; load->prefetch: 3 cycles
171 (define_bypass 3 "r24k_int_load" "r24k_int_load") 160 (define_bypass 3 "r24k_int_load" "r24k_int_load")
172 (define_bypass 3 "r24k_int_load" "r24k_int_store" "!store_data_bypass_p") 161 (define_bypass 3 "r24k_int_load" "r24k_int_store" "!mips_store_data_bypass_p")
173 (define_bypass 3 "r24k_int_load" "r24k_int_prefetch") 162 (define_bypass 3 "r24k_int_load" "r24k_int_prefetch")
174 163
175 ;; arith->next use : 1 cycles (Default) 164 ;; arith->next use : 1 cycles (Default)
176 ;; arith->load base: 2 cycles 165 ;; arith->load base: 2 cycles
177 ;; arith->store base: 2 cycles 166 ;; arith->store base: 2 cycles
178 ;; arith->prefetch: 2 cycles 167 ;; arith->prefetch: 2 cycles
179 (define_bypass 2 "r24k_int_arith" "r24k_int_load") 168 (define_bypass 2 "r24k_int_arith" "r24k_int_load")
180 (define_bypass 2 "r24k_int_arith" "r24k_int_store" "!store_data_bypass_p") 169 (define_bypass 2 "r24k_int_arith" "r24k_int_store" "!mips_store_data_bypass_p")
181 (define_bypass 2 "r24k_int_arith" "r24k_int_prefetch") 170 (define_bypass 2 "r24k_int_arith" "r24k_int_prefetch")
182 171
183 ;; mul3->next use : 5 cycles (default) 172 ;; mul3->next use : 5 cycles (default)
184 ;; mul3->l/s base : 6 cycles 173 ;; mul3->l/s base : 6 cycles
185 ;; mul3->prefetch : 6 cycles 174 ;; mul3->prefetch : 6 cycles
186 (define_bypass 6 "r24k_int_mul3" "r24k_int_load") 175 (define_bypass 6 "r24k_int_mul3" "r24k_int_load")
187 (define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p") 176 (define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!mips_store_data_bypass_p")
188 (define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch") 177 (define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch")
189 178
190 ;; mul3->madd/msub : 1 cycle 179 ;; mul3->madd/msub : 1 cycle
191 (define_bypass 1 "r24k_int_mul3" "r24k_int_madd" "mips_linked_madd_p") 180 (define_bypass 1 "r24k_int_mul3" "r24k_int_madd" "mips_linked_madd_p")
192 181
193 ;; mfhilo->next use : 5 cycles (default) 182 ;; mfhilo->next use : 5 cycles (default)
194 ;; mfhilo->l/s base : 6 cycles 183 ;; mfhilo->l/s base : 6 cycles
195 ;; mfhilo->prefetch : 6 cycles 184 ;; mfhilo->prefetch : 6 cycles
196 ;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo) 185 ;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo)
197 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_load") 186 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_load")
198 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_store" "!store_data_bypass_p") 187 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_store"
188 "!mips_store_data_bypass_p")
199 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch") 189 (define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch")
200 (define_bypass 2 "r24k_int_mthilo" "r24k_int_madd") 190 (define_bypass 2 "r24k_int_mthilo" "r24k_int_madd")
201 191
202 ;; cop->next use : 3 cycles (Default) 192 ;; cop->next use : 3 cycles (Default)
203 ;; cop->l/s base : 4 cycles 193 ;; cop->l/s base : 4 cycles
204 ;; (define_bypass 4 "r24k_int_cop" "r24k_int_load") 194 ;; (define_bypass 4 "r24k_int_cop" "r24k_int_load")
205 ;; (define_bypass 4 "r24k_int_cop" "r24k_int_store" "!store_data_bypass_p") 195 ;; (define_bypass 4 "r24k_int_cop" "r24k_int_store"
196 ;; "!mips_store_data_bypass_p")
206 197
207 ;; multi->next use : 1 cycles (Default) 198 ;; multi->next use : 1 cycles (Default)
208 ;; multi->l/s base : 2 cycles 199 ;; multi->l/s base : 2 cycles
209 ;; multi->prefetch : 2 cycles 200 ;; multi->prefetch : 2 cycles
210 (define_bypass 2 "r24k_int_multi" "r24k_int_load") 201 (define_bypass 2 "r24k_int_multi" "r24k_int_load")
211 (define_bypass 2 "r24k_int_multi" "r24k_int_store" "!store_data_bypass_p") 202 (define_bypass 2 "r24k_int_multi" "r24k_int_store" "!mips_store_data_bypass_p")
212 (define_bypass 2 "r24k_int_multi" "r24k_int_prefetch") 203 (define_bypass 2 "r24k_int_multi" "r24k_int_prefetch")
204
205
206 ;; --------------------------------------------------------------
207 ;; DSP instructions
208 ;; --------------------------------------------------------------
209
210 ;; absq, addq, addsc, addu, addwc, bitrev, cmp, cmpgu, cmpu, insv, modsub,
211 ;; packrl, pick, preceq, preceu, precequ, precrq, precrqu, raddu, rddsp, repl,
212 ;; replv, shll, shllv, shra, shrav, shrl, shrlv, subq, subu, wrdsp
213 (define_insn_reservation "r24k_dsp_alu" 2
214 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
215 (eq_attr "type" "dspalu,dspalusat"))
216 "r24k_iss+r24k_ixu_arith")
217
218 ;; dpaq_s, dpau, dpsq_s, dpsu, maq_s, mulsaq
219 (define_insn_reservation "r24k_dsp_mac" 1
220 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
221 (eq_attr "type" "dspmac"))
222 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
223
224 ;; dpaq_sa, dpsq_sa, maq_sa
225 (define_insn_reservation "r24k_dsp_mac_sat" 1
226 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
227 (eq_attr "type" "dspmacsat"))
228 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
229
230 ;; extp, extpdp, extpdpv, extpv, extr, extrv
231 (define_insn_reservation "r24k_dsp_acc_ext" 5
232 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
233 (eq_attr "type" "accext"))
234 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
235
236 ;; mthlip, shilo, shilov
237 (define_insn_reservation "r24k_dsp_acc_mod" 1
238 (and (eq_attr "cpu" "24kc,24kf2_1,24kf1_1")
239 (eq_attr "type" "accmod"))
240 "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)")
241
242
243 ;; mult/madd->dsp_acc_ext : 4 cycles
244 ;; mult/madd->dsp_acc_mod : 4 cycles
245 (define_bypass 4 "r24k_int_mult" "r24k_dsp_acc_ext")
246 (define_bypass 4 "r24k_int_mult" "r24k_dsp_acc_mod")
247
248 ;; mthilo->dsp_acc_ext : 4 cycles
249 ;; mthilo->dsp_acc_ext : 4 cycles
250 (define_bypass 4 "r24k_int_mthilo" "r24k_dsp_acc_ext")
251 (define_bypass 4 "r24k_int_mthilo" "r24k_dsp_acc_mod")
252
253 ;; dsp_mac->next use : 1 cycles (default)
254 ;; dsp_mac->dsp_acc_ext : 4 cycles
255 ;; dsp_mac->dsp_acc_mod : 4 cycles
256 (define_bypass 4 "r24k_dsp_mac" "r24k_dsp_acc_ext")
257 (define_bypass 4 "r24k_dsp_mac" "r24k_dsp_acc_mod")
258
259 ;; dsp_mac_sat->next use : 1 cycles (default)
260 ;; dsp_mac_sat->mult/madd : 2 cycles
261 ;; dsp_mac_sat->dsp_mac : 2 cycles
262 ;; dsp_mac_sat->dsp_mac_sat : 2 cycles
263 ;; dsp_mac_sat->dsp_acc_ext : 4 cycles
264 ;; dsp_mac_sat->dsp_acc_mod : 4 cycles
265 (define_bypass 2 "r24k_dsp_mac_sat" "r24k_int_mult")
266 (define_bypass 2 "r24k_dsp_mac_sat" "r24k_dsp_mac")
267 (define_bypass 2 "r24k_dsp_mac_sat" "r24k_dsp_mac_sat")
268 (define_bypass 4 "r24k_dsp_mac_sat" "r24k_dsp_acc_ext")
269 (define_bypass 4 "r24k_dsp_mac_sat" "r24k_dsp_acc_mod")
270
271 ;; dsp_acc_ext->next use : 5 cycles (default)
272 ;; dsp_acc_ext->l/s base : 6 cycles
273 ;; dsp_acc_ext->prefetch : 6 cycles
274 (define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_load")
275 (define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_store"
276 "!mips_store_data_bypass_p")
277 (define_bypass 6 "r24k_dsp_acc_ext" "r24k_int_prefetch")
278
279 ;; dsp_acc_mod->next use : 1 cycles (default)
280 ;; dsp_acc_mod->mult/madd : 2 cycles
281 ;; dsp_acc_mod->dsp_mac : 2 cycles
282 ;; dsp_acc_mod->dsp_mac_sat : 2 cycles
283 ;; dsp_acc_mod->dsp_acc_ext : 4 cycles
284 ;; dsp_acc_mod->dsp_acc_mod : 4 cycles
285 (define_bypass 2 "r24k_dsp_acc_mod" "r24k_int_mult")
286 (define_bypass 2 "r24k_dsp_acc_mod" "r24k_dsp_mac")
287 (define_bypass 2 "r24k_dsp_acc_mod" "r24k_dsp_mac_sat")
288 (define_bypass 4 "r24k_dsp_acc_mod" "r24k_dsp_acc_ext")
289 (define_bypass 4 "r24k_dsp_acc_mod" "r24k_dsp_acc_mod")
290
291 ;; dspalu->next use : 2 cycles (default)
292 ;; dspalu->l/s base : 3 cycles
293 ;; dspalu->prefetch : 3 cycles
294 ;; some pairs of dspalu (addsc/addwc, cmp/pick, wrdsp/insv) : 1 cycle
295 (define_bypass 3 "r24k_dsp_alu" "r24k_int_load")
296 (define_bypass 3 "r24k_dsp_alu" "r24k_int_store" "!mips_store_data_bypass_p")
297 (define_bypass 3 "r24k_dsp_alu" "r24k_int_prefetch")
298 (define_bypass 1 "r24k_dsp_alu" "r24k_dsp_alu" "mips_dspalu_bypass_p")
213 299
214 300
215 ;; -------------------------------------------------------------- 301 ;; --------------------------------------------------------------
216 ;; Floating Point Instructions 302 ;; Floating Point Instructions
217 ;; -------------------------------------------------------------- 303 ;; --------------------------------------------------------------
328 ;; Bypass to Consumer 414 ;; Bypass to Consumer
329 ;; -------------------------------------------------------------- 415 ;; --------------------------------------------------------------
330 ;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles 416 ;; r24kf2_1_fcvt_f2i->l/s base : 11 cycles
331 ;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles 417 ;; r24kf2_1_fcvt_f2i->prefetch : 11 cycles
332 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load") 418 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_load")
333 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p") 419 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_store"
420 "!mips_store_data_bypass_p")
334 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch") 421 (define_bypass 11 "r24kf2_1_fcvt_f2i" "r24k_int_prefetch")
335 422
336 ;; r24kf2_1_fxfer->l/s base : 5 cycles 423 ;; r24kf2_1_fxfer->l/s base : 5 cycles
337 ;; r24kf2_1_fxfer->prefetch : 5 cycles 424 ;; r24kf2_1_fxfer->prefetch : 5 cycles
338 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load") 425 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_load")
339 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!store_data_bypass_p") 426 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p")
340 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch") 427 (define_bypass 5 "r24kf2_1_fxfer" "r24k_int_prefetch")
341 428
342 ;; -------------------------------------------------------------- 429 ;; --------------------------------------------------------------
343 ;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use 430 ;; The 24kf1_1 is a 24k configured with 1:1 cpu and fpu, so use
344 ;; the unscaled timings 431 ;; the unscaled timings
444 ;; Bypass to Consumer 531 ;; Bypass to Consumer
445 ;; -------------------------------------------------------------- 532 ;; --------------------------------------------------------------
446 ;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles 533 ;; r24kf1_1_fcvt_f2i->l/s base : 6 cycles
447 ;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles 534 ;; r24kf1_1_fcvt_f2i->prefetch : 6 cycles
448 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load") 535 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_load")
449 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p") 536 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_store"
537 "!mips_store_data_bypass_p")
450 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch") 538 (define_bypass 6 "r24kf1_1_fcvt_f2i" "r24k_int_prefetch")
451 539
452 ;; r24kf1_1_fxfer->l/s base : 3 cycles 540 ;; r24kf1_1_fxfer->l/s base : 3 cycles
453 ;; r24kf1_1_fxfer->prefetch : 3 cycles 541 ;; r24kf1_1_fxfer->prefetch : 3 cycles
454 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load") 542 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_load")
455 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!store_data_bypass_p") 543 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_store" "!mips_store_data_bypass_p")
456 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch") 544 (define_bypass 3 "r24kf1_1_fxfer" "r24k_int_prefetch")
457 545