Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/mips/4130.md @ 111:04ced10e8804
gcc 7
| author | kono |
|---|---|
| date | Fri, 27 Oct 2017 22:46:09 +0900 |
| parents | 77e2b8dfacca |
| children | 84e7813d76e9 |
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| 68:561a7518be6b | 111:04ced10e8804 |
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| 1 ;; Copyright (C) 2004, 2005, 2007 Free Software Foundation, Inc. | 1 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc. |
| 2 ;; | 2 ;; |
| 3 ;; This file is part of GCC. | 3 ;; This file is part of GCC. |
| 4 ;; | 4 ;; |
| 5 ;; GCC is free software; you can redistribute it and/or modify | 5 ;; GCC is free software; you can redistribute it and/or modify |
| 6 ;; it under the terms of the GNU General Public License as published by | 6 ;; it under the terms of the GNU General Public License as published by |
| 70 ;; The scheduling hooks use this attribute for (b) above. | 70 ;; The scheduling hooks use this attribute for (b) above. |
| 71 (define_attr "vr4130_class" "mul,mem,alu" | 71 (define_attr "vr4130_class" "mul,mem,alu" |
| 72 (cond [(eq_attr "type" "load,store") | 72 (cond [(eq_attr "type" "load,store") |
| 73 (const_string "mem") | 73 (const_string "mem") |
| 74 | 74 |
| 75 (eq_attr "type" "mfhilo,mthilo,imul,imul3,imadd,idiv") | 75 (eq_attr "type" "mfhi,mflo,mthi,mtlo,imul,imul3,imadd,idiv") |
| 76 (const_string "mul")] | 76 (const_string "mul")] |
| 77 (const_string "alu"))) | 77 (const_string "alu"))) |
| 78 | 78 |
| 79 (define_insn_reservation "vr4130_multi" 1 | 79 (define_insn_reservation "vr4130_multi" 1 |
| 80 (and (eq_attr "cpu" "r4130") | 80 (and (eq_attr "cpu" "r4130") |
| 81 (eq_attr "type" "multi,unknown")) | 81 (eq_attr "type" "multi,unknown,atomic,syncloop")) |
| 82 "vr4130_alu1 + vr4130_alu2 + vr4130_dcache + vr4130_muldiv") | 82 "vr4130_alu1 + vr4130_alu2 + vr4130_dcache + vr4130_muldiv") |
| 83 | 83 |
| 84 (define_insn_reservation "vr4130_int" 1 | 84 (define_insn_reservation "vr4130_int" 1 |
| 85 (and (eq_attr "cpu" "r4130") | 85 (and (eq_attr "cpu" "r4130") |
| 86 (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt")) | 86 (eq_attr "type" "arith,const,logical,move,nop,shift,signext,slt")) |
| 96 (eq_attr "type" "store")) | 96 (eq_attr "type" "store")) |
| 97 "vr4130_dcache") | 97 "vr4130_dcache") |
| 98 | 98 |
| 99 (define_insn_reservation "vr4130_mfhilo" 3 | 99 (define_insn_reservation "vr4130_mfhilo" 3 |
| 100 (and (eq_attr "cpu" "r4130") | 100 (and (eq_attr "cpu" "r4130") |
| 101 (eq_attr "type" "mfhilo")) | 101 (eq_attr "type" "mfhi,mflo")) |
| 102 "vr4130_muldiv") | 102 "vr4130_muldiv") |
| 103 | 103 |
| 104 (define_insn_reservation "vr4130_mthilo" 1 | 104 (define_insn_reservation "vr4130_mthilo" 1 |
| 105 (and (eq_attr "cpu" "r4130") | 105 (and (eq_attr "cpu" "r4130") |
| 106 (eq_attr "type" "mthilo")) | 106 (eq_attr "type" "mthi,mtlo")) |
| 107 "vr4130_muldiv") | 107 "vr4130_muldiv") |
| 108 | 108 |
| 109 ;; The product is available in LO & HI after one cycle. Moving the result | 109 ;; The product is available in LO & HI after one cycle. Moving the result |
| 110 ;; into an integer register will take an additional three cycles, see mflo | 110 ;; into an integer register will take an additional three cycles, see mflo |
| 111 ;; & mfhi above. Note that the same latencies and repeat rates apply if we | 111 ;; & mfhi above. Note that the same latencies and repeat rates apply if we |