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comparison gcc/config/mips/5k.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents a06113de4d67
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
8 ;; 8 ;;
9 ;; 5Kc - Single issue with no floating point unit. 9 ;; 5Kc - Single issue with no floating point unit.
10 ;; 5kf - Separate floating point pipe which can dual-issue with the 10 ;; 5kf - Separate floating point pipe which can dual-issue with the
11 ;; integer pipe. 11 ;; integer pipe.
12 ;; 12 ;;
13 ;; Copyright (C) 2005, 2007 Free Software Foundation, Inc. 13 ;; Copyright (C) 2005-2017 Free Software Foundation, Inc.
14 ;; 14 ;;
15 ;; This file is part of GCC. 15 ;; This file is part of GCC.
16 ;; 16 ;;
17 ;; GCC is free software; you can redistribute it and/or modify it 17 ;; GCC is free software; you can redistribute it and/or modify it
18 ;; under the terms of the GNU General Public License as published 18 ;; under the terms of the GNU General Public License as published
86 "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") 86 "r5k_ixu_arith+(r5k_ixu_mpydiv*2)")
87 87
88 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency. 88 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
89 (define_insn_reservation "r5k_int_mthilo" 1 89 (define_insn_reservation "r5k_int_mthilo" 1
90 (and (eq_attr "cpu" "5kc,5kf") 90 (and (eq_attr "cpu" "5kc,5kf")
91 (eq_attr "type" "mthilo")) 91 (eq_attr "type" "mthi,mtlo"))
92 "r5k_ixu_arith+r5k_ixu_mpydiv") 92 "r5k_ixu_arith+r5k_ixu_mpydiv")
93 93
94 ;; Move from HI/LO -> integer operation has a 2 cycle latency. 94 ;; Move from HI/LO -> integer operation has a 2 cycle latency.
95 (define_insn_reservation "r5k_int_mfhilo" 2 95 (define_insn_reservation "r5k_int_mfhilo" 2
96 (and (eq_attr "cpu" "5kc,5kf") 96 (and (eq_attr "cpu" "5kc,5kf")
97 (eq_attr "type" "mfhilo")) 97 (eq_attr "type" "mfhi,mflo"))
98 "r5k_ixu_arith+r5k_ixu_mpydiv") 98 "r5k_ixu_arith+r5k_ixu_mpydiv")
99 99
100 ;; All other integer insns. 100 ;; All other integer insns.
101 (define_insn_reservation "r5k_int_alu" 1 101 (define_insn_reservation "r5k_int_alu" 1
102 (and (eq_attr "cpu" "5kc,5kf") 102 (and (eq_attr "cpu" "5kc,5kf")
125 (define_bypass 3 "r5k_int_mul" "r5k_int_jump") 125 (define_bypass 3 "r5k_int_mul" "r5k_int_jump")
126 126
127 ;; Unknown or multi - single issue 127 ;; Unknown or multi - single issue
128 (define_insn_reservation "r5k_int_unknown" 1 128 (define_insn_reservation "r5k_int_unknown" 1
129 (and (eq_attr "cpu" "5kc,5kf") 129 (and (eq_attr "cpu" "5kc,5kf")
130 (eq_attr "type" "unknown,multi")) 130 (eq_attr "type" "unknown,multi,atomic,syncloop"))
131 "r5k_ixu_arith+r5k_ixu_mpydiv") 131 "r5k_ixu_arith+r5k_ixu_mpydiv")
132 132
133 133
134 ;; Floating Point Instructions 134 ;; Floating Point Instructions
135 ;; The 5Kf is a partial dual-issue cpu which can dual issue an integer 135 ;; The 5Kf is a partial dual-issue cpu which can dual issue an integer