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comparison gcc/config/mips/mips-msa.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
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68:561a7518be6b 111:04ced10e8804
1 ;; Machine Description for MIPS MSA ASE
2 ;; Based on the MIPS MSA spec Revision 1.11 8/4/2014
3 ;;
4 ;; Copyright (C) 2015-2017 Free Software Foundation, Inc.
5 ;;
6 ;; This file is part of GCC.
7 ;;
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; any later version.
12 ;;
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
21 ;;
22
23 (define_c_enum "unspec" [
24 UNSPEC_MSA_ASUB_S
25 UNSPEC_MSA_ASUB_U
26 UNSPEC_MSA_AVE_S
27 UNSPEC_MSA_AVE_U
28 UNSPEC_MSA_AVER_S
29 UNSPEC_MSA_AVER_U
30 UNSPEC_MSA_BCLR
31 UNSPEC_MSA_BCLRI
32 UNSPEC_MSA_BINSL
33 UNSPEC_MSA_BINSLI
34 UNSPEC_MSA_BINSR
35 UNSPEC_MSA_BINSRI
36 UNSPEC_MSA_BNEG
37 UNSPEC_MSA_BNEGI
38 UNSPEC_MSA_BSET
39 UNSPEC_MSA_BSETI
40 UNSPEC_MSA_BRANCH_V
41 UNSPEC_MSA_BRANCH
42 UNSPEC_MSA_CFCMSA
43 UNSPEC_MSA_CTCMSA
44 UNSPEC_MSA_FCAF
45 UNSPEC_MSA_FCLASS
46 UNSPEC_MSA_FCUNE
47 UNSPEC_MSA_FEXDO
48 UNSPEC_MSA_FEXP2
49 UNSPEC_MSA_FEXUPL
50 UNSPEC_MSA_FEXUPR
51 UNSPEC_MSA_FFQL
52 UNSPEC_MSA_FFQR
53 UNSPEC_MSA_FLOG2
54 UNSPEC_MSA_FRCP
55 UNSPEC_MSA_FRINT
56 UNSPEC_MSA_FRSQRT
57 UNSPEC_MSA_FSAF
58 UNSPEC_MSA_FSEQ
59 UNSPEC_MSA_FSLE
60 UNSPEC_MSA_FSLT
61 UNSPEC_MSA_FSNE
62 UNSPEC_MSA_FSOR
63 UNSPEC_MSA_FSUEQ
64 UNSPEC_MSA_FSULE
65 UNSPEC_MSA_FSULT
66 UNSPEC_MSA_FSUN
67 UNSPEC_MSA_FSUNE
68 UNSPEC_MSA_FTINT_S
69 UNSPEC_MSA_FTINT_U
70 UNSPEC_MSA_FTQ
71 UNSPEC_MSA_MADD_Q
72 UNSPEC_MSA_MADDR_Q
73 UNSPEC_MSA_MSUB_Q
74 UNSPEC_MSA_MSUBR_Q
75 UNSPEC_MSA_MUL_Q
76 UNSPEC_MSA_MULR_Q
77 UNSPEC_MSA_NLOC
78 UNSPEC_MSA_SAT_S
79 UNSPEC_MSA_SAT_U
80 UNSPEC_MSA_SLD
81 UNSPEC_MSA_SLDI
82 UNSPEC_MSA_SPLAT
83 UNSPEC_MSA_SPLATI
84 UNSPEC_MSA_SRAR
85 UNSPEC_MSA_SRARI
86 UNSPEC_MSA_SRLR
87 UNSPEC_MSA_SRLRI
88 UNSPEC_MSA_SUBS_S
89 UNSPEC_MSA_SUBS_U
90 UNSPEC_MSA_SUBSUU_S
91 UNSPEC_MSA_SUBSUS_U
92 UNSPEC_MSA_VSHF
93 ])
94
95 ;; All vector modes with 128 bits.
96 (define_mode_iterator MSA [V2DF V4SF V2DI V4SI V8HI V16QI])
97
98 ;; Same as MSA. Used by vcond to iterate two modes.
99 (define_mode_iterator MSA_2 [V2DF V4SF V2DI V4SI V8HI V16QI])
100
101 ;; Only used for splitting insert_d and copy_{u,s}.d.
102 (define_mode_iterator MSA_D [V2DI V2DF])
103
104 ;; Only used for copy_{u,s}.w.
105 (define_mode_iterator MSA_W [V4SI V4SF])
106
107 ;; Only integer modes.
108 (define_mode_iterator IMSA [V2DI V4SI V8HI V16QI])
109
110 ;; As IMSA but excludes V16QI.
111 (define_mode_iterator IMSA_DWH [V2DI V4SI V8HI])
112
113 ;; As IMSA but excludes V2DI.
114 (define_mode_iterator IMSA_WHB [V4SI V8HI V16QI])
115
116 ;; Only integer modes equal or larger than a word.
117 (define_mode_iterator IMSA_DW [V2DI V4SI])
118
119 ;; Only integer modes smaller than a word.
120 (define_mode_iterator IMSA_HB [V8HI V16QI])
121
122 ;; Only integer modes for fixed-point madd_q/maddr_q.
123 (define_mode_iterator IMSA_WH [V4SI V8HI])
124
125 ;; Only floating-point modes.
126 (define_mode_iterator FMSA [V2DF V4SF])
127
128 ;; Only used for immediate set shuffle elements instruction.
129 (define_mode_iterator MSA_WHB_W [V4SI V8HI V16QI V4SF])
130
131 ;; The attribute gives the integer vector mode with same size.
132 (define_mode_attr VIMODE
133 [(V2DF "V2DI")
134 (V4SF "V4SI")
135 (V2DI "V2DI")
136 (V4SI "V4SI")
137 (V8HI "V8HI")
138 (V16QI "V16QI")])
139
140 ;; The attribute gives half modes for vector modes.
141 (define_mode_attr VHMODE
142 [(V8HI "V16QI")
143 (V4SI "V8HI")
144 (V2DI "V4SI")])
145
146 ;; The attribute gives double modes for vector modes.
147 (define_mode_attr VDMODE
148 [(V4SI "V2DI")
149 (V8HI "V4SI")
150 (V16QI "V8HI")])
151
152 ;; The attribute gives half modes with same number of elements for vector modes.
153 (define_mode_attr VTRUNCMODE
154 [(V8HI "V8QI")
155 (V4SI "V4HI")
156 (V2DI "V2SI")])
157
158 ;; This attribute gives the mode of the result for "copy_s_b, copy_u_b" etc.
159 (define_mode_attr VRES
160 [(V2DF "DF")
161 (V4SF "SF")
162 (V2DI "DI")
163 (V4SI "SI")
164 (V8HI "SI")
165 (V16QI "SI")])
166
167 ;; Only used with MSA_D iterator.
168 (define_mode_attr msa_d
169 [(V2DI "reg_or_0")
170 (V2DF "register")])
171
172 ;; This attribute gives the integer vector mode with same size.
173 (define_mode_attr mode_i
174 [(V2DF "v2di")
175 (V4SF "v4si")
176 (V2DI "v2di")
177 (V4SI "v4si")
178 (V8HI "v8hi")
179 (V16QI "v16qi")])
180
181 ;; This attribute gives suffix for MSA instructions.
182 (define_mode_attr msafmt
183 [(V2DF "d")
184 (V4SF "w")
185 (V2DI "d")
186 (V4SI "w")
187 (V8HI "h")
188 (V16QI "b")])
189
190 ;; This attribute gives suffix for integers in VHMODE.
191 (define_mode_attr hmsafmt
192 [(V2DI "w")
193 (V4SI "h")
194 (V8HI "b")])
195
196 ;; This attribute gives define_insn suffix for MSA instructions that need
197 ;; distinction between integer and floating point.
198 (define_mode_attr msafmt_f
199 [(V2DF "d_f")
200 (V4SF "w_f")
201 (V2DI "d")
202 (V4SI "w")
203 (V8HI "h")
204 (V16QI "b")])
205
206 ;; This is used to form an immediate operand constraint using
207 ;; "const_<indeximm>_operand".
208 (define_mode_attr indeximm
209 [(V2DF "0_or_1")
210 (V4SF "0_to_3")
211 (V2DI "0_or_1")
212 (V4SI "0_to_3")
213 (V8HI "uimm3")
214 (V16QI "uimm4")])
215
216 ;; This attribute represents bitmask needed for vec_merge using
217 ;; "const_<bitmask>_operand".
218 (define_mode_attr bitmask
219 [(V2DF "exp_2")
220 (V4SF "exp_4")
221 (V2DI "exp_2")
222 (V4SI "exp_4")
223 (V8HI "exp_8")
224 (V16QI "exp_16")])
225
226 ;; This attribute is used to form an immediate operand constraint using
227 ;; "const_<bitimm>_operand".
228 (define_mode_attr bitimm
229 [(V16QI "uimm3")
230 (V8HI "uimm4")
231 (V4SI "uimm5")
232 (V2DI "uimm6")])
233
234 (define_expand "vec_init<mode><unitmode>"
235 [(match_operand:MSA 0 "register_operand")
236 (match_operand:MSA 1 "")]
237 "ISA_HAS_MSA"
238 {
239 mips_expand_vector_init (operands[0], operands[1]);
240 DONE;
241 })
242
243 ;; pckev pattern with implicit type conversion.
244 (define_insn "vec_pack_trunc_<mode>"
245 [(set (match_operand:<VHMODE> 0 "register_operand" "=f")
246 (vec_concat:<VHMODE>
247 (truncate:<VTRUNCMODE>
248 (match_operand:IMSA_DWH 1 "register_operand" "f"))
249 (truncate:<VTRUNCMODE>
250 (match_operand:IMSA_DWH 2 "register_operand" "f"))))]
251 "ISA_HAS_MSA"
252 "pckev.<hmsafmt>\t%w0,%w2,%w1"
253 [(set_attr "type" "simd_permute")
254 (set_attr "mode" "<MODE>")])
255
256 (define_expand "vec_unpacks_hi_v4sf"
257 [(set (match_operand:V2DF 0 "register_operand" "=f")
258 (float_extend:V2DF
259 (vec_select:V2SF
260 (match_operand:V4SF 1 "register_operand" "f")
261 (match_dup 2))))]
262 "ISA_HAS_MSA"
263 {
264 operands[2] = mips_msa_vec_parallel_const_half (V4SFmode, true/*high_p*/);
265 })
266
267 (define_expand "vec_unpacks_lo_v4sf"
268 [(set (match_operand:V2DF 0 "register_operand" "=f")
269 (float_extend:V2DF
270 (vec_select:V2SF
271 (match_operand:V4SF 1 "register_operand" "f")
272 (match_dup 2))))]
273 "ISA_HAS_MSA"
274 {
275 operands[2] = mips_msa_vec_parallel_const_half (V4SFmode, false/*high_p*/);
276 })
277
278 (define_expand "vec_unpacks_hi_<mode>"
279 [(match_operand:<VDMODE> 0 "register_operand")
280 (match_operand:IMSA_WHB 1 "register_operand")]
281 "ISA_HAS_MSA"
282 {
283 mips_expand_vec_unpack (operands, false/*unsigned_p*/, true/*high_p*/);
284 DONE;
285 })
286
287 (define_expand "vec_unpacks_lo_<mode>"
288 [(match_operand:<VDMODE> 0 "register_operand")
289 (match_operand:IMSA_WHB 1 "register_operand")]
290 "ISA_HAS_MSA"
291 {
292 mips_expand_vec_unpack (operands, false/*unsigned_p*/, false/*high_p*/);
293 DONE;
294 })
295
296 (define_expand "vec_unpacku_hi_<mode>"
297 [(match_operand:<VDMODE> 0 "register_operand")
298 (match_operand:IMSA_WHB 1 "register_operand")]
299 "ISA_HAS_MSA"
300 {
301 mips_expand_vec_unpack (operands, true/*unsigned_p*/, true/*high_p*/);
302 DONE;
303 })
304
305 (define_expand "vec_unpacku_lo_<mode>"
306 [(match_operand:<VDMODE> 0 "register_operand")
307 (match_operand:IMSA_WHB 1 "register_operand")]
308 "ISA_HAS_MSA"
309 {
310 mips_expand_vec_unpack (operands, true/*unsigned_p*/, false/*high_p*/);
311 DONE;
312 })
313
314 (define_expand "vec_extract<mode><unitmode>"
315 [(match_operand:<UNITMODE> 0 "register_operand")
316 (match_operand:IMSA 1 "register_operand")
317 (match_operand 2 "const_<indeximm>_operand")]
318 "ISA_HAS_MSA"
319 {
320 if (<UNITMODE>mode == QImode || <UNITMODE>mode == HImode)
321 {
322 rtx dest1 = gen_reg_rtx (SImode);
323 emit_insn (gen_msa_copy_s_<msafmt> (dest1, operands[1], operands[2]));
324 emit_move_insn (operands[0],
325 gen_lowpart (<UNITMODE>mode, dest1));
326 }
327 else
328 emit_insn (gen_msa_copy_s_<msafmt> (operands[0], operands[1], operands[2]));
329 DONE;
330 })
331
332 (define_expand "vec_extract<mode><unitmode>"
333 [(match_operand:<UNITMODE> 0 "register_operand")
334 (match_operand:FMSA 1 "register_operand")
335 (match_operand 2 "const_<indeximm>_operand")]
336 "ISA_HAS_MSA"
337 {
338 rtx temp;
339 HOST_WIDE_INT val = INTVAL (operands[2]);
340
341 if (val == 0)
342 temp = operands[1];
343 else
344 {
345 /* We need to do the SLDI operation in V16QImode and adjust
346 operands[2] accordingly. */
347 rtx wd = gen_reg_rtx (V16QImode);
348 rtx ws = gen_reg_rtx (V16QImode);
349 emit_move_insn (ws, gen_rtx_SUBREG (V16QImode, operands[1], 0));
350 rtx n = GEN_INT (val * GET_MODE_SIZE (<UNITMODE>mode));
351 gcc_assert (INTVAL (n) < GET_MODE_NUNITS (V16QImode));
352 emit_insn (gen_msa_sldi_b (wd, ws, ws, n));
353 temp = gen_reg_rtx (<MODE>mode);
354 emit_move_insn (temp, gen_rtx_SUBREG (<MODE>mode, wd, 0));
355 }
356 emit_insn (gen_msa_vec_extract_<msafmt_f> (operands[0], temp));
357 DONE;
358 })
359
360 (define_insn_and_split "msa_vec_extract_<msafmt_f>"
361 [(set (match_operand:<UNITMODE> 0 "register_operand" "=f")
362 (vec_select:<UNITMODE>
363 (match_operand:FMSA 1 "register_operand" "f")
364 (parallel [(const_int 0)])))]
365 "ISA_HAS_MSA"
366 "#"
367 "&& reload_completed"
368 [(set (match_dup 0) (match_dup 1))]
369 {
370 /* An MSA register cannot be reinterpreted as a single precision
371 register when using -mno-odd-spreg and the MSA register is
372 an odd number. */
373 if (<UNITMODE>mode == SFmode && !TARGET_ODD_SPREG
374 && (REGNO (operands[1]) & 1))
375 {
376 emit_move_insn (gen_rtx_REG (<MODE>mode, REGNO (operands[0])),
377 operands[1]);
378 operands[1] = operands[0];
379 }
380 else
381 operands[1] = gen_rtx_REG (<UNITMODE>mode, REGNO (operands[1]));
382 }
383 [(set_attr "move_type" "fmove")
384 (set_attr "mode" "<UNITMODE>")])
385
386 (define_expand "vec_set<mode>"
387 [(match_operand:IMSA 0 "register_operand")
388 (match_operand:<UNITMODE> 1 "reg_or_0_operand")
389 (match_operand 2 "const_<indeximm>_operand")]
390 "ISA_HAS_MSA"
391 {
392 rtx index = GEN_INT (1 << INTVAL (operands[2]));
393 emit_insn (gen_msa_insert_<msafmt> (operands[0], operands[1],
394 operands[0], index));
395 DONE;
396 })
397
398 (define_expand "vec_set<mode>"
399 [(match_operand:FMSA 0 "register_operand")
400 (match_operand:<UNITMODE> 1 "register_operand")
401 (match_operand 2 "const_<indeximm>_operand")]
402 "ISA_HAS_MSA"
403 {
404 rtx index = GEN_INT (1 << INTVAL (operands[2]));
405 emit_insn (gen_msa_insve_<msafmt_f>_scalar (operands[0], operands[1],
406 operands[0], index));
407 DONE;
408 })
409
410 (define_expand "vcondu<MSA:mode><IMSA:mode>"
411 [(match_operand:MSA 0 "register_operand")
412 (match_operand:MSA 1 "reg_or_m1_operand")
413 (match_operand:MSA 2 "reg_or_0_operand")
414 (match_operator 3 ""
415 [(match_operand:IMSA 4 "register_operand")
416 (match_operand:IMSA 5 "register_operand")])]
417 "ISA_HAS_MSA
418 && (GET_MODE_NUNITS (<MSA:MODE>mode) == GET_MODE_NUNITS (<IMSA:MODE>mode))"
419 {
420 mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands);
421 DONE;
422 })
423
424 (define_expand "vcond<MSA:mode><MSA_2:mode>"
425 [(match_operand:MSA 0 "register_operand")
426 (match_operand:MSA 1 "reg_or_m1_operand")
427 (match_operand:MSA 2 "reg_or_0_operand")
428 (match_operator 3 ""
429 [(match_operand:MSA_2 4 "register_operand")
430 (match_operand:MSA_2 5 "register_operand")])]
431 "ISA_HAS_MSA
432 && (GET_MODE_NUNITS (<MSA:MODE>mode) == GET_MODE_NUNITS (<MSA_2:MODE>mode))"
433 {
434 mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands);
435 DONE;
436 })
437
438 (define_insn "msa_insert_<msafmt_f>"
439 [(set (match_operand:MSA 0 "register_operand" "=f")
440 (vec_merge:MSA
441 (vec_duplicate:MSA
442 (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ"))
443 (match_operand:MSA 2 "register_operand" "0")
444 (match_operand 3 "const_<bitmask>_operand" "")))]
445 "ISA_HAS_MSA"
446 {
447 if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
448 return "#";
449 else
450 return "insert.<msafmt>\t%w0[%y3],%z1";
451 }
452 [(set_attr "type" "simd_insert")
453 (set_attr "mode" "<MODE>")])
454
455 (define_split
456 [(set (match_operand:MSA_D 0 "register_operand")
457 (vec_merge:MSA_D
458 (vec_duplicate:MSA_D
459 (match_operand:<UNITMODE> 1 "<MSA_D:msa_d>_operand"))
460 (match_operand:MSA_D 2 "register_operand")
461 (match_operand 3 "const_<bitmask>_operand")))]
462 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT"
463 [(const_int 0)]
464 {
465 mips_split_msa_insert_d (operands[0], operands[2], operands[3], operands[1]);
466 DONE;
467 })
468
469 (define_insn "msa_insve_<msafmt_f>"
470 [(set (match_operand:MSA 0 "register_operand" "=f")
471 (vec_merge:MSA
472 (vec_duplicate:MSA
473 (vec_select:<UNITMODE>
474 (match_operand:MSA 1 "register_operand" "f")
475 (parallel [(const_int 0)])))
476 (match_operand:MSA 2 "register_operand" "0")
477 (match_operand 3 "const_<bitmask>_operand" "")))]
478 "ISA_HAS_MSA"
479 "insve.<msafmt>\t%w0[%y3],%w1[0]"
480 [(set_attr "type" "simd_insert")
481 (set_attr "mode" "<MODE>")])
482
483 ;; Operand 3 is a scalar.
484 (define_insn "msa_insve_<msafmt_f>_scalar"
485 [(set (match_operand:FMSA 0 "register_operand" "=f")
486 (vec_merge:FMSA
487 (vec_duplicate:FMSA
488 (match_operand:<UNITMODE> 1 "register_operand" "f"))
489 (match_operand:FMSA 2 "register_operand" "0")
490 (match_operand 3 "const_<bitmask>_operand" "")))]
491 "ISA_HAS_MSA"
492 "insve.<msafmt>\t%w0[%y3],%w1[0]"
493 [(set_attr "type" "simd_insert")
494 (set_attr "mode" "<MODE>")])
495
496 (define_insn "msa_copy_<su>_<msafmt>"
497 [(set (match_operand:<VRES> 0 "register_operand" "=d")
498 (any_extend:<VRES>
499 (vec_select:<UNITMODE>
500 (match_operand:IMSA_HB 1 "register_operand" "f")
501 (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))]
502 "ISA_HAS_MSA"
503 "copy_<su>.<msafmt>\t%0,%w1[%2]"
504 [(set_attr "type" "simd_copy")
505 (set_attr "mode" "<MODE>")])
506
507 (define_insn "msa_copy_u_w"
508 [(set (match_operand:DI 0 "register_operand" "=d")
509 (zero_extend:DI
510 (vec_select:SI
511 (match_operand:V4SI 1 "register_operand" "f")
512 (parallel [(match_operand 2 "const_0_to_3_operand" "")]))))]
513 "ISA_HAS_MSA && TARGET_64BIT"
514 "copy_u.w\t%0,%w1[%2]"
515 [(set_attr "type" "simd_copy")
516 (set_attr "mode" "V4SI")])
517
518 (define_insn "msa_copy_s_<msafmt_f>_64bit"
519 [(set (match_operand:DI 0 "register_operand" "=d")
520 (sign_extend:DI
521 (vec_select:<UNITMODE>
522 (match_operand:MSA_W 1 "register_operand" "f")
523 (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))]
524 "ISA_HAS_MSA && TARGET_64BIT"
525 "copy_s.<msafmt>\t%0,%w1[%2]"
526 [(set_attr "type" "simd_copy")
527 (set_attr "mode" "<MODE>")])
528
529 (define_insn "msa_copy_s_<msafmt_f>"
530 [(set (match_operand:<UNITMODE> 0 "register_operand" "=d")
531 (vec_select:<UNITMODE>
532 (match_operand:MSA_W 1 "register_operand" "f")
533 (parallel [(match_operand 2 "const_<indeximm>_operand" "")])))]
534 "ISA_HAS_MSA"
535 "copy_s.<msafmt>\t%0,%w1[%2]"
536 [(set_attr "type" "simd_copy")
537 (set_attr "mode" "<MODE>")])
538
539 (define_insn_and_split "msa_copy_s_<msafmt_f>"
540 [(set (match_operand:<UNITMODE> 0 "register_operand" "=d")
541 (vec_select:<UNITMODE>
542 (match_operand:MSA_D 1 "register_operand" "f")
543 (parallel [(match_operand 2 "const_<indeximm>_operand" "")])))]
544 "ISA_HAS_MSA"
545 {
546 if (TARGET_64BIT)
547 return "copy_s.<msafmt>\t%0,%w1[%2]";
548 else
549 return "#";
550 }
551 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT"
552 [(const_int 0)]
553 {
554 mips_split_msa_copy_d (operands[0], operands[1], operands[2],
555 gen_msa_copy_s_w);
556 DONE;
557 }
558 [(set_attr "type" "simd_copy")
559 (set_attr "mode" "<MODE>")])
560
561 (define_expand "vec_perm_const<mode>"
562 [(match_operand:MSA 0 "register_operand")
563 (match_operand:MSA 1 "register_operand")
564 (match_operand:MSA 2 "register_operand")
565 (match_operand:<VIMODE> 3 "")]
566 "ISA_HAS_MSA"
567 {
568 if (mips_expand_vec_perm_const (operands))
569 DONE;
570 else
571 FAIL;
572 })
573
574 (define_expand "abs<mode>2"
575 [(match_operand:IMSA 0 "register_operand" "=f")
576 (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))]
577 "ISA_HAS_MSA"
578 {
579 rtx reg = gen_reg_rtx (<MODE>mode);
580 emit_move_insn (reg, CONST0_RTX (<MODE>mode));
581 emit_insn (gen_msa_add_a_<msafmt> (operands[0], operands[1], reg));
582 DONE;
583 })
584
585 (define_expand "neg<mode>2"
586 [(set (match_operand:MSA 0 "register_operand")
587 (minus:MSA (match_dup 2)
588 (match_operand:MSA 1 "register_operand")))]
589 "ISA_HAS_MSA"
590 {
591 rtx reg = gen_reg_rtx (<MODE>mode);
592 emit_move_insn (reg, CONST0_RTX (<MODE>mode));
593 operands[2] = reg;
594 })
595
596 (define_expand "msa_ldi<mode>"
597 [(match_operand:IMSA 0 "register_operand")
598 (match_operand 1 "const_imm10_operand")]
599 "ISA_HAS_MSA"
600 {
601 if (<MODE>mode == V16QImode)
602 operands[1] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1]),
603 <UNITMODE>mode));
604 emit_move_insn (operands[0],
605 mips_gen_const_int_vector (<MODE>mode, INTVAL (operands[1])));
606 DONE;
607 })
608
609 (define_insn "vec_perm<mode>"
610 [(set (match_operand:MSA 0 "register_operand" "=f")
611 (unspec:MSA [(match_operand:MSA 1 "register_operand" "f")
612 (match_operand:MSA 2 "register_operand" "f")
613 (match_operand:<VIMODE> 3 "register_operand" "0")]
614 UNSPEC_MSA_VSHF))]
615 "ISA_HAS_MSA"
616 "vshf.<msafmt>\t%w0,%w2,%w1"
617 [(set_attr "type" "simd_sld")
618 (set_attr "mode" "<MODE>")])
619
620 (define_expand "mov<mode>"
621 [(set (match_operand:MSA 0)
622 (match_operand:MSA 1))]
623 "ISA_HAS_MSA"
624 {
625 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
626 DONE;
627 })
628
629 (define_expand "movmisalign<mode>"
630 [(set (match_operand:MSA 0)
631 (match_operand:MSA 1))]
632 "ISA_HAS_MSA"
633 {
634 if (mips_legitimize_move (<MODE>mode, operands[0], operands[1]))
635 DONE;
636 })
637
638 ;; 128-bit MSA modes can only exist in MSA registers or memory. An exception
639 ;; is allowing MSA modes for GP registers for arguments and return values.
640 (define_insn "mov<mode>_msa"
641 [(set (match_operand:MSA 0 "nonimmediate_operand" "=f,f,R,*d,*f")
642 (match_operand:MSA 1 "move_operand" "fYGYI,R,f,*f,*d"))]
643 "ISA_HAS_MSA"
644 { return mips_output_move (operands[0], operands[1]); }
645 [(set_attr "type" "simd_move,simd_load,simd_store,simd_copy,simd_insert")
646 (set_attr "mode" "<MODE>")])
647
648 (define_split
649 [(set (match_operand:MSA 0 "nonimmediate_operand")
650 (match_operand:MSA 1 "move_operand"))]
651 "reload_completed && ISA_HAS_MSA
652 && mips_split_move_insn_p (operands[0], operands[1], insn)"
653 [(const_int 0)]
654 {
655 mips_split_move_insn (operands[0], operands[1], curr_insn);
656 DONE;
657 })
658
659 ;; Offset load
660 (define_expand "msa_ld_<msafmt_f>"
661 [(match_operand:MSA 0 "register_operand")
662 (match_operand 1 "pmode_register_operand")
663 (match_operand 2 "aq10<msafmt>_operand")]
664 "ISA_HAS_MSA"
665 {
666 rtx addr = plus_constant (GET_MODE (operands[1]), operands[1],
667 INTVAL (operands[2]));
668 mips_emit_move (operands[0], gen_rtx_MEM (<MODE>mode, addr));
669 DONE;
670 })
671
672 ;; Offset store
673 (define_expand "msa_st_<msafmt_f>"
674 [(match_operand:MSA 0 "register_operand")
675 (match_operand 1 "pmode_register_operand")
676 (match_operand 2 "aq10<msafmt>_operand")]
677 "ISA_HAS_MSA"
678 {
679 rtx addr = plus_constant (GET_MODE (operands[1]), operands[1],
680 INTVAL (operands[2]));
681 mips_emit_move (gen_rtx_MEM (<MODE>mode, addr), operands[0]);
682 DONE;
683 })
684
685 ;; Integer operations
686 (define_insn "add<mode>3"
687 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f")
688 (plus:IMSA
689 (match_operand:IMSA 1 "register_operand" "f,f,f")
690 (match_operand:IMSA 2 "reg_or_vector_same_ximm5_operand" "f,Unv5,Uuv5")))]
691 "ISA_HAS_MSA"
692 {
693 switch (which_alternative)
694 {
695 case 0:
696 return "addv.<msafmt>\t%w0,%w1,%w2";
697 case 1:
698 {
699 HOST_WIDE_INT val = INTVAL (CONST_VECTOR_ELT (operands[2], 0));
700
701 operands[2] = GEN_INT (-val);
702 return "subvi.<msafmt>\t%w0,%w1,%d2";
703 }
704 case 2:
705 return "addvi.<msafmt>\t%w0,%w1,%E2";
706 default:
707 gcc_unreachable ();
708 }
709 }
710 [(set_attr "alu_type" "simd_add")
711 (set_attr "type" "simd_int_arith")
712 (set_attr "mode" "<MODE>")])
713
714 (define_insn "sub<mode>3"
715 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
716 (minus:IMSA
717 (match_operand:IMSA 1 "register_operand" "f,f")
718 (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))]
719 "ISA_HAS_MSA"
720 "@
721 subv.<msafmt>\t%w0,%w1,%w2
722 subvi.<msafmt>\t%w0,%w1,%E2"
723 [(set_attr "alu_type" "simd_add")
724 (set_attr "type" "simd_int_arith")
725 (set_attr "mode" "<MODE>")])
726
727 (define_insn "mul<mode>3"
728 [(set (match_operand:IMSA 0 "register_operand" "=f")
729 (mult:IMSA (match_operand:IMSA 1 "register_operand" "f")
730 (match_operand:IMSA 2 "register_operand" "f")))]
731 "ISA_HAS_MSA"
732 "mulv.<msafmt>\t%w0,%w1,%w2"
733 [(set_attr "type" "simd_mul")
734 (set_attr "mode" "<MODE>")])
735
736 (define_insn "msa_maddv_<msafmt>"
737 [(set (match_operand:IMSA 0 "register_operand" "=f")
738 (plus:IMSA (mult:IMSA (match_operand:IMSA 1 "register_operand" "f")
739 (match_operand:IMSA 2 "register_operand" "f"))
740 (match_operand:IMSA 3 "register_operand" "0")))]
741 "ISA_HAS_MSA"
742 "maddv.<msafmt>\t%w0,%w1,%w2"
743 [(set_attr "type" "simd_mul")
744 (set_attr "mode" "<MODE>")])
745
746 (define_insn "msa_msubv_<msafmt>"
747 [(set (match_operand:IMSA 0 "register_operand" "=f")
748 (minus:IMSA (match_operand:IMSA 1 "register_operand" "0")
749 (mult:IMSA (match_operand:IMSA 2 "register_operand" "f")
750 (match_operand:IMSA 3 "register_operand" "f"))))]
751 "ISA_HAS_MSA"
752 "msubv.<msafmt>\t%w0,%w2,%w3"
753 [(set_attr "type" "simd_mul")
754 (set_attr "mode" "<MODE>")])
755
756 (define_insn "div<mode>3"
757 [(set (match_operand:IMSA 0 "register_operand" "=f")
758 (div:IMSA (match_operand:IMSA 1 "register_operand" "f")
759 (match_operand:IMSA 2 "register_operand" "f")))]
760 "ISA_HAS_MSA"
761 { return mips_msa_output_division ("div_s.<msafmt>\t%w0,%w1,%w2", operands); }
762 [(set_attr "type" "simd_div")
763 (set_attr "mode" "<MODE>")])
764
765 (define_insn "udiv<mode>3"
766 [(set (match_operand:IMSA 0 "register_operand" "=f")
767 (udiv:IMSA (match_operand:IMSA 1 "register_operand" "f")
768 (match_operand:IMSA 2 "register_operand" "f")))]
769 "ISA_HAS_MSA"
770 { return mips_msa_output_division ("div_u.<msafmt>\t%w0,%w1,%w2", operands); }
771 [(set_attr "type" "simd_div")
772 (set_attr "mode" "<MODE>")])
773
774 (define_insn "mod<mode>3"
775 [(set (match_operand:IMSA 0 "register_operand" "=f")
776 (mod:IMSA (match_operand:IMSA 1 "register_operand" "f")
777 (match_operand:IMSA 2 "register_operand" "f")))]
778 "ISA_HAS_MSA"
779 { return mips_msa_output_division ("mod_s.<msafmt>\t%w0,%w1,%w2", operands); }
780 [(set_attr "type" "simd_div")
781 (set_attr "mode" "<MODE>")])
782
783 (define_insn "umod<mode>3"
784 [(set (match_operand:IMSA 0 "register_operand" "=f")
785 (umod:IMSA (match_operand:IMSA 1 "register_operand" "f")
786 (match_operand:IMSA 2 "register_operand" "f")))]
787 "ISA_HAS_MSA"
788 { return mips_msa_output_division ("mod_u.<msafmt>\t%w0,%w1,%w2", operands); }
789 [(set_attr "type" "simd_div")
790 (set_attr "mode" "<MODE>")])
791
792 (define_insn "xor<mode>3"
793 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f")
794 (xor:IMSA
795 (match_operand:IMSA 1 "register_operand" "f,f,f")
796 (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
797 "ISA_HAS_MSA"
798 "@
799 xor.v\t%w0,%w1,%w2
800 bnegi.%v0\t%w0,%w1,%V2
801 xori.b\t%w0,%w1,%B2"
802 [(set_attr "type" "simd_logic,simd_bit,simd_logic")
803 (set_attr "mode" "<MODE>")])
804
805 (define_insn "ior<mode>3"
806 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f")
807 (ior:IMSA
808 (match_operand:IMSA 1 "register_operand" "f,f,f")
809 (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YC,Urv8")))]
810 "ISA_HAS_MSA"
811 "@
812 or.v\t%w0,%w1,%w2
813 bseti.%v0\t%w0,%w1,%V2
814 ori.b\t%w0,%w1,%B2"
815 [(set_attr "type" "simd_logic,simd_bit,simd_logic")
816 (set_attr "mode" "<MODE>")])
817
818 (define_insn "and<mode>3"
819 [(set (match_operand:IMSA 0 "register_operand" "=f,f,f")
820 (and:IMSA
821 (match_operand:IMSA 1 "register_operand" "f,f,f")
822 (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,YZ,Urv8")))]
823 "ISA_HAS_MSA"
824 {
825 switch (which_alternative)
826 {
827 case 0:
828 return "and.v\t%w0,%w1,%w2";
829 case 1:
830 {
831 rtx elt0 = CONST_VECTOR_ELT (operands[2], 0);
832 unsigned HOST_WIDE_INT val = ~UINTVAL (elt0);
833 operands[2] = mips_gen_const_int_vector (<MODE>mode, val & (-val));
834 return "bclri.%v0\t%w0,%w1,%V2";
835 }
836 case 2:
837 return "andi.b\t%w0,%w1,%B2";
838 default:
839 gcc_unreachable ();
840 }
841 }
842 [(set_attr "type" "simd_logic,simd_bit,simd_logic")
843 (set_attr "mode" "<MODE>")])
844
845 (define_insn "one_cmpl<mode>2"
846 [(set (match_operand:IMSA 0 "register_operand" "=f")
847 (not:IMSA (match_operand:IMSA 1 "register_operand" "f")))]
848 "ISA_HAS_MSA"
849 "nor.v\t%w0,%w1,%w1"
850 [(set_attr "type" "simd_logic")
851 (set_attr "mode" "TI")])
852
853 (define_insn "vlshr<mode>3"
854 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
855 (lshiftrt:IMSA
856 (match_operand:IMSA 1 "register_operand" "f,f")
857 (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
858 "ISA_HAS_MSA"
859 "@
860 srl.<msafmt>\t%w0,%w1,%w2
861 srli.<msafmt>\t%w0,%w1,%E2"
862 [(set_attr "type" "simd_shift")
863 (set_attr "mode" "<MODE>")])
864
865 (define_insn "vashr<mode>3"
866 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
867 (ashiftrt:IMSA
868 (match_operand:IMSA 1 "register_operand" "f,f")
869 (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
870 "ISA_HAS_MSA"
871 "@
872 sra.<msafmt>\t%w0,%w1,%w2
873 srai.<msafmt>\t%w0,%w1,%E2"
874 [(set_attr "type" "simd_shift")
875 (set_attr "mode" "<MODE>")])
876
877 (define_insn "vashl<mode>3"
878 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
879 (ashift:IMSA
880 (match_operand:IMSA 1 "register_operand" "f,f")
881 (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
882 "ISA_HAS_MSA"
883 "@
884 sll.<msafmt>\t%w0,%w1,%w2
885 slli.<msafmt>\t%w0,%w1,%E2"
886 [(set_attr "type" "simd_shift")
887 (set_attr "mode" "<MODE>")])
888
889 ;; Floating-point operations
890 (define_insn "add<mode>3"
891 [(set (match_operand:FMSA 0 "register_operand" "=f")
892 (plus:FMSA (match_operand:FMSA 1 "register_operand" "f")
893 (match_operand:FMSA 2 "register_operand" "f")))]
894 "ISA_HAS_MSA"
895 "fadd.<msafmt>\t%w0,%w1,%w2"
896 [(set_attr "type" "simd_fadd")
897 (set_attr "mode" "<MODE>")])
898
899 (define_insn "sub<mode>3"
900 [(set (match_operand:FMSA 0 "register_operand" "=f")
901 (minus:FMSA (match_operand:FMSA 1 "register_operand" "f")
902 (match_operand:FMSA 2 "register_operand" "f")))]
903 "ISA_HAS_MSA"
904 "fsub.<msafmt>\t%w0,%w1,%w2"
905 [(set_attr "type" "simd_fadd")
906 (set_attr "mode" "<MODE>")])
907
908 (define_insn "mul<mode>3"
909 [(set (match_operand:FMSA 0 "register_operand" "=f")
910 (mult:FMSA (match_operand:FMSA 1 "register_operand" "f")
911 (match_operand:FMSA 2 "register_operand" "f")))]
912 "ISA_HAS_MSA"
913 "fmul.<msafmt>\t%w0,%w1,%w2"
914 [(set_attr "type" "simd_fmul")
915 (set_attr "mode" "<MODE>")])
916
917 (define_insn "div<mode>3"
918 [(set (match_operand:FMSA 0 "register_operand" "=f")
919 (div:FMSA (match_operand:FMSA 1 "register_operand" "f")
920 (match_operand:FMSA 2 "register_operand" "f")))]
921 "ISA_HAS_MSA"
922 "fdiv.<msafmt>\t%w0,%w1,%w2"
923 [(set_attr "type" "simd_fdiv")
924 (set_attr "mode" "<MODE>")])
925
926 (define_insn "fma<mode>4"
927 [(set (match_operand:FMSA 0 "register_operand" "=f")
928 (fma:FMSA (match_operand:FMSA 1 "register_operand" "f")
929 (match_operand:FMSA 2 "register_operand" "f")
930 (match_operand:FMSA 3 "register_operand" "0")))]
931 "ISA_HAS_MSA"
932 "fmadd.<msafmt>\t%w0,%w1,%w2"
933 [(set_attr "type" "simd_fmadd")
934 (set_attr "mode" "<MODE>")])
935
936 (define_insn "fnma<mode>4"
937 [(set (match_operand:FMSA 0 "register_operand" "=f")
938 (fma:FMSA (neg:FMSA (match_operand:FMSA 1 "register_operand" "f"))
939 (match_operand:FMSA 2 "register_operand" "f")
940 (match_operand:FMSA 3 "register_operand" "0")))]
941 "ISA_HAS_MSA"
942 "fmsub.<msafmt>\t%w0,%w1,%w2"
943 [(set_attr "type" "simd_fmadd")
944 (set_attr "mode" "<MODE>")])
945
946 (define_insn "sqrt<mode>2"
947 [(set (match_operand:FMSA 0 "register_operand" "=f")
948 (sqrt:FMSA (match_operand:FMSA 1 "register_operand" "f")))]
949 "ISA_HAS_MSA"
950 "fsqrt.<msafmt>\t%w0,%w1"
951 [(set_attr "type" "simd_fdiv")
952 (set_attr "mode" "<MODE>")])
953
954 ;; Built-in functions
955 (define_insn "msa_add_a_<msafmt>"
956 [(set (match_operand:IMSA 0 "register_operand" "=f")
957 (plus:IMSA (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
958 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))))]
959 "ISA_HAS_MSA"
960 "add_a.<msafmt>\t%w0,%w1,%w2"
961 [(set_attr "type" "simd_int_arith")
962 (set_attr "mode" "<MODE>")])
963
964 (define_insn "msa_adds_a_<msafmt>"
965 [(set (match_operand:IMSA 0 "register_operand" "=f")
966 (ss_plus:IMSA
967 (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
968 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f"))))]
969 "ISA_HAS_MSA"
970 "adds_a.<msafmt>\t%w0,%w1,%w2"
971 [(set_attr "type" "simd_int_arith")
972 (set_attr "mode" "<MODE>")])
973
974 (define_insn "ssadd<mode>3"
975 [(set (match_operand:IMSA 0 "register_operand" "=f")
976 (ss_plus:IMSA (match_operand:IMSA 1 "register_operand" "f")
977 (match_operand:IMSA 2 "register_operand" "f")))]
978 "ISA_HAS_MSA"
979 "adds_s.<msafmt>\t%w0,%w1,%w2"
980 [(set_attr "type" "simd_int_arith")
981 (set_attr "mode" "<MODE>")])
982
983 (define_insn "usadd<mode>3"
984 [(set (match_operand:IMSA 0 "register_operand" "=f")
985 (us_plus:IMSA (match_operand:IMSA 1 "register_operand" "f")
986 (match_operand:IMSA 2 "register_operand" "f")))]
987 "ISA_HAS_MSA"
988 "adds_u.<msafmt>\t%w0,%w1,%w2"
989 [(set_attr "type" "simd_int_arith")
990 (set_attr "mode" "<MODE>")])
991
992 (define_insn "msa_asub_s_<msafmt>"
993 [(set (match_operand:IMSA 0 "register_operand" "=f")
994 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
995 (match_operand:IMSA 2 "register_operand" "f")]
996 UNSPEC_MSA_ASUB_S))]
997 "ISA_HAS_MSA"
998 "asub_s.<msafmt>\t%w0,%w1,%w2"
999 [(set_attr "type" "simd_int_arith")
1000 (set_attr "mode" "<MODE>")])
1001
1002 (define_insn "msa_asub_u_<msafmt>"
1003 [(set (match_operand:IMSA 0 "register_operand" "=f")
1004 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1005 (match_operand:IMSA 2 "register_operand" "f")]
1006 UNSPEC_MSA_ASUB_U))]
1007 "ISA_HAS_MSA"
1008 "asub_u.<msafmt>\t%w0,%w1,%w2"
1009 [(set_attr "type" "simd_int_arith")
1010 (set_attr "mode" "<MODE>")])
1011
1012 (define_insn "msa_ave_s_<msafmt>"
1013 [(set (match_operand:IMSA 0 "register_operand" "=f")
1014 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1015 (match_operand:IMSA 2 "register_operand" "f")]
1016 UNSPEC_MSA_AVE_S))]
1017 "ISA_HAS_MSA"
1018 "ave_s.<msafmt>\t%w0,%w1,%w2"
1019 [(set_attr "type" "simd_int_arith")
1020 (set_attr "mode" "<MODE>")])
1021
1022 (define_insn "msa_ave_u_<msafmt>"
1023 [(set (match_operand:IMSA 0 "register_operand" "=f")
1024 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1025 (match_operand:IMSA 2 "register_operand" "f")]
1026 UNSPEC_MSA_AVE_U))]
1027 "ISA_HAS_MSA"
1028 "ave_u.<msafmt>\t%w0,%w1,%w2"
1029 [(set_attr "type" "simd_int_arith")
1030 (set_attr "mode" "<MODE>")])
1031
1032 (define_insn "msa_aver_s_<msafmt>"
1033 [(set (match_operand:IMSA 0 "register_operand" "=f")
1034 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1035 (match_operand:IMSA 2 "register_operand" "f")]
1036 UNSPEC_MSA_AVER_S))]
1037 "ISA_HAS_MSA"
1038 "aver_s.<msafmt>\t%w0,%w1,%w2"
1039 [(set_attr "type" "simd_int_arith")
1040 (set_attr "mode" "<MODE>")])
1041
1042 (define_insn "msa_aver_u_<msafmt>"
1043 [(set (match_operand:IMSA 0 "register_operand" "=f")
1044 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1045 (match_operand:IMSA 2 "register_operand" "f")]
1046 UNSPEC_MSA_AVER_U))]
1047 "ISA_HAS_MSA"
1048 "aver_u.<msafmt>\t%w0,%w1,%w2"
1049 [(set_attr "type" "simd_int_arith")
1050 (set_attr "mode" "<MODE>")])
1051
1052 (define_insn "msa_bclr_<msafmt>"
1053 [(set (match_operand:IMSA 0 "register_operand" "=f")
1054 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1055 (match_operand:IMSA 2 "register_operand" "f")]
1056 UNSPEC_MSA_BCLR))]
1057 "ISA_HAS_MSA"
1058 "bclr.<msafmt>\t%w0,%w1,%w2"
1059 [(set_attr "type" "simd_bit")
1060 (set_attr "mode" "<MODE>")])
1061
1062 (define_insn "msa_bclri_<msafmt>"
1063 [(set (match_operand:IMSA 0 "register_operand" "=f")
1064 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1065 (match_operand 2 "const_<bitimm>_operand" "")]
1066 UNSPEC_MSA_BCLRI))]
1067 "ISA_HAS_MSA"
1068 "bclri.<msafmt>\t%w0,%w1,%2"
1069 [(set_attr "type" "simd_bit")
1070 (set_attr "mode" "<MODE>")])
1071
1072 (define_insn "msa_binsl_<msafmt>"
1073 [(set (match_operand:IMSA 0 "register_operand" "=f")
1074 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0")
1075 (match_operand:IMSA 2 "register_operand" "f")
1076 (match_operand:IMSA 3 "register_operand" "f")]
1077 UNSPEC_MSA_BINSL))]
1078 "ISA_HAS_MSA"
1079 "binsl.<msafmt>\t%w0,%w2,%w3"
1080 [(set_attr "type" "simd_bitins")
1081 (set_attr "mode" "<MODE>")])
1082
1083 (define_insn "msa_binsli_<msafmt>"
1084 [(set (match_operand:IMSA 0 "register_operand" "=f")
1085 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0")
1086 (match_operand:IMSA 2 "register_operand" "f")
1087 (match_operand 3 "const_<bitimm>_operand" "")]
1088 UNSPEC_MSA_BINSLI))]
1089 "ISA_HAS_MSA"
1090 "binsli.<msafmt>\t%w0,%w2,%3"
1091 [(set_attr "type" "simd_bitins")
1092 (set_attr "mode" "<MODE>")])
1093
1094 (define_insn "msa_binsr_<msafmt>"
1095 [(set (match_operand:IMSA 0 "register_operand" "=f")
1096 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0")
1097 (match_operand:IMSA 2 "register_operand" "f")
1098 (match_operand:IMSA 3 "register_operand" "f")]
1099 UNSPEC_MSA_BINSR))]
1100 "ISA_HAS_MSA"
1101 "binsr.<msafmt>\t%w0,%w2,%w3"
1102 [(set_attr "type" "simd_bitins")
1103 (set_attr "mode" "<MODE>")])
1104
1105 (define_insn "msa_binsri_<msafmt>"
1106 [(set (match_operand:IMSA 0 "register_operand" "=f")
1107 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "0")
1108 (match_operand:IMSA 2 "register_operand" "f")
1109 (match_operand 3 "const_<bitimm>_operand" "")]
1110 UNSPEC_MSA_BINSRI))]
1111 "ISA_HAS_MSA"
1112 "binsri.<msafmt>\t%w0,%w2,%3"
1113 [(set_attr "type" "simd_bitins")
1114 (set_attr "mode" "<MODE>")])
1115
1116 (define_insn "msa_bmnz_<msafmt>"
1117 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
1118 (ior:IMSA (and:IMSA (match_operand:IMSA 2 "register_operand" "f,f")
1119 (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8"))
1120 (and:IMSA (not:IMSA (match_dup 3))
1121 (match_operand:IMSA 1 "register_operand" "0,0"))))]
1122 "ISA_HAS_MSA"
1123 "@
1124 bmnz.v\t%w0,%w2,%w3
1125 bmnzi.b\t%w0,%w2,%B3"
1126 [(set_attr "type" "simd_bitmov")
1127 (set_attr "mode" "<MODE>")])
1128
1129 (define_insn "msa_bmz_<msafmt>"
1130 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
1131 (ior:IMSA (and:IMSA (not:IMSA
1132 (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8"))
1133 (match_operand:IMSA 2 "register_operand" "f,f"))
1134 (and:IMSA (match_operand:IMSA 1 "register_operand" "0,0")
1135 (match_dup 3))))]
1136 "ISA_HAS_MSA"
1137 "@
1138 bmz.v\t%w0,%w2,%w3
1139 bmzi.b\t%w0,%w2,%B3"
1140 [(set_attr "type" "simd_bitmov")
1141 (set_attr "mode" "<MODE>")])
1142
1143 (define_insn "msa_bneg_<msafmt>"
1144 [(set (match_operand:IMSA 0 "register_operand" "=f")
1145 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1146 (match_operand:IMSA 2 "register_operand" "f")]
1147 UNSPEC_MSA_BNEG))]
1148 "ISA_HAS_MSA"
1149 "bneg.<msafmt>\t%w0,%w1,%w2"
1150 [(set_attr "type" "simd_bit")
1151 (set_attr "mode" "<MODE>")])
1152
1153 (define_insn "msa_bnegi_<msafmt>"
1154 [(set (match_operand:IMSA 0 "register_operand" "=f")
1155 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1156 (match_operand 2 "const_msa_branch_operand" "")]
1157 UNSPEC_MSA_BNEGI))]
1158 "ISA_HAS_MSA"
1159 "bnegi.<msafmt>\t%w0,%w1,%2"
1160 [(set_attr "type" "simd_bit")
1161 (set_attr "mode" "<MODE>")])
1162
1163 (define_insn "msa_bsel_<msafmt>"
1164 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
1165 (ior:IMSA (and:IMSA (not:IMSA
1166 (match_operand:IMSA 1 "register_operand" "0,0"))
1167 (match_operand:IMSA 2 "register_operand" "f,f"))
1168 (and:IMSA (match_dup 1)
1169 (match_operand:IMSA 3 "reg_or_vector_same_val_operand" "f,Urv8"))))]
1170 "ISA_HAS_MSA"
1171 "@
1172 bsel.v\t%w0,%w2,%w3
1173 bseli.b\t%w0,%w2,%B3"
1174 [(set_attr "type" "simd_bitmov")
1175 (set_attr "mode" "<MODE>")])
1176
1177 (define_insn "msa_bset_<msafmt>"
1178 [(set (match_operand:IMSA 0 "register_operand" "=f")
1179 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1180 (match_operand:IMSA 2 "register_operand" "f")]
1181 UNSPEC_MSA_BSET))]
1182 "ISA_HAS_MSA"
1183 "bset.<msafmt>\t%w0,%w1,%w2"
1184 [(set_attr "type" "simd_bit")
1185 (set_attr "mode" "<MODE>")])
1186
1187 (define_insn "msa_bseti_<msafmt>"
1188 [(set (match_operand:IMSA 0 "register_operand" "=f")
1189 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
1190 (match_operand 2 "const_<bitimm>_operand" "")]
1191 UNSPEC_MSA_BSETI))]
1192 "ISA_HAS_MSA"
1193 "bseti.<msafmt>\t%w0,%w1,%2"
1194 [(set_attr "type" "simd_bit")
1195 (set_attr "mode" "<MODE>")])
1196
1197 (define_code_iterator ICC [eq le leu lt ltu])
1198
1199 (define_code_attr icc
1200 [(eq "eq")
1201 (le "le_s")
1202 (leu "le_u")
1203 (lt "lt_s")
1204 (ltu "lt_u")])
1205
1206 (define_code_attr icci
1207 [(eq "eqi")
1208 (le "lei_s")
1209 (leu "lei_u")
1210 (lt "lti_s")
1211 (ltu "lti_u")])
1212
1213 (define_code_attr cmpi
1214 [(eq "s")
1215 (le "s")
1216 (leu "u")
1217 (lt "s")
1218 (ltu "u")])
1219
1220 (define_insn "msa_c<ICC:icc>_<IMSA:msafmt>"
1221 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
1222 (ICC:IMSA
1223 (match_operand:IMSA 1 "register_operand" "f,f")
1224 (match_operand:IMSA 2 "reg_or_vector_same_<ICC:cmpi>imm5_operand" "f,U<ICC:cmpi>v5")))]
1225 "ISA_HAS_MSA"
1226 "@
1227 c<ICC:icc>.<IMSA:msafmt>\t%w0,%w1,%w2
1228 c<ICC:icci>.<IMSA:msafmt>\t%w0,%w1,%E2"
1229 [(set_attr "type" "simd_int_arith")
1230 (set_attr "mode" "<MODE>")])
1231
1232 (define_insn "msa_dotp_<su>_d"
1233 [(set (match_operand:V2DI 0 "register_operand" "=f")
1234 (plus:V2DI
1235 (mult:V2DI
1236 (any_extend:V2DI
1237 (vec_select:V2SI
1238 (match_operand:V4SI 1 "register_operand" "%f")
1239 (parallel [(const_int 0) (const_int 2)])))
1240 (any_extend:V2DI
1241 (vec_select:V2SI
1242 (match_operand:V4SI 2 "register_operand" "f")
1243 (parallel [(const_int 0) (const_int 2)]))))
1244 (mult:V2DI
1245 (any_extend:V2DI
1246 (vec_select:V2SI (match_dup 1)
1247 (parallel [(const_int 1) (const_int 3)])))
1248 (any_extend:V2DI
1249 (vec_select:V2SI (match_dup 2)
1250 (parallel [(const_int 1) (const_int 3)]))))))]
1251 "ISA_HAS_MSA"
1252 "dotp_<su>.d\t%w0,%w1,%w2"
1253 [(set_attr "type" "simd_mul")
1254 (set_attr "mode" "V2DI")])
1255
1256 (define_insn "msa_dotp_<su>_w"
1257 [(set (match_operand:V4SI 0 "register_operand" "=f")
1258 (plus:V4SI
1259 (mult:V4SI
1260 (any_extend:V4SI
1261 (vec_select:V4HI
1262 (match_operand:V8HI 1 "register_operand" "%f")
1263 (parallel [(const_int 0) (const_int 2)
1264 (const_int 4) (const_int 6)])))
1265 (any_extend:V4SI
1266 (vec_select:V4HI
1267 (match_operand:V8HI 2 "register_operand" "f")
1268 (parallel [(const_int 0) (const_int 2)
1269 (const_int 4) (const_int 6)]))))
1270 (mult:V4SI
1271 (any_extend:V4SI
1272 (vec_select:V4HI (match_dup 1)
1273 (parallel [(const_int 1) (const_int 3)
1274 (const_int 5) (const_int 7)])))
1275 (any_extend:V4SI
1276 (vec_select:V4HI (match_dup 2)
1277 (parallel [(const_int 1) (const_int 3)
1278 (const_int 5) (const_int 7)]))))))]
1279 "ISA_HAS_MSA"
1280 "dotp_<su>.w\t%w0,%w1,%w2"
1281 [(set_attr "type" "simd_mul")
1282 (set_attr "mode" "V4SI")])
1283
1284 (define_insn "msa_dotp_<su>_h"
1285 [(set (match_operand:V8HI 0 "register_operand" "=f")
1286 (plus:V8HI
1287 (mult:V8HI
1288 (any_extend:V8HI
1289 (vec_select:V8QI
1290 (match_operand:V16QI 1 "register_operand" "%f")
1291 (parallel [(const_int 0) (const_int 2)
1292 (const_int 4) (const_int 6)
1293 (const_int 8) (const_int 10)
1294 (const_int 12) (const_int 14)])))
1295 (any_extend:V8HI
1296 (vec_select:V8QI
1297 (match_operand:V16QI 2 "register_operand" "f")
1298 (parallel [(const_int 0) (const_int 2)
1299 (const_int 4) (const_int 6)
1300 (const_int 8) (const_int 10)
1301 (const_int 12) (const_int 14)]))))
1302 (mult:V8HI
1303 (any_extend:V8HI
1304 (vec_select:V8QI (match_dup 1)
1305 (parallel [(const_int 1) (const_int 3)
1306 (const_int 5) (const_int 7)
1307 (const_int 9) (const_int 11)
1308 (const_int 13) (const_int 15)])))
1309 (any_extend:V8HI
1310 (vec_select:V8QI (match_dup 2)
1311 (parallel [(const_int 1) (const_int 3)
1312 (const_int 5) (const_int 7)
1313 (const_int 9) (const_int 11)
1314 (const_int 13) (const_int 15)]))))))]
1315 "ISA_HAS_MSA"
1316 "dotp_<su>.h\t%w0,%w1,%w2"
1317 [(set_attr "type" "simd_mul")
1318 (set_attr "mode" "V8HI")])
1319
1320 (define_insn "msa_dpadd_<su>_d"
1321 [(set (match_operand:V2DI 0 "register_operand" "=f")
1322 (plus:V2DI
1323 (plus:V2DI
1324 (mult:V2DI
1325 (any_extend:V2DI
1326 (vec_select:V2SI
1327 (match_operand:V4SI 2 "register_operand" "%f")
1328 (parallel [(const_int 0) (const_int 2)])))
1329 (any_extend:V2DI
1330 (vec_select:V2SI
1331 (match_operand:V4SI 3 "register_operand" "f")
1332 (parallel [(const_int 0) (const_int 2)]))))
1333 (mult:V2DI
1334 (any_extend:V2DI
1335 (vec_select:V2SI (match_dup 2)
1336 (parallel [(const_int 1) (const_int 3)])))
1337 (any_extend:V2DI
1338 (vec_select:V2SI (match_dup 3)
1339 (parallel [(const_int 1) (const_int 3)])))))
1340 (match_operand:V2DI 1 "register_operand" "0")))]
1341 "ISA_HAS_MSA"
1342 "dpadd_<su>.d\t%w0,%w2,%w3"
1343 [(set_attr "type" "simd_mul")
1344 (set_attr "mode" "V2DI")])
1345
1346 (define_insn "msa_dpadd_<su>_w"
1347 [(set (match_operand:V4SI 0 "register_operand" "=f")
1348 (plus:V4SI
1349 (plus:V4SI
1350 (mult:V4SI
1351 (any_extend:V4SI
1352 (vec_select:V4HI
1353 (match_operand:V8HI 2 "register_operand" "%f")
1354 (parallel [(const_int 0) (const_int 2)
1355 (const_int 4) (const_int 6)])))
1356 (any_extend:V4SI
1357 (vec_select:V4HI
1358 (match_operand:V8HI 3 "register_operand" "f")
1359 (parallel [(const_int 0) (const_int 2)
1360 (const_int 4) (const_int 6)]))))
1361 (mult:V4SI
1362 (any_extend:V4SI
1363 (vec_select:V4HI (match_dup 2)
1364 (parallel [(const_int 1) (const_int 3)
1365 (const_int 5) (const_int 7)])))
1366 (any_extend:V4SI
1367 (vec_select:V4HI (match_dup 3)
1368 (parallel [(const_int 1) (const_int 3)
1369 (const_int 5) (const_int 7)])))))
1370 (match_operand:V4SI 1 "register_operand" "0")))]
1371 "ISA_HAS_MSA"
1372 "dpadd_<su>.w\t%w0,%w2,%w3"
1373 [(set_attr "type" "simd_mul")
1374 (set_attr "mode" "V4SI")])
1375
1376 (define_insn "msa_dpadd_<su>_h"
1377 [(set (match_operand:V8HI 0 "register_operand" "=f")
1378 (plus:V8HI
1379 (plus:V8HI
1380 (mult:V8HI
1381 (any_extend:V8HI
1382 (vec_select:V8QI
1383 (match_operand:V16QI 2 "register_operand" "%f")
1384 (parallel [(const_int 0) (const_int 2)
1385 (const_int 4) (const_int 6)
1386 (const_int 8) (const_int 10)
1387 (const_int 12) (const_int 14)])))
1388 (any_extend:V8HI
1389 (vec_select:V8QI
1390 (match_operand:V16QI 3 "register_operand" "f")
1391 (parallel [(const_int 0) (const_int 2)
1392 (const_int 4) (const_int 6)
1393 (const_int 8) (const_int 10)
1394 (const_int 12) (const_int 14)]))))
1395 (mult:V8HI
1396 (any_extend:V8HI
1397 (vec_select:V8QI (match_dup 2)
1398 (parallel [(const_int 1) (const_int 3)
1399 (const_int 5) (const_int 7)
1400 (const_int 9) (const_int 11)
1401 (const_int 13) (const_int 15)])))
1402 (any_extend:V8HI
1403 (vec_select:V8QI (match_dup 3)
1404 (parallel [(const_int 1) (const_int 3)
1405 (const_int 5) (const_int 7)
1406 (const_int 9) (const_int 11)
1407 (const_int 13) (const_int 15)])))))
1408 (match_operand:V8HI 1 "register_operand" "0")))]
1409 "ISA_HAS_MSA"
1410 "dpadd_<su>.h\t%w0,%w2,%w3"
1411 [(set_attr "type" "simd_mul")
1412 (set_attr "mode" "V8HI")])
1413
1414 (define_insn "msa_dpsub_<su>_d"
1415 [(set (match_operand:V2DI 0 "register_operand" "=f")
1416 (minus:V2DI
1417 (match_operand:V2DI 1 "register_operand" "0")
1418 (plus:V2DI
1419 (mult:V2DI
1420 (any_extend:V2DI
1421 (vec_select:V2SI
1422 (match_operand:V4SI 2 "register_operand" "%f")
1423 (parallel [(const_int 0) (const_int 2)])))
1424 (any_extend:V2DI
1425 (vec_select:V2SI
1426 (match_operand:V4SI 3 "register_operand" "f")
1427 (parallel [(const_int 0) (const_int 2)]))))
1428 (mult:V2DI
1429 (any_extend:V2DI
1430 (vec_select:V2SI (match_dup 2)
1431 (parallel [(const_int 1) (const_int 3)])))
1432 (any_extend:V2DI
1433 (vec_select:V2SI (match_dup 3)
1434 (parallel [(const_int 1) (const_int 3)])))))))]
1435 "ISA_HAS_MSA"
1436 "dpsub_<su>.d\t%w0,%w2,%w3"
1437 [(set_attr "type" "simd_mul")
1438 (set_attr "mode" "V2DI")])
1439
1440 (define_insn "msa_dpsub_<su>_w"
1441 [(set (match_operand:V4SI 0 "register_operand" "=f")
1442 (minus:V4SI
1443 (match_operand:V4SI 1 "register_operand" "0")
1444 (plus:V4SI
1445 (mult:V4SI
1446 (any_extend:V4SI
1447 (vec_select:V4HI
1448 (match_operand:V8HI 2 "register_operand" "%f")
1449 (parallel [(const_int 0) (const_int 2)
1450 (const_int 4) (const_int 6)])))
1451 (any_extend:V4SI
1452 (vec_select:V4HI
1453 (match_operand:V8HI 3 "register_operand" "f")
1454 (parallel [(const_int 0) (const_int 2)
1455 (const_int 4) (const_int 6)]))))
1456 (mult:V4SI
1457 (any_extend:V4SI
1458 (vec_select:V4HI (match_dup 2)
1459 (parallel [(const_int 1) (const_int 3)
1460 (const_int 5) (const_int 7)])))
1461 (any_extend:V4SI
1462 (vec_select:V4HI (match_dup 3)
1463 (parallel [(const_int 1) (const_int 3)
1464 (const_int 5) (const_int 7)])))))))]
1465 "ISA_HAS_MSA"
1466 "dpsub_<su>.w\t%w0,%w2,%w3"
1467 [(set_attr "type" "simd_mul")
1468 (set_attr "mode" "V4SI")])
1469
1470 (define_insn "msa_dpsub_<su>_h"
1471 [(set (match_operand:V8HI 0 "register_operand" "=f")
1472 (minus:V8HI
1473 (match_operand:V8HI 1 "register_operand" "0")
1474 (plus:V8HI
1475 (mult:V8HI
1476 (any_extend:V8HI
1477 (vec_select:V8QI
1478 (match_operand:V16QI 2 "register_operand" "%f")
1479 (parallel [(const_int 0) (const_int 2)
1480 (const_int 4) (const_int 6)
1481 (const_int 8) (const_int 10)
1482 (const_int 12) (const_int 14)])))
1483 (any_extend:V8HI
1484 (vec_select:V8QI
1485 (match_operand:V16QI 3 "register_operand" "f")
1486 (parallel [(const_int 0) (const_int 2)
1487 (const_int 4) (const_int 6)
1488 (const_int 8) (const_int 10)
1489 (const_int 12) (const_int 14)]))))
1490 (mult:V8HI
1491 (any_extend:V8HI
1492 (vec_select:V8QI (match_dup 2)
1493 (parallel [(const_int 1) (const_int 3)
1494 (const_int 5) (const_int 7)
1495 (const_int 9) (const_int 11)
1496 (const_int 13) (const_int 15)])))
1497 (any_extend:V8HI
1498 (vec_select:V8QI (match_dup 3)
1499 (parallel [(const_int 1) (const_int 3)
1500 (const_int 5) (const_int 7)
1501 (const_int 9) (const_int 11)
1502 (const_int 13) (const_int 15)])))))))]
1503 "ISA_HAS_MSA"
1504 "dpsub_<su>.h\t%w0,%w2,%w3"
1505 [(set_attr "type" "simd_mul")
1506 (set_attr "mode" "V8HI")])
1507
1508 (define_insn "msa_fclass_<msafmt>"
1509 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1510 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")]
1511 UNSPEC_MSA_FCLASS))]
1512 "ISA_HAS_MSA"
1513 "fclass.<msafmt>\t%w0,%w1"
1514 [(set_attr "type" "simd_fclass")
1515 (set_attr "mode" "<MODE>")])
1516
1517 (define_insn "msa_fcaf_<msafmt>"
1518 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1519 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")
1520 (match_operand:FMSA 2 "register_operand" "f")]
1521 UNSPEC_MSA_FCAF))]
1522 "ISA_HAS_MSA"
1523 "fcaf.<msafmt>\t%w0,%w1,%w2"
1524 [(set_attr "type" "simd_fcmp")
1525 (set_attr "mode" "<MODE>")])
1526
1527 (define_insn "msa_fcune_<FMSA:msafmt>"
1528 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1529 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")
1530 (match_operand:FMSA 2 "register_operand" "f")]
1531 UNSPEC_MSA_FCUNE))]
1532 "ISA_HAS_MSA"
1533 "fcune.<FMSA:msafmt>\t%w0,%w1,%w2"
1534 [(set_attr "type" "simd_fcmp")
1535 (set_attr "mode" "<MODE>")])
1536
1537 (define_code_iterator FCC [unordered ordered eq ne le lt uneq unle unlt])
1538
1539 (define_code_attr fcc
1540 [(unordered "fcun")
1541 (ordered "fcor")
1542 (eq "fceq")
1543 (ne "fcne")
1544 (uneq "fcueq")
1545 (unle "fcule")
1546 (unlt "fcult")
1547 (le "fcle")
1548 (lt "fclt")])
1549
1550 (define_int_iterator FSC_UNS [UNSPEC_MSA_FSAF UNSPEC_MSA_FSUN UNSPEC_MSA_FSOR
1551 UNSPEC_MSA_FSEQ UNSPEC_MSA_FSNE UNSPEC_MSA_FSUEQ
1552 UNSPEC_MSA_FSUNE UNSPEC_MSA_FSULE UNSPEC_MSA_FSULT
1553 UNSPEC_MSA_FSLE UNSPEC_MSA_FSLT])
1554
1555 (define_int_attr fsc
1556 [(UNSPEC_MSA_FSAF "fsaf")
1557 (UNSPEC_MSA_FSUN "fsun")
1558 (UNSPEC_MSA_FSOR "fsor")
1559 (UNSPEC_MSA_FSEQ "fseq")
1560 (UNSPEC_MSA_FSNE "fsne")
1561 (UNSPEC_MSA_FSUEQ "fsueq")
1562 (UNSPEC_MSA_FSUNE "fsune")
1563 (UNSPEC_MSA_FSULE "fsule")
1564 (UNSPEC_MSA_FSULT "fsult")
1565 (UNSPEC_MSA_FSLE "fsle")
1566 (UNSPEC_MSA_FSLT "fslt")])
1567
1568 (define_insn "msa_<FCC:fcc>_<FMSA:msafmt>"
1569 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1570 (FCC:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")
1571 (match_operand:FMSA 2 "register_operand" "f")))]
1572 "ISA_HAS_MSA"
1573 "<FCC:fcc>.<FMSA:msafmt>\t%w0,%w1,%w2"
1574 [(set_attr "type" "simd_fcmp")
1575 (set_attr "mode" "<MODE>")])
1576
1577 (define_insn "msa_<fsc>_<FMSA:msafmt>"
1578 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1579 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")
1580 (match_operand:FMSA 2 "register_operand" "f")]
1581 FSC_UNS))]
1582 "ISA_HAS_MSA"
1583 "<fsc>.<FMSA:msafmt>\t%w0,%w1,%w2"
1584 [(set_attr "type" "simd_fcmp")
1585 (set_attr "mode" "<MODE>")])
1586
1587 (define_insn "msa_fexp2_<msafmt>"
1588 [(set (match_operand:FMSA 0 "register_operand" "=f")
1589 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")
1590 (match_operand:<VIMODE> 2 "register_operand" "f")]
1591 UNSPEC_MSA_FEXP2))]
1592 "ISA_HAS_MSA"
1593 "fexp2.<msafmt>\t%w0,%w1,%w2"
1594 [(set_attr "type" "simd_fexp2")
1595 (set_attr "mode" "<MODE>")])
1596
1597 (define_mode_attr fint
1598 [(V4SF "v4si")
1599 (V2DF "v2di")])
1600
1601 (define_mode_attr FQ
1602 [(V4SF "V8HI")
1603 (V2DF "V4SI")])
1604
1605 (define_mode_attr FINTCNV
1606 [(V4SF "I2S")
1607 (V2DF "I2D")])
1608
1609 (define_mode_attr FINTCNV_2
1610 [(V4SF "S2I")
1611 (V2DF "D2I")])
1612
1613 (define_insn "float<fint><FMSA:mode>2"
1614 [(set (match_operand:FMSA 0 "register_operand" "=f")
1615 (float:FMSA (match_operand:<VIMODE> 1 "register_operand" "f")))]
1616 "ISA_HAS_MSA"
1617 "ffint_s.<msafmt>\t%w0,%w1"
1618 [(set_attr "type" "simd_fcvt")
1619 (set_attr "cnv_mode" "<FINTCNV>")
1620 (set_attr "mode" "<MODE>")])
1621
1622 (define_insn "floatuns<fint><FMSA:mode>2"
1623 [(set (match_operand:FMSA 0 "register_operand" "=f")
1624 (unsigned_float:FMSA
1625 (match_operand:<VIMODE> 1 "register_operand" "f")))]
1626 "ISA_HAS_MSA"
1627 "ffint_u.<msafmt>\t%w0,%w1"
1628 [(set_attr "type" "simd_fcvt")
1629 (set_attr "cnv_mode" "<FINTCNV>")
1630 (set_attr "mode" "<MODE>")])
1631
1632 (define_mode_attr FFQ
1633 [(V4SF "V8HI")
1634 (V2DF "V4SI")])
1635
1636 (define_insn "msa_ffql_<msafmt>"
1637 [(set (match_operand:FMSA 0 "register_operand" "=f")
1638 (unspec:FMSA [(match_operand:<FQ> 1 "register_operand" "f")]
1639 UNSPEC_MSA_FFQL))]
1640 "ISA_HAS_MSA"
1641 "ffql.<msafmt>\t%w0,%w1"
1642 [(set_attr "type" "simd_fcvt")
1643 (set_attr "cnv_mode" "<FINTCNV>")
1644 (set_attr "mode" "<MODE>")])
1645
1646 (define_insn "msa_ffqr_<msafmt>"
1647 [(set (match_operand:FMSA 0 "register_operand" "=f")
1648 (unspec:FMSA [(match_operand:<FQ> 1 "register_operand" "f")]
1649 UNSPEC_MSA_FFQR))]
1650 "ISA_HAS_MSA"
1651 "ffqr.<msafmt>\t%w0,%w1"
1652 [(set_attr "type" "simd_fcvt")
1653 (set_attr "cnv_mode" "<FINTCNV>")
1654 (set_attr "mode" "<MODE>")])
1655
1656 (define_insn "msa_fill_<msafmt_f>"
1657 [(set (match_operand:MSA 0 "register_operand" "=f,f")
1658 (vec_duplicate:MSA
1659 (match_operand:<UNITMODE> 1 "reg_or_0_operand" "d,J")))]
1660 "ISA_HAS_MSA"
1661 {
1662 if (which_alternative == 1)
1663 return "ldi.<msafmt>\t%w0,0";
1664
1665 if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
1666 return "#";
1667 else
1668 return "fill.<msafmt>\t%w0,%z1";
1669 }
1670 [(set_attr "type" "simd_fill")
1671 (set_attr "mode" "<MODE>")])
1672
1673 (define_split
1674 [(set (match_operand:MSA_D 0 "register_operand")
1675 (vec_duplicate:MSA_D
1676 (match_operand:<UNITMODE> 1 "register_operand")))]
1677 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT"
1678 [(const_int 0)]
1679 {
1680 mips_split_msa_fill_d (operands[0], operands[1]);
1681 DONE;
1682 })
1683
1684 (define_insn "msa_flog2_<msafmt>"
1685 [(set (match_operand:FMSA 0 "register_operand" "=f")
1686 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")]
1687 UNSPEC_MSA_FLOG2))]
1688 "ISA_HAS_MSA"
1689 "flog2.<msafmt>\t%w0,%w1"
1690 [(set_attr "type" "simd_flog2")
1691 (set_attr "mode" "<MODE>")])
1692
1693 (define_insn "smax<mode>3"
1694 [(set (match_operand:FMSA 0 "register_operand" "=f")
1695 (smax:FMSA (match_operand:FMSA 1 "register_operand" "f")
1696 (match_operand:FMSA 2 "register_operand" "f")))]
1697 "ISA_HAS_MSA"
1698 "fmax.<msafmt>\t%w0,%w1,%w2"
1699 [(set_attr "type" "simd_fminmax")
1700 (set_attr "mode" "<MODE>")])
1701
1702 (define_insn "msa_fmax_a_<msafmt>"
1703 [(set (match_operand:FMSA 0 "register_operand" "=f")
1704 (if_then_else:FMSA
1705 (gt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f"))
1706 (abs:FMSA (match_operand:FMSA 2 "register_operand" "f")))
1707 (match_dup 1)
1708 (match_dup 2)))]
1709 "ISA_HAS_MSA"
1710 "fmax_a.<msafmt>\t%w0,%w1,%w2"
1711 [(set_attr "type" "simd_fminmax")
1712 (set_attr "mode" "<MODE>")])
1713
1714 (define_insn "smin<mode>3"
1715 [(set (match_operand:FMSA 0 "register_operand" "=f")
1716 (smin:FMSA (match_operand:FMSA 1 "register_operand" "f")
1717 (match_operand:FMSA 2 "register_operand" "f")))]
1718 "ISA_HAS_MSA"
1719 "fmin.<msafmt>\t%w0,%w1,%w2"
1720 [(set_attr "type" "simd_fminmax")
1721 (set_attr "mode" "<MODE>")])
1722
1723 (define_insn "msa_fmin_a_<msafmt>"
1724 [(set (match_operand:FMSA 0 "register_operand" "=f")
1725 (if_then_else:FMSA
1726 (lt (abs:FMSA (match_operand:FMSA 1 "register_operand" "f"))
1727 (abs:FMSA (match_operand:FMSA 2 "register_operand" "f")))
1728 (match_dup 1)
1729 (match_dup 2)))]
1730 "ISA_HAS_MSA"
1731 "fmin_a.<msafmt>\t%w0,%w1,%w2"
1732 [(set_attr "type" "simd_fminmax")
1733 (set_attr "mode" "<MODE>")])
1734
1735 (define_insn "msa_frcp_<msafmt>"
1736 [(set (match_operand:FMSA 0 "register_operand" "=f")
1737 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")]
1738 UNSPEC_MSA_FRCP))]
1739 "ISA_HAS_MSA"
1740 "frcp.<msafmt>\t%w0,%w1"
1741 [(set_attr "type" "simd_fdiv")
1742 (set_attr "mode" "<MODE>")])
1743
1744 (define_insn "msa_frint_<msafmt>"
1745 [(set (match_operand:FMSA 0 "register_operand" "=f")
1746 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")]
1747 UNSPEC_MSA_FRINT))]
1748 "ISA_HAS_MSA"
1749 "frint.<msafmt>\t%w0,%w1"
1750 [(set_attr "type" "simd_fcvt")
1751 (set_attr "mode" "<MODE>")])
1752
1753 (define_insn "msa_frsqrt_<msafmt>"
1754 [(set (match_operand:FMSA 0 "register_operand" "=f")
1755 (unspec:FMSA [(match_operand:FMSA 1 "register_operand" "f")]
1756 UNSPEC_MSA_FRSQRT))]
1757 "ISA_HAS_MSA"
1758 "frsqrt.<msafmt>\t%w0,%w1"
1759 [(set_attr "type" "simd_fdiv")
1760 (set_attr "mode" "<MODE>")])
1761
1762 (define_insn "msa_ftint_s_<msafmt>"
1763 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1764 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")]
1765 UNSPEC_MSA_FTINT_S))]
1766 "ISA_HAS_MSA"
1767 "ftint_s.<msafmt>\t%w0,%w1"
1768 [(set_attr "type" "simd_fcvt")
1769 (set_attr "cnv_mode" "<FINTCNV_2>")
1770 (set_attr "mode" "<MODE>")])
1771
1772 (define_insn "msa_ftint_u_<msafmt>"
1773 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1774 (unspec:<VIMODE> [(match_operand:FMSA 1 "register_operand" "f")]
1775 UNSPEC_MSA_FTINT_U))]
1776 "ISA_HAS_MSA"
1777 "ftint_u.<msafmt>\t%w0,%w1"
1778 [(set_attr "type" "simd_fcvt")
1779 (set_attr "cnv_mode" "<FINTCNV_2>")
1780 (set_attr "mode" "<MODE>")])
1781
1782 (define_insn "fix_trunc<FMSA:mode><mode_i>2"
1783 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1784 (fix:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")))]
1785 "ISA_HAS_MSA"
1786 "ftrunc_s.<msafmt>\t%w0,%w1"
1787 [(set_attr "type" "simd_fcvt")
1788 (set_attr "cnv_mode" "<FINTCNV_2>")
1789 (set_attr "mode" "<MODE>")])
1790
1791 (define_insn "fixuns_trunc<FMSA:mode><mode_i>2"
1792 [(set (match_operand:<VIMODE> 0 "register_operand" "=f")
1793 (unsigned_fix:<VIMODE> (match_operand:FMSA 1 "register_operand" "f")))]
1794 "ISA_HAS_MSA"
1795 "ftrunc_u.<msafmt>\t%w0,%w1"
1796 [(set_attr "type" "simd_fcvt")
1797 (set_attr "cnv_mode" "<FINTCNV_2>")
1798 (set_attr "mode" "<MODE>")])
1799
1800 (define_insn "msa_ftq_h"
1801 [(set (match_operand:V8HI 0 "register_operand" "=f")
1802 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "f")
1803 (match_operand:V4SF 2 "register_operand" "f")]
1804 UNSPEC_MSA_FTQ))]
1805 "ISA_HAS_MSA"
1806 "ftq.h\t%w0,%w1,%w2"
1807 [(set_attr "type" "simd_fcvt")
1808 (set_attr "cnv_mode" "S2I")
1809 (set_attr "mode" "V4SF")])
1810
1811 (define_insn "msa_ftq_w"
1812 [(set (match_operand:V4SI 0 "register_operand" "=f")
1813 (unspec:V4SI [(match_operand:V2DF 1 "register_operand" "f")
1814 (match_operand:V2DF 2 "register_operand" "f")]
1815 UNSPEC_MSA_FTQ))]
1816 "ISA_HAS_MSA"
1817 "ftq.w\t%w0,%w1,%w2"
1818 [(set_attr "type" "simd_fcvt")
1819 (set_attr "cnv_mode" "D2I")
1820 (set_attr "mode" "V2DF")])
1821
1822 (define_insn "msa_h<optab>_<su>_h"
1823 [(set (match_operand:V8HI 0 "register_operand" "=f")
1824 (addsub:V8HI
1825 (any_extend:V8HI
1826 (vec_select:V8QI
1827 (match_operand:V16QI 1 "register_operand" "f")
1828 (parallel [(const_int 1) (const_int 3)
1829 (const_int 5) (const_int 7)
1830 (const_int 9) (const_int 11)
1831 (const_int 13) (const_int 15)])))
1832 (any_extend:V8HI
1833 (vec_select:V8QI
1834 (match_operand:V16QI 2 "register_operand" "f")
1835 (parallel [(const_int 0) (const_int 2)
1836 (const_int 4) (const_int 6)
1837 (const_int 8) (const_int 10)
1838 (const_int 12) (const_int 14)])))))]
1839 "ISA_HAS_MSA"
1840 "h<optab>_<su>.h\t%w0,%w1,%w2"
1841 [(set_attr "type" "simd_int_arith")
1842 (set_attr "mode" "V8HI")])
1843
1844 (define_insn "msa_h<optab>_<su>_w"
1845 [(set (match_operand:V4SI 0 "register_operand" "=f")
1846 (addsub:V4SI
1847 (any_extend:V4SI
1848 (vec_select:V4HI
1849 (match_operand:V8HI 1 "register_operand" "f")
1850 (parallel [(const_int 1) (const_int 3)
1851 (const_int 5) (const_int 7)])))
1852 (any_extend:V4SI
1853 (vec_select:V4HI
1854 (match_operand:V8HI 2 "register_operand" "f")
1855 (parallel [(const_int 0) (const_int 2)
1856 (const_int 4) (const_int 6)])))))]
1857 "ISA_HAS_MSA"
1858 "h<optab>_<su>.w\t%w0,%w1,%w2"
1859 [(set_attr "type" "simd_int_arith")
1860 (set_attr "mode" "V4SI")])
1861
1862 (define_insn "msa_h<optab>_<su>_d"
1863 [(set (match_operand:V2DI 0 "register_operand" "=f")
1864 (addsub:V2DI
1865 (any_extend:V2DI
1866 (vec_select:V2SI
1867 (match_operand:V4SI 1 "register_operand" "f")
1868 (parallel [(const_int 1) (const_int 3)])))
1869 (any_extend:V2DI
1870 (vec_select:V2SI
1871 (match_operand:V4SI 2 "register_operand" "f")
1872 (parallel [(const_int 0) (const_int 2)])))))]
1873 "ISA_HAS_MSA"
1874 "h<optab>_<su>.d\t%w0,%w1,%w2"
1875 [(set_attr "type" "simd_int_arith")
1876 (set_attr "mode" "V2DI")])
1877
1878 (define_insn "msa_ilvev_b"
1879 [(set (match_operand:V16QI 0 "register_operand" "=f")
1880 (vec_select:V16QI
1881 (vec_concat:V32QI
1882 (match_operand:V16QI 1 "register_operand" "f")
1883 (match_operand:V16QI 2 "register_operand" "f"))
1884 (parallel [(const_int 0) (const_int 16)
1885 (const_int 2) (const_int 18)
1886 (const_int 4) (const_int 20)
1887 (const_int 6) (const_int 22)
1888 (const_int 8) (const_int 24)
1889 (const_int 10) (const_int 26)
1890 (const_int 12) (const_int 28)
1891 (const_int 14) (const_int 30)])))]
1892 "ISA_HAS_MSA"
1893 "ilvev.b\t%w0,%w2,%w1"
1894 [(set_attr "type" "simd_permute")
1895 (set_attr "mode" "V16QI")])
1896
1897 (define_insn "msa_ilvev_h"
1898 [(set (match_operand:V8HI 0 "register_operand" "=f")
1899 (vec_select:V8HI
1900 (vec_concat:V16HI
1901 (match_operand:V8HI 1 "register_operand" "f")
1902 (match_operand:V8HI 2 "register_operand" "f"))
1903 (parallel [(const_int 0) (const_int 8)
1904 (const_int 2) (const_int 10)
1905 (const_int 4) (const_int 12)
1906 (const_int 6) (const_int 14)])))]
1907 "ISA_HAS_MSA"
1908 "ilvev.h\t%w0,%w2,%w1"
1909 [(set_attr "type" "simd_permute")
1910 (set_attr "mode" "V8HI")])
1911
1912 (define_insn "msa_ilvev_w"
1913 [(set (match_operand:V4SI 0 "register_operand" "=f")
1914 (vec_select:V4SI
1915 (vec_concat:V8SI
1916 (match_operand:V4SI 1 "register_operand" "f")
1917 (match_operand:V4SI 2 "register_operand" "f"))
1918 (parallel [(const_int 0) (const_int 4)
1919 (const_int 2) (const_int 6)])))]
1920 "ISA_HAS_MSA"
1921 "ilvev.w\t%w0,%w2,%w1"
1922 [(set_attr "type" "simd_permute")
1923 (set_attr "mode" "V4SI")])
1924
1925 (define_insn "msa_ilvev_w_f"
1926 [(set (match_operand:V4SF 0 "register_operand" "=f")
1927 (vec_select:V4SF
1928 (vec_concat:V8SF
1929 (match_operand:V4SF 1 "register_operand" "f")
1930 (match_operand:V4SF 2 "register_operand" "f"))
1931 (parallel [(const_int 0) (const_int 4)
1932 (const_int 2) (const_int 6)])))]
1933 "ISA_HAS_MSA"
1934 "ilvev.w\t%w0,%w2,%w1"
1935 [(set_attr "type" "simd_permute")
1936 (set_attr "mode" "V4SF")])
1937
1938 (define_insn "msa_ilvl_b"
1939 [(set (match_operand:V16QI 0 "register_operand" "=f")
1940 (vec_select:V16QI
1941 (vec_concat:V32QI
1942 (match_operand:V16QI 1 "register_operand" "f")
1943 (match_operand:V16QI 2 "register_operand" "f"))
1944 (parallel [(const_int 8) (const_int 24)
1945 (const_int 9) (const_int 25)
1946 (const_int 10) (const_int 26)
1947 (const_int 11) (const_int 27)
1948 (const_int 12) (const_int 28)
1949 (const_int 13) (const_int 29)
1950 (const_int 14) (const_int 30)
1951 (const_int 15) (const_int 31)])))]
1952 "ISA_HAS_MSA"
1953 "ilvl.b\t%w0,%w2,%w1"
1954 [(set_attr "type" "simd_permute")
1955 (set_attr "mode" "V16QI")])
1956
1957 (define_insn "msa_ilvl_h"
1958 [(set (match_operand:V8HI 0 "register_operand" "=f")
1959 (vec_select:V8HI
1960 (vec_concat:V16HI
1961 (match_operand:V8HI 1 "register_operand" "f")
1962 (match_operand:V8HI 2 "register_operand" "f"))
1963 (parallel [(const_int 4) (const_int 12)
1964 (const_int 5) (const_int 13)
1965 (const_int 6) (const_int 14)
1966 (const_int 7) (const_int 15)])))]
1967 "ISA_HAS_MSA"
1968 "ilvl.h\t%w0,%w2,%w1"
1969 [(set_attr "type" "simd_permute")
1970 (set_attr "mode" "V8HI")])
1971
1972 (define_insn "msa_ilvl_w"
1973 [(set (match_operand:V4SI 0 "register_operand" "=f")
1974 (vec_select:V4SI
1975 (vec_concat:V8SI
1976 (match_operand:V4SI 1 "register_operand" "f")
1977 (match_operand:V4SI 2 "register_operand" "f"))
1978 (parallel [(const_int 2) (const_int 6)
1979 (const_int 3) (const_int 7)])))]
1980 "ISA_HAS_MSA"
1981 "ilvl.w\t%w0,%w2,%w1"
1982 [(set_attr "type" "simd_permute")
1983 (set_attr "mode" "V4SI")])
1984
1985 (define_insn "msa_ilvl_w_f"
1986 [(set (match_operand:V4SF 0 "register_operand" "=f")
1987 (vec_select:V4SF
1988 (vec_concat:V8SF
1989 (match_operand:V4SF 1 "register_operand" "f")
1990 (match_operand:V4SF 2 "register_operand" "f"))
1991 (parallel [(const_int 2) (const_int 6)
1992 (const_int 3) (const_int 7)])))]
1993 "ISA_HAS_MSA"
1994 "ilvl.w\t%w0,%w2,%w1"
1995 [(set_attr "type" "simd_permute")
1996 (set_attr "mode" "V4SF")])
1997
1998 (define_insn "msa_ilvl_d"
1999 [(set (match_operand:V2DI 0 "register_operand" "=f")
2000 (vec_select:V2DI
2001 (vec_concat:V4DI
2002 (match_operand:V2DI 1 "register_operand" "f")
2003 (match_operand:V2DI 2 "register_operand" "f"))
2004 (parallel [(const_int 1) (const_int 3)])))]
2005 "ISA_HAS_MSA"
2006 "ilvl.d\t%w0,%w2,%w1"
2007 [(set_attr "type" "simd_permute")
2008 (set_attr "mode" "V2DI")])
2009
2010 (define_insn "msa_ilvl_d_f"
2011 [(set (match_operand:V2DF 0 "register_operand" "=f")
2012 (vec_select:V2DF
2013 (vec_concat:V4DF
2014 (match_operand:V2DF 1 "register_operand" "f")
2015 (match_operand:V2DF 2 "register_operand" "f"))
2016 (parallel [(const_int 1) (const_int 3)])))]
2017 "ISA_HAS_MSA"
2018 "ilvl.d\t%w0,%w2,%w1"
2019 [(set_attr "type" "simd_permute")
2020 (set_attr "mode" "V2DF")])
2021
2022 (define_insn "msa_ilvod_b"
2023 [(set (match_operand:V16QI 0 "register_operand" "=f")
2024 (vec_select:V16QI
2025 (vec_concat:V32QI
2026 (match_operand:V16QI 1 "register_operand" "f")
2027 (match_operand:V16QI 2 "register_operand" "f"))
2028 (parallel [(const_int 1) (const_int 17)
2029 (const_int 3) (const_int 19)
2030 (const_int 5) (const_int 21)
2031 (const_int 7) (const_int 23)
2032 (const_int 9) (const_int 25)
2033 (const_int 11) (const_int 27)
2034 (const_int 13) (const_int 29)
2035 (const_int 15) (const_int 31)])))]
2036 "ISA_HAS_MSA"
2037 "ilvod.b\t%w0,%w2,%w1"
2038 [(set_attr "type" "simd_permute")
2039 (set_attr "mode" "V16QI")])
2040
2041 (define_insn "msa_ilvod_h"
2042 [(set (match_operand:V8HI 0 "register_operand" "=f")
2043 (vec_select:V8HI
2044 (vec_concat:V16HI
2045 (match_operand:V8HI 1 "register_operand" "f")
2046 (match_operand:V8HI 2 "register_operand" "f"))
2047 (parallel [(const_int 1) (const_int 9)
2048 (const_int 3) (const_int 11)
2049 (const_int 5) (const_int 13)
2050 (const_int 7) (const_int 15)])))]
2051 "ISA_HAS_MSA"
2052 "ilvod.h\t%w0,%w2,%w1"
2053 [(set_attr "type" "simd_permute")
2054 (set_attr "mode" "V8HI")])
2055
2056 (define_insn "msa_ilvod_w"
2057 [(set (match_operand:V4SI 0 "register_operand" "=f")
2058 (vec_select:V4SI
2059 (vec_concat:V8SI
2060 (match_operand:V4SI 1 "register_operand" "f")
2061 (match_operand:V4SI 2 "register_operand" "f"))
2062 (parallel [(const_int 1) (const_int 5)
2063 (const_int 3) (const_int 7)])))]
2064 "ISA_HAS_MSA"
2065 "ilvod.w\t%w0,%w2,%w1"
2066 [(set_attr "type" "simd_permute")
2067 (set_attr "mode" "V4SI")])
2068
2069 (define_insn "msa_ilvod_w_f"
2070 [(set (match_operand:V4SF 0 "register_operand" "=f")
2071 (vec_select:V4SF
2072 (vec_concat:V8SF
2073 (match_operand:V4SF 1 "register_operand" "f")
2074 (match_operand:V4SF 2 "register_operand" "f"))
2075 (parallel [(const_int 1) (const_int 5)
2076 (const_int 3) (const_int 7)])))]
2077 "ISA_HAS_MSA"
2078 "ilvod.w\t%w0,%w2,%w1"
2079 [(set_attr "type" "simd_permute")
2080 (set_attr "mode" "V4SF")])
2081
2082 (define_insn "msa_ilvr_b"
2083 [(set (match_operand:V16QI 0 "register_operand" "=f")
2084 (vec_select:V16QI
2085 (vec_concat:V32QI
2086 (match_operand:V16QI 1 "register_operand" "f")
2087 (match_operand:V16QI 2 "register_operand" "f"))
2088 (parallel [(const_int 0) (const_int 16)
2089 (const_int 1) (const_int 17)
2090 (const_int 2) (const_int 18)
2091 (const_int 3) (const_int 19)
2092 (const_int 4) (const_int 20)
2093 (const_int 5) (const_int 21)
2094 (const_int 6) (const_int 22)
2095 (const_int 7) (const_int 23)])))]
2096 "ISA_HAS_MSA"
2097 "ilvr.b\t%w0,%w2,%w1"
2098 [(set_attr "type" "simd_permute")
2099 (set_attr "mode" "V16QI")])
2100
2101 (define_insn "msa_ilvr_h"
2102 [(set (match_operand:V8HI 0 "register_operand" "=f")
2103 (vec_select:V8HI
2104 (vec_concat:V16HI
2105 (match_operand:V8HI 1 "register_operand" "f")
2106 (match_operand:V8HI 2 "register_operand" "f"))
2107 (parallel [(const_int 0) (const_int 8)
2108 (const_int 1) (const_int 9)
2109 (const_int 2) (const_int 10)
2110 (const_int 3) (const_int 11)])))]
2111 "ISA_HAS_MSA"
2112 "ilvr.h\t%w0,%w2,%w1"
2113 [(set_attr "type" "simd_permute")
2114 (set_attr "mode" "V8HI")])
2115
2116 (define_insn "msa_ilvr_w"
2117 [(set (match_operand:V4SI 0 "register_operand" "=f")
2118 (vec_select:V4SI
2119 (vec_concat:V8SI
2120 (match_operand:V4SI 1 "register_operand" "f")
2121 (match_operand:V4SI 2 "register_operand" "f"))
2122 (parallel [(const_int 0) (const_int 4)
2123 (const_int 1) (const_int 5)])))]
2124 "ISA_HAS_MSA"
2125 "ilvr.w\t%w0,%w2,%w1"
2126 [(set_attr "type" "simd_permute")
2127 (set_attr "mode" "V4SI")])
2128
2129 (define_insn "msa_ilvr_w_f"
2130 [(set (match_operand:V4SF 0 "register_operand" "=f")
2131 (vec_select:V4SF
2132 (vec_concat:V8SF
2133 (match_operand:V4SF 1 "register_operand" "f")
2134 (match_operand:V4SF 2 "register_operand" "f"))
2135 (parallel [(const_int 0) (const_int 4)
2136 (const_int 1) (const_int 5)])))]
2137 "ISA_HAS_MSA"
2138 "ilvr.w\t%w0,%w2,%w1"
2139 [(set_attr "type" "simd_permute")
2140 (set_attr "mode" "V4SF")])
2141
2142 (define_insn "msa_ilvr_d"
2143 [(set (match_operand:V2DI 0 "register_operand" "=f")
2144 (vec_select:V2DI
2145 (vec_concat:V4DI
2146 (match_operand:V2DI 1 "register_operand" "f")
2147 (match_operand:V2DI 2 "register_operand" "f"))
2148 (parallel [(const_int 0) (const_int 2)])))]
2149 "ISA_HAS_MSA"
2150 "ilvr.d\t%w0,%w2,%w1"
2151 [(set_attr "type" "simd_permute")
2152 (set_attr "mode" "V2DI")])
2153
2154 (define_insn "msa_ilvr_d_f"
2155 [(set (match_operand:V2DF 0 "register_operand" "=f")
2156 (vec_select:V2DF
2157 (vec_concat:V4DF
2158 (match_operand:V2DF 1 "register_operand" "f")
2159 (match_operand:V2DF 2 "register_operand" "f"))
2160 (parallel [(const_int 0) (const_int 2)])))]
2161 "ISA_HAS_MSA"
2162 "ilvr.d\t%w0,%w2,%w1"
2163 [(set_attr "type" "simd_permute")
2164 (set_attr "mode" "V2DF")])
2165
2166 (define_insn "msa_madd_q_<msafmt>"
2167 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2168 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0")
2169 (match_operand:IMSA_WH 2 "register_operand" "f")
2170 (match_operand:IMSA_WH 3 "register_operand" "f")]
2171 UNSPEC_MSA_MADD_Q))]
2172 "ISA_HAS_MSA"
2173 "madd_q.<msafmt>\t%w0,%w2,%w3"
2174 [(set_attr "type" "simd_mul")
2175 (set_attr "mode" "<MODE>")])
2176
2177 (define_insn "msa_maddr_q_<msafmt>"
2178 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2179 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0")
2180 (match_operand:IMSA_WH 2 "register_operand" "f")
2181 (match_operand:IMSA_WH 3 "register_operand" "f")]
2182 UNSPEC_MSA_MADDR_Q))]
2183 "ISA_HAS_MSA"
2184 "maddr_q.<msafmt>\t%w0,%w2,%w3"
2185 [(set_attr "type" "simd_mul")
2186 (set_attr "mode" "<MODE>")])
2187
2188 (define_insn "msa_max_a_<msafmt>"
2189 [(set (match_operand:IMSA 0 "register_operand" "=f")
2190 (if_then_else:IMSA
2191 (gt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
2192 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f")))
2193 (match_dup 1)
2194 (match_dup 2)))]
2195 "ISA_HAS_MSA"
2196 "max_a.<msafmt>\t%w0,%w1,%w2"
2197 [(set_attr "type" "simd_int_arith")
2198 (set_attr "mode" "<MODE>")])
2199
2200 (define_insn "smax<mode>3"
2201 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2202 (smax:IMSA (match_operand:IMSA 1 "register_operand" "f,f")
2203 (match_operand:IMSA 2 "reg_or_vector_same_simm5_operand" "f,Usv5")))]
2204 "ISA_HAS_MSA"
2205 "@
2206 max_s.<msafmt>\t%w0,%w1,%w2
2207 maxi_s.<msafmt>\t%w0,%w1,%E2"
2208 [(set_attr "type" "simd_int_arith")
2209 (set_attr "mode" "<MODE>")])
2210
2211 (define_insn "umax<mode>3"
2212 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2213 (umax:IMSA (match_operand:IMSA 1 "register_operand" "f,f")
2214 (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))]
2215 "ISA_HAS_MSA"
2216 "@
2217 max_u.<msafmt>\t%w0,%w1,%w2
2218 maxi_u.<msafmt>\t%w0,%w1,%B2"
2219 [(set_attr "type" "simd_int_arith")
2220 (set_attr "mode" "<MODE>")])
2221
2222 (define_insn "msa_min_a_<msafmt>"
2223 [(set (match_operand:IMSA 0 "register_operand" "=f")
2224 (if_then_else:IMSA
2225 (lt (abs:IMSA (match_operand:IMSA 1 "register_operand" "f"))
2226 (abs:IMSA (match_operand:IMSA 2 "register_operand" "f")))
2227 (match_dup 1)
2228 (match_dup 2)))]
2229 "ISA_HAS_MSA"
2230 "min_a.<msafmt>\t%w0,%w1,%w2"
2231 [(set_attr "type" "simd_int_arith")
2232 (set_attr "mode" "<MODE>")])
2233
2234 (define_insn "smin<mode>3"
2235 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2236 (smin:IMSA (match_operand:IMSA 1 "register_operand" "f,f")
2237 (match_operand:IMSA 2 "reg_or_vector_same_simm5_operand" "f,Usv5")))]
2238 "ISA_HAS_MSA"
2239 "@
2240 min_s.<msafmt>\t%w0,%w1,%w2
2241 mini_s.<msafmt>\t%w0,%w1,%E2"
2242 [(set_attr "type" "simd_int_arith")
2243 (set_attr "mode" "<MODE>")])
2244
2245 (define_insn "umin<mode>3"
2246 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2247 (umin:IMSA (match_operand:IMSA 1 "register_operand" "f,f")
2248 (match_operand:IMSA 2 "reg_or_vector_same_uimm5_operand" "f,Uuv5")))]
2249 "ISA_HAS_MSA"
2250 "@
2251 min_u.<msafmt>\t%w0,%w1,%w2
2252 mini_u.<msafmt>\t%w0,%w1,%B2"
2253 [(set_attr "type" "simd_int_arith")
2254 (set_attr "mode" "<MODE>")])
2255
2256 (define_insn "msa_msub_q_<msafmt>"
2257 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2258 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0")
2259 (match_operand:IMSA_WH 2 "register_operand" "f")
2260 (match_operand:IMSA_WH 3 "register_operand" "f")]
2261 UNSPEC_MSA_MSUB_Q))]
2262 "ISA_HAS_MSA"
2263 "msub_q.<msafmt>\t%w0,%w2,%w3"
2264 [(set_attr "type" "simd_mul")
2265 (set_attr "mode" "<MODE>")])
2266
2267 (define_insn "msa_msubr_q_<msafmt>"
2268 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2269 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "0")
2270 (match_operand:IMSA_WH 2 "register_operand" "f")
2271 (match_operand:IMSA_WH 3 "register_operand" "f")]
2272 UNSPEC_MSA_MSUBR_Q))]
2273 "ISA_HAS_MSA"
2274 "msubr_q.<msafmt>\t%w0,%w2,%w3"
2275 [(set_attr "type" "simd_mul")
2276 (set_attr "mode" "<MODE>")])
2277
2278 (define_insn "msa_mul_q_<msafmt>"
2279 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2280 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "f")
2281 (match_operand:IMSA_WH 2 "register_operand" "f")]
2282 UNSPEC_MSA_MUL_Q))]
2283 "ISA_HAS_MSA"
2284 "mul_q.<msafmt>\t%w0,%w1,%w2"
2285 [(set_attr "type" "simd_mul")
2286 (set_attr "mode" "<MODE>")])
2287
2288 (define_insn "msa_mulr_q_<msafmt>"
2289 [(set (match_operand:IMSA_WH 0 "register_operand" "=f")
2290 (unspec:IMSA_WH [(match_operand:IMSA_WH 1 "register_operand" "f")
2291 (match_operand:IMSA_WH 2 "register_operand" "f")]
2292 UNSPEC_MSA_MULR_Q))]
2293 "ISA_HAS_MSA"
2294 "mulr_q.<msafmt>\t%w0,%w1,%w2"
2295 [(set_attr "type" "simd_mul")
2296 (set_attr "mode" "<MODE>")])
2297
2298 (define_insn "msa_nloc_<msafmt>"
2299 [(set (match_operand:IMSA 0 "register_operand" "=f")
2300 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")]
2301 UNSPEC_MSA_NLOC))]
2302 "ISA_HAS_MSA"
2303 "nloc.<msafmt>\t%w0,%w1"
2304 [(set_attr "type" "simd_bit")
2305 (set_attr "mode" "<MODE>")])
2306
2307 (define_insn "clz<mode>2"
2308 [(set (match_operand:IMSA 0 "register_operand" "=f")
2309 (clz:IMSA (match_operand:IMSA 1 "register_operand" "f")))]
2310 "ISA_HAS_MSA"
2311 "nlzc.<msafmt>\t%w0,%w1"
2312 [(set_attr "type" "simd_bit")
2313 (set_attr "mode" "<MODE>")])
2314
2315 (define_insn "msa_nor_<msafmt>"
2316 [(set (match_operand:IMSA 0 "register_operand" "=f,f")
2317 (and:IMSA (not:IMSA (match_operand:IMSA 1 "register_operand" "f,f"))
2318 (not:IMSA (match_operand:IMSA 2 "reg_or_vector_same_val_operand" "f,Urv8"))))]
2319 "ISA_HAS_MSA"
2320 "@
2321 nor.v\t%w0,%w1,%w2
2322 nori.b\t%w0,%w1,%B2"
2323 [(set_attr "type" "simd_logic")
2324 (set_attr "mode" "<MODE>")])
2325
2326 (define_insn "msa_pckev_b"
2327 [(set (match_operand:V16QI 0 "register_operand" "=f")
2328 (vec_select:V16QI
2329 (vec_concat:V32QI
2330 (match_operand:V16QI 1 "register_operand" "f")
2331 (match_operand:V16QI 2 "register_operand" "f"))
2332 (parallel [(const_int 0) (const_int 2)
2333 (const_int 4) (const_int 6)
2334 (const_int 8) (const_int 10)
2335 (const_int 12) (const_int 14)
2336 (const_int 16) (const_int 18)
2337 (const_int 20) (const_int 22)
2338 (const_int 24) (const_int 26)
2339 (const_int 28) (const_int 30)])))]
2340 "ISA_HAS_MSA"
2341 "pckev.b\t%w0,%w2,%w1"
2342 [(set_attr "type" "simd_permute")
2343 (set_attr "mode" "V16QI")])
2344
2345 (define_insn "msa_pckev_h"
2346 [(set (match_operand:V8HI 0 "register_operand" "=f")
2347 (vec_select:V8HI
2348 (vec_concat:V16HI
2349 (match_operand:V8HI 1 "register_operand" "f")
2350 (match_operand:V8HI 2 "register_operand" "f"))
2351 (parallel [(const_int 0) (const_int 2)
2352 (const_int 4) (const_int 6)
2353 (const_int 8) (const_int 10)
2354 (const_int 12) (const_int 14)])))]
2355 "ISA_HAS_MSA"
2356 "pckev.h\t%w0,%w2,%w1"
2357 [(set_attr "type" "simd_permute")
2358 (set_attr "mode" "V8HI")])
2359
2360 (define_insn "msa_pckev_w"
2361 [(set (match_operand:V4SI 0 "register_operand" "=f")
2362 (vec_select:V4SI
2363 (vec_concat:V8SI
2364 (match_operand:V4SI 1 "register_operand" "f")
2365 (match_operand:V4SI 2 "register_operand" "f"))
2366 (parallel [(const_int 0) (const_int 2)
2367 (const_int 4) (const_int 6)])))]
2368 "ISA_HAS_MSA"
2369 "pckev.w\t%w0,%w2,%w1"
2370 [(set_attr "type" "simd_permute")
2371 (set_attr "mode" "V4SI")])
2372
2373 (define_insn "msa_pckev_w_f"
2374 [(set (match_operand:V4SF 0 "register_operand" "=f")
2375 (vec_select:V4SF
2376 (vec_concat:V8SF
2377 (match_operand:V4SF 1 "register_operand" "f")
2378 (match_operand:V4SF 2 "register_operand" "f"))
2379 (parallel [(const_int 0) (const_int 2)
2380 (const_int 4) (const_int 6)])))]
2381 "ISA_HAS_MSA"
2382 "pckev.w\t%w0,%w2,%w1"
2383 [(set_attr "type" "simd_permute")
2384 (set_attr "mode" "V4SF")])
2385
2386 (define_insn "msa_pckod_b"
2387 [(set (match_operand:V16QI 0 "register_operand" "=f")
2388 (vec_select:V16QI
2389 (vec_concat:V32QI
2390 (match_operand:V16QI 1 "register_operand" "f")
2391 (match_operand:V16QI 2 "register_operand" "f"))
2392 (parallel [(const_int 1) (const_int 3)
2393 (const_int 5) (const_int 7)
2394 (const_int 9) (const_int 11)
2395 (const_int 13) (const_int 15)
2396 (const_int 17) (const_int 19)
2397 (const_int 21) (const_int 23)
2398 (const_int 25) (const_int 27)
2399 (const_int 29) (const_int 31)])))]
2400 "ISA_HAS_MSA"
2401 "pckod.b\t%w0,%w2,%w1"
2402 [(set_attr "type" "simd_permute")
2403 (set_attr "mode" "V16QI")])
2404
2405 (define_insn "msa_pckod_h"
2406 [(set (match_operand:V8HI 0 "register_operand" "=f")
2407 (vec_select:V8HI
2408 (vec_concat:V16HI
2409 (match_operand:V8HI 1 "register_operand" "f")
2410 (match_operand:V8HI 2 "register_operand" "f"))
2411 (parallel [(const_int 1) (const_int 3)
2412 (const_int 5) (const_int 7)
2413 (const_int 9) (const_int 11)
2414 (const_int 13) (const_int 15)])))]
2415 "ISA_HAS_MSA"
2416 "pckod.h\t%w0,%w2,%w1"
2417 [(set_attr "type" "simd_permute")
2418 (set_attr "mode" "V8HI")])
2419
2420 (define_insn "msa_pckod_w"
2421 [(set (match_operand:V4SI 0 "register_operand" "=f")
2422 (vec_select:V4SI
2423 (vec_concat:V8SI
2424 (match_operand:V4SI 1 "register_operand" "f")
2425 (match_operand:V4SI 2 "register_operand" "f"))
2426 (parallel [(const_int 1) (const_int 3)
2427 (const_int 5) (const_int 7)])))]
2428 "ISA_HAS_MSA"
2429 "pckod.w\t%w0,%w2,%w1"
2430 [(set_attr "type" "simd_permute")
2431 (set_attr "mode" "V4SI")])
2432
2433 (define_insn "msa_pckod_w_f"
2434 [(set (match_operand:V4SF 0 "register_operand" "=f")
2435 (vec_select:V4SF
2436 (vec_concat:V8SF
2437 (match_operand:V4SF 1 "register_operand" "f")
2438 (match_operand:V4SF 2 "register_operand" "f"))
2439 (parallel [(const_int 1) (const_int 3)
2440 (const_int 5) (const_int 7)])))]
2441 "ISA_HAS_MSA"
2442 "pckod.w\t%w0,%w2,%w1"
2443 [(set_attr "type" "simd_permute")
2444 (set_attr "mode" "V4SF")])
2445
2446 (define_insn "popcount<mode>2"
2447 [(set (match_operand:IMSA 0 "register_operand" "=f")
2448 (popcount:IMSA (match_operand:IMSA 1 "register_operand" "f")))]
2449 "ISA_HAS_MSA"
2450 "pcnt.<msafmt>\t%w0,%w1"
2451 [(set_attr "type" "simd_pcnt")
2452 (set_attr "mode" "<MODE>")])
2453
2454 (define_insn "msa_sat_s_<msafmt>"
2455 [(set (match_operand:IMSA 0 "register_operand" "=f")
2456 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2457 (match_operand 2 "const_<bitimm>_operand" "")]
2458 UNSPEC_MSA_SAT_S))]
2459 "ISA_HAS_MSA"
2460 "sat_s.<msafmt>\t%w0,%w1,%2"
2461 [(set_attr "type" "simd_sat")
2462 (set_attr "mode" "<MODE>")])
2463
2464 (define_insn "msa_sat_u_<msafmt>"
2465 [(set (match_operand:IMSA 0 "register_operand" "=f")
2466 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2467 (match_operand 2 "const_<bitimm>_operand" "")]
2468 UNSPEC_MSA_SAT_U))]
2469 "ISA_HAS_MSA"
2470 "sat_u.<msafmt>\t%w0,%w1,%2"
2471 [(set_attr "type" "simd_sat")
2472 (set_attr "mode" "<MODE>")])
2473
2474 (define_insn "msa_shf_<msafmt_f>"
2475 [(set (match_operand:MSA_WHB_W 0 "register_operand" "=f")
2476 (vec_select:MSA_WHB_W
2477 (match_operand:MSA_WHB_W 1 "register_operand" "f")
2478 (match_operand 2 "par_const_vector_shf_set_operand" "")))]
2479 "ISA_HAS_MSA"
2480 {
2481 HOST_WIDE_INT val = 0;
2482 unsigned int i;
2483
2484 /* We convert the selection to an immediate. */
2485 for (i = 0; i < 4; i++)
2486 val |= INTVAL (XVECEXP (operands[2], 0, i)) << (2 * i);
2487
2488 operands[2] = GEN_INT (val);
2489 return "shf.<msafmt>\t%w0,%w1,%X2";
2490 }
2491 [(set_attr "type" "simd_shf")
2492 (set_attr "mode" "<MODE>")])
2493
2494 (define_insn "msa_srar_<msafmt>"
2495 [(set (match_operand:IMSA 0 "register_operand" "=f")
2496 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2497 (match_operand:IMSA 2 "register_operand" "f")]
2498 UNSPEC_MSA_SRAR))]
2499 "ISA_HAS_MSA"
2500 "srar.<msafmt>\t%w0,%w1,%w2"
2501 [(set_attr "type" "simd_shift")
2502 (set_attr "mode" "<MODE>")])
2503
2504 (define_insn "msa_srari_<msafmt>"
2505 [(set (match_operand:IMSA 0 "register_operand" "=f")
2506 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2507 (match_operand 2 "const_<bitimm>_operand" "")]
2508 UNSPEC_MSA_SRARI))]
2509 "ISA_HAS_MSA"
2510 "srari.<msafmt>\t%w0,%w1,%2"
2511 [(set_attr "type" "simd_shift")
2512 (set_attr "mode" "<MODE>")])
2513
2514 (define_insn "msa_srlr_<msafmt>"
2515 [(set (match_operand:IMSA 0 "register_operand" "=f")
2516 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2517 (match_operand:IMSA 2 "register_operand" "f")]
2518 UNSPEC_MSA_SRLR))]
2519 "ISA_HAS_MSA"
2520 "srlr.<msafmt>\t%w0,%w1,%w2"
2521 [(set_attr "type" "simd_shift")
2522 (set_attr "mode" "<MODE>")])
2523
2524 (define_insn "msa_srlri_<msafmt>"
2525 [(set (match_operand:IMSA 0 "register_operand" "=f")
2526 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2527 (match_operand 2 "const_<bitimm>_operand" "")]
2528 UNSPEC_MSA_SRLRI))]
2529 "ISA_HAS_MSA"
2530 "srlri.<msafmt>\t%w0,%w1,%2"
2531 [(set_attr "type" "simd_shift")
2532 (set_attr "mode" "<MODE>")])
2533
2534 (define_insn "msa_subs_s_<msafmt>"
2535 [(set (match_operand:IMSA 0 "register_operand" "=f")
2536 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2537 (match_operand:IMSA 2 "register_operand" "f")]
2538 UNSPEC_MSA_SUBS_S))]
2539 "ISA_HAS_MSA"
2540 "subs_s.<msafmt>\t%w0,%w1,%w2"
2541 [(set_attr "type" "simd_int_arith")
2542 (set_attr "mode" "<MODE>")])
2543
2544 (define_insn "msa_subs_u_<msafmt>"
2545 [(set (match_operand:IMSA 0 "register_operand" "=f")
2546 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2547 (match_operand:IMSA 2 "register_operand" "f")]
2548 UNSPEC_MSA_SUBS_U))]
2549 "ISA_HAS_MSA"
2550 "subs_u.<msafmt>\t%w0,%w1,%w2"
2551 [(set_attr "type" "simd_int_arith")
2552 (set_attr "mode" "<MODE>")])
2553
2554 (define_insn "msa_subsuu_s_<msafmt>"
2555 [(set (match_operand:IMSA 0 "register_operand" "=f")
2556 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2557 (match_operand:IMSA 2 "register_operand" "f")]
2558 UNSPEC_MSA_SUBSUU_S))]
2559 "ISA_HAS_MSA"
2560 "subsuu_s.<msafmt>\t%w0,%w1,%w2"
2561 [(set_attr "type" "simd_int_arith")
2562 (set_attr "mode" "<MODE>")])
2563
2564 (define_insn "msa_subsus_u_<msafmt>"
2565 [(set (match_operand:IMSA 0 "register_operand" "=f")
2566 (unspec:IMSA [(match_operand:IMSA 1 "register_operand" "f")
2567 (match_operand:IMSA 2 "register_operand" "f")]
2568 UNSPEC_MSA_SUBSUS_U))]
2569 "ISA_HAS_MSA"
2570 "subsus_u.<msafmt>\t%w0,%w1,%w2"
2571 [(set_attr "type" "simd_int_arith")
2572 (set_attr "mode" "<MODE>")])
2573
2574 (define_insn "msa_sld_<msafmt_f>"
2575 [(set (match_operand:MSA 0 "register_operand" "=f")
2576 (unspec:MSA [(match_operand:MSA 1 "register_operand" "0")
2577 (match_operand:MSA 2 "register_operand" "f")
2578 (match_operand:SI 3 "reg_or_0_operand" "dJ")]
2579 UNSPEC_MSA_SLD))]
2580 "ISA_HAS_MSA"
2581 "sld.<msafmt>\t%w0,%w2[%z3]"
2582 [(set_attr "type" "simd_sld")
2583 (set_attr "mode" "<MODE>")])
2584
2585 (define_insn "msa_sldi_<msafmt_f>"
2586 [(set (match_operand:MSA 0 "register_operand" "=f")
2587 (unspec:MSA [(match_operand:MSA 1 "register_operand" "0")
2588 (match_operand:MSA 2 "register_operand" "f")
2589 (match_operand 3 "const_<indeximm>_operand" "")]
2590 UNSPEC_MSA_SLDI))]
2591 "ISA_HAS_MSA"
2592 "sldi.<msafmt>\t%w0,%w2[%3]"
2593 [(set_attr "type" "simd_sld")
2594 (set_attr "mode" "<MODE>")])
2595
2596 (define_insn "msa_splat_<msafmt_f>"
2597 [(set (match_operand:MSA 0 "register_operand" "=f")
2598 (unspec:MSA [(match_operand:MSA 1 "register_operand" "f")
2599 (match_operand:SI 2 "register_operand" "d")]
2600 UNSPEC_MSA_SPLAT))]
2601 "ISA_HAS_MSA"
2602 "splat.<msafmt>\t%w0,%w1[%z2]"
2603 [(set_attr "type" "simd_splat")
2604 (set_attr "mode" "<MODE>")])
2605
2606 (define_insn "msa_splati_<msafmt_f>"
2607 [(set (match_operand:MSA 0 "register_operand" "=f")
2608 (vec_duplicate:MSA
2609 (vec_select:<UNITMODE>
2610 (match_operand:MSA 1 "register_operand" "f")
2611 (parallel [(match_operand 2 "const_<indeximm>_operand" "")]))))]
2612 "ISA_HAS_MSA"
2613 "splati.<msafmt>\t%w0,%w1[%2]"
2614 [(set_attr "type" "simd_splat")
2615 (set_attr "mode" "<MODE>")])
2616
2617 (define_insn "msa_splati_<msafmt_f>_scalar"
2618 [(set (match_operand:FMSA 0 "register_operand" "=f")
2619 (unspec:FMSA [(match_operand:<UNITMODE> 1 "register_operand" "f")]
2620 UNSPEC_MSA_SPLATI))]
2621 "ISA_HAS_MSA"
2622 "splati.<msafmt>\t%w0,%w1[0]"
2623 [(set_attr "type" "simd_splat")
2624 (set_attr "mode" "<MODE>")])
2625
2626 (define_insn "msa_cfcmsa"
2627 [(set (match_operand:SI 0 "register_operand" "=d")
2628 (unspec_volatile:SI [(match_operand 1 "const_uimm5_operand" "")]
2629 UNSPEC_MSA_CFCMSA))]
2630 "ISA_HAS_MSA"
2631 "cfcmsa\t%0,$%1"
2632 [(set_attr "type" "simd_cmsa")
2633 (set_attr "mode" "SI")])
2634
2635 (define_insn "msa_ctcmsa"
2636 [(unspec_volatile [(match_operand 0 "const_uimm5_operand" "")
2637 (match_operand:SI 1 "register_operand" "d")]
2638 UNSPEC_MSA_CTCMSA)]
2639 "ISA_HAS_MSA"
2640 "ctcmsa\t$%0,%1"
2641 [(set_attr "type" "simd_cmsa")
2642 (set_attr "mode" "SI")])
2643
2644 (define_insn "msa_fexdo_h"
2645 [(set (match_operand:V8HI 0 "register_operand" "=f")
2646 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "f")
2647 (match_operand:V4SF 2 "register_operand" "f")]
2648 UNSPEC_MSA_FEXDO))]
2649 "ISA_HAS_MSA"
2650 "fexdo.h\t%w0,%w1,%w2"
2651 [(set_attr "type" "simd_fcvt")
2652 (set_attr "mode" "V8HI")])
2653
2654 (define_insn "vec_pack_trunc_v2df"
2655 [(set (match_operand:V4SF 0 "register_operand" "=f")
2656 (vec_concat:V4SF
2657 (float_truncate:V2SF (match_operand:V2DF 1 "register_operand" "f"))
2658 (float_truncate:V2SF (match_operand:V2DF 2 "register_operand" "f"))))]
2659 "ISA_HAS_MSA"
2660 "fexdo.w\t%w0,%w2,%w1"
2661 [(set_attr "type" "simd_fcvt")
2662 (set_attr "mode" "V4SF")])
2663
2664 (define_insn "msa_fexupl_w"
2665 [(set (match_operand:V4SF 0 "register_operand" "=f")
2666 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")]
2667 UNSPEC_MSA_FEXUPL))]
2668 "ISA_HAS_MSA"
2669 "fexupl.w\t%w0,%w1"
2670 [(set_attr "type" "simd_fcvt")
2671 (set_attr "mode" "V4SF")])
2672
2673 (define_insn "msa_fexupl_d"
2674 [(set (match_operand:V2DF 0 "register_operand" "=f")
2675 (float_extend:V2DF
2676 (vec_select:V2SF
2677 (match_operand:V4SF 1 "register_operand" "f")
2678 (parallel [(const_int 2) (const_int 3)]))))]
2679 "ISA_HAS_MSA"
2680 "fexupl.d\t%w0,%w1"
2681 [(set_attr "type" "simd_fcvt")
2682 (set_attr "mode" "V2DF")])
2683
2684 (define_insn "msa_fexupr_w"
2685 [(set (match_operand:V4SF 0 "register_operand" "=f")
2686 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "f")]
2687 UNSPEC_MSA_FEXUPR))]
2688 "ISA_HAS_MSA"
2689 "fexupr.w\t%w0,%w1"
2690 [(set_attr "type" "simd_fcvt")
2691 (set_attr "mode" "V4SF")])
2692
2693 (define_insn "msa_fexupr_d"
2694 [(set (match_operand:V2DF 0 "register_operand" "=f")
2695 (float_extend:V2DF
2696 (vec_select:V2SF
2697 (match_operand:V4SF 1 "register_operand" "f")
2698 (parallel [(const_int 0) (const_int 1)]))))]
2699 "ISA_HAS_MSA"
2700 "fexupr.d\t%w0,%w1"
2701 [(set_attr "type" "simd_fcvt")
2702 (set_attr "mode" "V2DF")])
2703
2704 (define_code_attr msabr
2705 [(eq "bz")
2706 (ne "bnz")])
2707
2708 (define_code_attr msabr_neg
2709 [(eq "bnz")
2710 (ne "bz")])
2711
2712 (define_insn "msa_<msabr>_<msafmt_f>"
2713 [(set (pc) (if_then_else
2714 (equality_op
2715 (unspec:SI [(match_operand:MSA 1 "register_operand" "f")]
2716 UNSPEC_MSA_BRANCH)
2717 (match_operand:SI 2 "const_0_operand"))
2718 (label_ref (match_operand 0))
2719 (pc)))]
2720 "ISA_HAS_MSA"
2721 {
2722 return mips_output_conditional_branch (insn, operands,
2723 MIPS_BRANCH ("<msabr>.<msafmt>",
2724 "%w1,%0"),
2725 MIPS_BRANCH ("<msabr_neg>.<msafmt>",
2726 "%w1,%0"));
2727 }
2728 [(set_attr "type" "simd_branch")
2729 (set_attr "mode" "<MODE>")
2730 (set_attr "compact_form" "never")])
2731
2732 (define_insn "msa_<msabr>_v_<msafmt_f>"
2733 [(set (pc) (if_then_else
2734 (equality_op
2735 (unspec:SI [(match_operand:MSA 1 "register_operand" "f")]
2736 UNSPEC_MSA_BRANCH_V)
2737 (match_operand:SI 2 "const_0_operand"))
2738 (label_ref (match_operand 0))
2739 (pc)))]
2740 "ISA_HAS_MSA"
2741 {
2742 return mips_output_conditional_branch (insn, operands,
2743 MIPS_BRANCH ("<msabr>.v", "%w1,%0"),
2744 MIPS_BRANCH ("<msabr_neg>.v",
2745 "%w1,%0"));
2746 }
2747 [(set_attr "type" "simd_branch")
2748 (set_attr "mode" "TI")
2749 (set_attr "compact_form" "never")])