Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/mips/mips-ps-3d.md @ 111:04ced10e8804
gcc 7
author | kono |
---|---|
date | Fri, 27 Oct 2017 22:46:09 +0900 |
parents | f6334be47118 |
children | 84e7813d76e9 |
comparison
equal
deleted
inserted
replaced
68:561a7518be6b | 111:04ced10e8804 |
---|---|
1 ;; MIPS Paired-Single Floating and MIPS-3D Instructions. | 1 ;; MIPS Paired-Single Floating and MIPS-3D Instructions. |
2 ;; Copyright (C) 2004, 2007, 2010 Free Software Foundation, Inc. | 2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc. |
3 ;; | 3 ;; |
4 ;; This file is part of GCC. | 4 ;; This file is part of GCC. |
5 ;; | 5 ;; |
6 ;; GCC is free software; you can redistribute it and/or modify | 6 ;; GCC is free software; you can redistribute it and/or modify |
7 ;; it under the terms of the GNU General Public License as published by | 7 ;; it under the terms of the GNU General Public License as published by |
87 | 87 |
88 mips_expand_conditional_move (operands); | 88 mips_expand_conditional_move (operands); |
89 DONE; | 89 DONE; |
90 }) | 90 }) |
91 | 91 |
92 ; pul.ps - Pair Upper Lower | 92 (define_insn "vec_perm_const_ps" |
93 (define_insn "mips_pul_ps" | |
94 [(set (match_operand:V2SF 0 "register_operand" "=f") | 93 [(set (match_operand:V2SF 0 "register_operand" "=f") |
95 (vec_merge:V2SF | 94 (vec_select:V2SF |
96 (match_operand:V2SF 1 "register_operand" "f") | 95 (vec_concat:V4SF |
97 (match_operand:V2SF 2 "register_operand" "f") | 96 (match_operand:V2SF 1 "register_operand" "f") |
98 (const_int 2)))] | 97 (match_operand:V2SF 2 "register_operand" "f")) |
99 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 98 (parallel [(match_operand:SI 3 "const_0_or_1_operand" "") |
100 "pul.ps\t%0,%1,%2" | 99 (match_operand:SI 4 "const_2_or_3_operand" "")])))] |
100 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | |
101 { | |
102 /* Let <op>L be the lower part of operand <op> and <op>U be the upper part. | |
103 The P[UL][UL].PS instruction always specifies the upper part of the | |
104 result first, so the instruction is: | |
105 | |
106 P<aUL><bUL>.PS %0,<aop>,<bop> | |
107 | |
108 where 0U == <aop><aUL> and 0L == <bop><bUL>. | |
109 | |
110 GCC's vector indices are specified in memory order, which means | |
111 that vector element 0 is the lower part (L) on little-endian targets | |
112 and the upper part (U) on big-endian targets. vec_concat likewise | |
113 concatenates in memory order, which means that operand 3 (being | |
114 0 or 1) selects part of operand 1 and operand 4 (being 2 or 3) | |
115 selects part of operand 2. | |
116 | |
117 Let: | |
118 | |
119 I3 = INTVAL (operands[3]) | |
120 I4 = INTVAL (operands[4]) - 2 | |
121 | |
122 Taking the two endiannesses in turn: | |
123 | |
124 Little-endian: | |
125 | |
126 The semantics of the RTL pattern are: | |
127 | |
128 { 0L, 0U } = { X[I3], X[I4 + 2] }, where X = { 1L, 1U, 2L, 2U } | |
129 | |
130 so: 0L = { 1L, 1U }[I3] (= <bop><bUL>) | |
131 0U = { 2L, 2U }[I4] (= <aop><aUL>) | |
132 | |
133 <aop> = 2, <aUL> = I4 ? U : L | |
134 <bop> = 1, <bUL> = I3 ? U : L | |
135 | |
136 [LL] !I4 && !I3 [UL] I4 && !I3 | |
137 [LU] !I4 && I3 [UU] I4 && I3 | |
138 | |
139 Big-endian: | |
140 | |
141 The semantics of the RTL pattern are: | |
142 | |
143 { 0U, 0L } = { X[I3], X[I4 + 2] }, where X = { 1U, 1L, 2U, 2L } | |
144 | |
145 so: 0U = { 1U, 1L }[I3] (= <aop><aUL>) | |
146 0L = { 2U, 2L }[I4] (= <bop><bUL>) | |
147 | |
148 <aop> = 1, <aUL> = I3 ? L : U | |
149 <bop> = 2, <bUL> = I4 ? L : U | |
150 | |
151 [UU] !I3 && !I4 [UL] !I3 && I4 | |
152 [LU] I3 && !I4 [LL] I3 && I4. */ | |
153 | |
154 static const char * const mnemonics[2][4] = { | |
155 /* LE */ { "pll.ps\t%0,%2,%1", "pul.ps\t%0,%2,%1", | |
156 "plu.ps\t%0,%2,%1", "puu.ps\t%0,%2,%1" }, | |
157 /* BE */ { "puu.ps\t%0,%1,%2", "pul.ps\t%0,%1,%2", | |
158 "plu.ps\t%0,%1,%2", "pll.ps\t%0,%1,%2" }, | |
159 }; | |
160 | |
161 unsigned mask = INTVAL (operands[3]) * 2 + (INTVAL (operands[4]) - 2); | |
162 return mnemonics[BYTES_BIG_ENDIAN][mask]; | |
163 } | |
101 [(set_attr "type" "fmove") | 164 [(set_attr "type" "fmove") |
102 (set_attr "mode" "SF")]) | 165 (set_attr "mode" "SF")]) |
103 | 166 |
104 ; puu.ps - Pair upper upper | 167 (define_expand "vec_perm_constv2sf" |
105 (define_insn "mips_puu_ps" | 168 [(match_operand:V2SF 0 "register_operand" "") |
106 [(set (match_operand:V2SF 0 "register_operand" "=f") | 169 (match_operand:V2SF 1 "register_operand" "") |
107 (vec_merge:V2SF | 170 (match_operand:V2SF 2 "register_operand" "") |
108 (match_operand:V2SF 1 "register_operand" "f") | 171 (match_operand:V2SI 3 "" "")] |
109 (vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f") | 172 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" |
110 (parallel [(const_int 1) | 173 { |
111 (const_int 0)])) | 174 if (mips_expand_vec_perm_const (operands)) |
112 (const_int 2)))] | 175 DONE; |
113 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 176 else |
114 "puu.ps\t%0,%1,%2" | 177 FAIL; |
115 [(set_attr "type" "fmove") | 178 }) |
116 (set_attr "mode" "SF")]) | 179 |
117 | 180 ;; Expanders for builtins. The instruction: |
118 ; pll.ps - Pair Lower Lower | 181 ;; |
119 (define_insn "mips_pll_ps" | 182 ;; P[UL][UL].PS <result>, <a>, <b> |
120 [(set (match_operand:V2SF 0 "register_operand" "=f") | 183 ;; |
121 (vec_merge:V2SF | 184 ;; says that the upper part of <result> is taken from half of <a> and |
122 (vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f") | 185 ;; the lower part of <result> is taken from half of <b>. This means |
123 (parallel [(const_int 1) | 186 ;; that the P[UL][UL].PS operand order matches memory order on big-endian |
124 (const_int 0)])) | 187 ;; targets; <a> is element 0 of the V2SF result while <b> is element 1. |
125 (match_operand:V2SF 2 "register_operand" "f") | 188 ;; However, the P[UL][UL].PS operand order is the reverse of memory order |
126 (const_int 2)))] | 189 ;; on little-endian targets; <a> is element 1 of the V2SF result while |
127 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 190 ;; <b> is element 0. The arguments to vec_perm_const_ps are always in |
128 "pll.ps\t%0,%1,%2" | 191 ;; memory order. |
129 [(set_attr "type" "fmove") | 192 ;; |
130 (set_attr "mode" "SF")]) | 193 ;; Similarly, "U" corresponds to element 0 on big-endian targets but |
131 | 194 ;; to element 1 on little-endian targets. |
132 ; plu.ps - Pair Lower Upper | 195 |
133 (define_insn "mips_plu_ps" | 196 (define_expand "mips_puu_ps" |
134 [(set (match_operand:V2SF 0 "register_operand" "=f") | 197 [(match_operand:V2SF 0 "register_operand" "") |
135 (vec_merge:V2SF | 198 (match_operand:V2SF 1 "register_operand" "") |
136 (vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f") | 199 (match_operand:V2SF 2 "register_operand" "")] |
137 (parallel [(const_int 1) | 200 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" |
138 (const_int 0)])) | 201 { |
139 (vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f") | 202 if (BYTES_BIG_ENDIAN) |
140 (parallel [(const_int 1) | 203 emit_insn (gen_vec_perm_const_ps (operands[0], operands[1], operands[2], |
141 (const_int 0)])) | 204 const0_rtx, const2_rtx)); |
142 (const_int 2)))] | 205 else |
143 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 206 emit_insn (gen_vec_perm_const_ps (operands[0], operands[2], operands[1], |
144 "plu.ps\t%0,%1,%2" | 207 const1_rtx, GEN_INT (3))); |
145 [(set_attr "type" "fmove") | 208 DONE; |
146 (set_attr "mode" "SF")]) | 209 }) |
210 | |
211 (define_expand "mips_pul_ps" | |
212 [(match_operand:V2SF 0 "register_operand" "") | |
213 (match_operand:V2SF 1 "register_operand" "") | |
214 (match_operand:V2SF 2 "register_operand" "")] | |
215 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | |
216 { | |
217 if (BYTES_BIG_ENDIAN) | |
218 emit_insn (gen_vec_perm_const_ps (operands[0], operands[1], operands[2], | |
219 const0_rtx, GEN_INT (3))); | |
220 else | |
221 emit_insn (gen_vec_perm_const_ps (operands[0], operands[2], operands[1], | |
222 const0_rtx, GEN_INT (3))); | |
223 DONE; | |
224 }) | |
225 | |
226 (define_expand "mips_plu_ps" | |
227 [(match_operand:V2SF 0 "register_operand" "") | |
228 (match_operand:V2SF 1 "register_operand" "") | |
229 (match_operand:V2SF 2 "register_operand" "")] | |
230 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | |
231 { | |
232 if (BYTES_BIG_ENDIAN) | |
233 emit_insn (gen_vec_perm_const_ps (operands[0], operands[1], operands[2], | |
234 const1_rtx, const2_rtx)); | |
235 else | |
236 emit_insn (gen_vec_perm_const_ps (operands[0], operands[2], operands[1], | |
237 const1_rtx, const2_rtx)); | |
238 DONE; | |
239 }) | |
240 | |
241 (define_expand "mips_pll_ps" | |
242 [(match_operand:V2SF 0 "register_operand" "") | |
243 (match_operand:V2SF 1 "register_operand" "") | |
244 (match_operand:V2SF 2 "register_operand" "")] | |
245 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | |
246 { | |
247 if (BYTES_BIG_ENDIAN) | |
248 emit_insn (gen_vec_perm_const_ps (operands[0], operands[1], operands[2], | |
249 const1_rtx, GEN_INT (3))); | |
250 else | |
251 emit_insn (gen_vec_perm_const_ps (operands[0], operands[2], operands[1], | |
252 const0_rtx, const2_rtx)); | |
253 DONE; | |
254 }) | |
147 | 255 |
148 ; vec_init | 256 ; vec_init |
149 (define_expand "vec_initv2sf" | 257 (define_expand "vec_initv2sfsf" |
150 [(match_operand:V2SF 0 "register_operand") | 258 [(match_operand:V2SF 0 "register_operand") |
151 (match_operand:V2SF 1 "")] | 259 (match_operand:V2SF 1 "")] |
152 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 260 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" |
153 { | 261 { |
154 rtx op0 = force_reg (SFmode, XVECEXP (operands[1], 0, 0)); | 262 mips_expand_vector_init (operands[0], operands[1]); |
155 rtx op1 = force_reg (SFmode, XVECEXP (operands[1], 0, 1)); | 263 DONE; |
156 emit_insn (gen_vec_initv2sf_internal (operands[0], op0, op1)); | 264 }) |
157 DONE; | 265 |
158 }) | 266 (define_insn "vec_concatv2sf" |
159 | |
160 (define_insn "vec_initv2sf_internal" | |
161 [(set (match_operand:V2SF 0 "register_operand" "=f") | 267 [(set (match_operand:V2SF 0 "register_operand" "=f") |
162 (vec_concat:V2SF | 268 (vec_concat:V2SF |
163 (match_operand:SF 1 "register_operand" "f") | 269 (match_operand:SF 1 "register_operand" "f") |
164 (match_operand:SF 2 "register_operand" "f")))] | 270 (match_operand:SF 2 "register_operand" "f")))] |
165 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 271 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" |
174 | 280 |
175 ;; ??? This is only generated if we perform a vector operation that has to be | 281 ;; ??? This is only generated if we perform a vector operation that has to be |
176 ;; emulated. There is no other way to get a vector mode bitfield extract | 282 ;; emulated. There is no other way to get a vector mode bitfield extract |
177 ;; currently. | 283 ;; currently. |
178 | 284 |
179 (define_insn "vec_extractv2sf" | 285 (define_insn "vec_extractv2sfsf" |
180 [(set (match_operand:SF 0 "register_operand" "=f") | 286 [(set (match_operand:SF 0 "register_operand" "=f") |
181 (vec_select:SF (match_operand:V2SF 1 "register_operand" "f") | 287 (vec_select:SF (match_operand:V2SF 1 "register_operand" "f") |
182 (parallel | 288 (parallel |
183 [(match_operand 2 "const_0_or_1_operand" "")])))] | 289 [(match_operand 2 "const_0_or_1_operand" "")])))] |
184 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 290 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" |
193 | 299 |
194 ;; ??? This is only generated if we disable the vec_init pattern. There is | 300 ;; ??? This is only generated if we disable the vec_init pattern. There is |
195 ;; no other way to get a vector mode bitfield store currently. | 301 ;; no other way to get a vector mode bitfield store currently. |
196 | 302 |
197 (define_expand "vec_setv2sf" | 303 (define_expand "vec_setv2sf" |
198 [(match_operand:V2SF 0 "register_operand") | 304 [(set (match_operand:V2SF 0 "register_operand" "") |
199 (match_operand:SF 1 "register_operand") | 305 (vec_select:V2SF |
200 (match_operand 2 "const_0_or_1_operand")] | 306 (vec_concat:V4SF |
201 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 307 (match_operand:SF 1 "register_operand" "") |
202 { | 308 (match_dup 0)) |
203 rtx temp; | 309 (parallel [(match_operand 2 "const_0_or_1_operand" "") |
204 | 310 (match_dup 3)])))] |
311 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | |
312 { | |
205 /* We don't have an insert instruction, so we duplicate the float, and | 313 /* We don't have an insert instruction, so we duplicate the float, and |
206 then use a PUL instruction. */ | 314 then use a PUL instruction. */ |
207 temp = gen_reg_rtx (V2SFmode); | 315 rtx temp = gen_reg_rtx (V2SFmode); |
208 emit_insn (gen_mips_cvt_ps_s (temp, operands[1], operands[1])); | 316 emit_insn (gen_vec_concatv2sf (temp, operands[1], operands[1])); |
209 if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN) | 317 operands[1] = temp; |
210 emit_insn (gen_mips_pul_ps (operands[0], temp, operands[0])); | 318 operands[3] = GEN_INT (1 - INTVAL (operands[2]) + 2); |
211 else | |
212 emit_insn (gen_mips_pul_ps (operands[0], operands[0], temp)); | |
213 DONE; | |
214 }) | 319 }) |
215 | 320 |
216 ; cvt.ps.s - Floating Point Convert Pair to Paired Single | 321 ; cvt.ps.s - Floating Point Convert Pair to Paired Single |
217 (define_expand "mips_cvt_ps_s" | 322 (define_expand "mips_cvt_ps_s" |
218 [(match_operand:V2SF 0 "register_operand") | 323 [(match_operand:V2SF 0 "register_operand") |
219 (match_operand:SF 1 "register_operand") | 324 (match_operand:SF 1 "register_operand") |
220 (match_operand:SF 2 "register_operand")] | 325 (match_operand:SF 2 "register_operand")] |
221 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 326 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" |
222 { | 327 { |
223 if (BYTES_BIG_ENDIAN) | 328 if (BYTES_BIG_ENDIAN) |
224 emit_insn (gen_vec_initv2sf_internal (operands[0], operands[1], | 329 emit_insn (gen_vec_concatv2sf (operands[0], operands[1], operands[2])); |
225 operands[2])); | |
226 else | 330 else |
227 emit_insn (gen_vec_initv2sf_internal (operands[0], operands[2], | 331 emit_insn (gen_vec_concatv2sf (operands[0], operands[2], operands[1])); |
228 operands[1])); | |
229 DONE; | 332 DONE; |
230 }) | 333 }) |
231 | 334 |
232 ; cvt.s.pl - Floating Point Convert Pair Lower to Single Floating Point | 335 ; cvt.s.pl - Floating Point Convert Pair Lower to Single Floating Point |
233 (define_expand "mips_cvt_s_pl" | 336 (define_expand "mips_cvt_s_pl" |
261 (define_insn "mips_addr_ps" | 364 (define_insn "mips_addr_ps" |
262 [(set (match_operand:V2SF 0 "register_operand" "=f") | 365 [(set (match_operand:V2SF 0 "register_operand" "=f") |
263 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") | 366 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") |
264 (match_operand:V2SF 2 "register_operand" "f")] | 367 (match_operand:V2SF 2 "register_operand" "f")] |
265 UNSPEC_ADDR_PS))] | 368 UNSPEC_ADDR_PS))] |
266 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 369 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
267 "addr.ps\t%0,%1,%2" | 370 "addr.ps\t%0,%1,%2" |
268 [(set_attr "type" "fadd") | 371 [(set_attr "type" "fadd") |
269 (set_attr "mode" "SF")]) | 372 (set_attr "mode" "SF")]) |
373 | |
374 (define_expand "reduc_plus_scal_v2sf" | |
375 [(match_operand:SF 0 "register_operand" "=f") | |
376 (match_operand:V2SF 1 "register_operand" "f")] | |
377 "TARGET_HARD_FLOAT && TARGET_MIPS3D" | |
378 { | |
379 rtx temp = gen_reg_rtx (V2SFmode); | |
380 emit_insn (gen_mips_addr_ps (temp, operands[1], operands[1])); | |
381 rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; | |
382 emit_insn (gen_vec_extractv2sfsf (operands[0], temp, lane)); | |
383 DONE; | |
384 }) | |
270 | 385 |
271 ; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word | 386 ; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word |
272 (define_insn "mips_cvt_pw_ps" | 387 (define_insn "mips_cvt_pw_ps" |
273 [(set (match_operand:V2SF 0 "register_operand" "=f") | 388 [(set (match_operand:V2SF 0 "register_operand" "=f") |
274 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] | 389 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] |
275 UNSPEC_CVT_PW_PS))] | 390 UNSPEC_CVT_PW_PS))] |
276 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 391 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
277 "cvt.pw.ps\t%0,%1" | 392 "cvt.pw.ps\t%0,%1" |
278 [(set_attr "type" "fcvt") | 393 [(set_attr "type" "fcvt") |
279 (set_attr "mode" "SF")]) | 394 (set_attr "mode" "SF")]) |
280 | 395 |
281 ; cvt.ps.pw - Floating Point Convert Paired Word to Paired Single | 396 ; cvt.ps.pw - Floating Point Convert Paired Word to Paired Single |
282 (define_insn "mips_cvt_ps_pw" | 397 (define_insn "mips_cvt_ps_pw" |
283 [(set (match_operand:V2SF 0 "register_operand" "=f") | 398 [(set (match_operand:V2SF 0 "register_operand" "=f") |
284 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] | 399 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] |
285 UNSPEC_CVT_PS_PW))] | 400 UNSPEC_CVT_PS_PW))] |
286 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 401 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
287 "cvt.ps.pw\t%0,%1" | 402 "cvt.ps.pw\t%0,%1" |
288 [(set_attr "type" "fcvt") | 403 [(set_attr "type" "fcvt") |
289 (set_attr "mode" "SF")]) | 404 (set_attr "mode" "SF")]) |
290 | 405 |
291 ; mulr.ps - Floating Point Reduction Multiply | 406 ; mulr.ps - Floating Point Reduction Multiply |
292 (define_insn "mips_mulr_ps" | 407 (define_insn "mips_mulr_ps" |
293 [(set (match_operand:V2SF 0 "register_operand" "=f") | 408 [(set (match_operand:V2SF 0 "register_operand" "=f") |
294 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") | 409 (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") |
295 (match_operand:V2SF 2 "register_operand" "f")] | 410 (match_operand:V2SF 2 "register_operand" "f")] |
296 UNSPEC_MULR_PS))] | 411 UNSPEC_MULR_PS))] |
297 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 412 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
298 "mulr.ps\t%0,%1,%2" | 413 "mulr.ps\t%0,%1,%2" |
299 [(set_attr "type" "fmul") | 414 [(set_attr "type" "fmul") |
300 (set_attr "mode" "SF")]) | 415 (set_attr "mode" "SF")]) |
301 | 416 |
302 ; abs.ps | 417 ; abs.ps |
332 [(set (match_operand:CC 0 "register_operand" "=z") | 447 [(set (match_operand:CC 0 "register_operand" "=z") |
333 (unspec:CC [(match_operand:SCALARF 1 "register_operand" "f") | 448 (unspec:CC [(match_operand:SCALARF 1 "register_operand" "f") |
334 (match_operand:SCALARF 2 "register_operand" "f") | 449 (match_operand:SCALARF 2 "register_operand" "f") |
335 (match_operand 3 "const_int_operand" "")] | 450 (match_operand 3 "const_int_operand" "")] |
336 UNSPEC_CABS))] | 451 UNSPEC_CABS))] |
337 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 452 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
338 "cabs.%Y3.<fmt>\t%0,%1,%2" | 453 "cabs.%Y3.<fmt>\t%0,%1,%2" |
339 [(set_attr "type" "fcmp") | 454 [(set_attr "type" "fcmp") |
340 (set_attr "mode" "FPSW")]) | 455 (set_attr "mode" "FPSW")]) |
341 | 456 |
342 | 457 |
368 { | 483 { |
369 operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0); | 484 operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0); |
370 operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8); | 485 operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8); |
371 } | 486 } |
372 [(set_attr "type" "fcmp") | 487 [(set_attr "type" "fcmp") |
373 (set_attr "length" "8") | 488 (set_attr "insn_count" "2") |
374 (set_attr "mode" "FPSW")]) | 489 (set_attr "mode" "FPSW")]) |
375 | 490 |
376 (define_insn_and_split "mips_cabs_cond_4s" | 491 (define_insn_and_split "mips_cabs_cond_4s" |
377 [(set (match_operand:CCV4 0 "register_operand" "=z") | 492 [(set (match_operand:CCV4 0 "register_operand" "=z") |
378 (unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f") | 493 (unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f") |
379 (match_operand:V2SF 2 "register_operand" "f") | 494 (match_operand:V2SF 2 "register_operand" "f") |
380 (match_operand:V2SF 3 "register_operand" "f") | 495 (match_operand:V2SF 3 "register_operand" "f") |
381 (match_operand:V2SF 4 "register_operand" "f") | 496 (match_operand:V2SF 4 "register_operand" "f") |
382 (match_operand 5 "const_int_operand" "")] | 497 (match_operand 5 "const_int_operand" "")] |
383 UNSPEC_CABS))] | 498 UNSPEC_CABS))] |
384 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 499 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
385 "#" | 500 "#" |
386 "&& reload_completed" | 501 "&& reload_completed" |
387 [(set (match_dup 6) | 502 [(set (match_dup 6) |
388 (unspec:CCV2 [(match_dup 1) | 503 (unspec:CCV2 [(match_dup 1) |
389 (match_dup 2) | 504 (match_dup 2) |
397 { | 512 { |
398 operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0); | 513 operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0); |
399 operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8); | 514 operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8); |
400 } | 515 } |
401 [(set_attr "type" "fcmp") | 516 [(set_attr "type" "fcmp") |
402 (set_attr "length" "8") | 517 (set_attr "insn_count" "2") |
403 (set_attr "mode" "FPSW")]) | 518 (set_attr "mode" "FPSW")]) |
404 | 519 |
405 | 520 |
406 ;---------------------------------------------------------------------------- | 521 ;---------------------------------------------------------------------------- |
407 ; Floating Point Comparisons for Paired Singles | 522 ; Floating Point Comparisons for Paired Singles |
422 [(set (match_operand:CCV2 0 "register_operand" "=z") | 537 [(set (match_operand:CCV2 0 "register_operand" "=z") |
423 (unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f") | 538 (unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f") |
424 (match_operand:V2SF 2 "register_operand" "f") | 539 (match_operand:V2SF 2 "register_operand" "f") |
425 (match_operand 3 "const_int_operand" "")] | 540 (match_operand 3 "const_int_operand" "")] |
426 UNSPEC_CABS))] | 541 UNSPEC_CABS))] |
427 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 542 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
428 "cabs.%Y3.ps\t%0,%1,%2" | 543 "cabs.%Y3.ps\t%0,%1,%2" |
429 [(set_attr "type" "fcmp") | 544 [(set_attr "type" "fcmp") |
430 (set_attr "mode" "FPSW")]) | 545 (set_attr "mode" "FPSW")]) |
431 | 546 |
432 ;; An expander for generating an scc operation. | 547 ;; An expander for generating an scc operation. |
465 [(set (pc) | 580 [(set (pc) |
466 (if_then_else (ne (match_operand:CCV4 1 "register_operand" "z") | 581 (if_then_else (ne (match_operand:CCV4 1 "register_operand" "z") |
467 (const_int 0)) | 582 (const_int 0)) |
468 (label_ref (match_operand 0 "" "")) | 583 (label_ref (match_operand 0 "" "")) |
469 (pc)))] | 584 (pc)))] |
470 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 585 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
471 "%*bc1any4t\t%1,%0%/" | 586 "%*bc1any4t\t%1,%0%/" |
472 [(set_attr "type" "branch")]) | 587 [(set_attr "type" "branch")]) |
473 | 588 |
474 ; Branch on Any of Four Floating Point Condition Codes False | 589 ; Branch on Any of Four Floating Point Condition Codes False |
475 (define_insn "bc1any4f" | 590 (define_insn "bc1any4f" |
476 [(set (pc) | 591 [(set (pc) |
477 (if_then_else (ne (match_operand:CCV4 1 "register_operand" "z") | 592 (if_then_else (ne (match_operand:CCV4 1 "register_operand" "z") |
478 (const_int -1)) | 593 (const_int -1)) |
479 (label_ref (match_operand 0 "" "")) | 594 (label_ref (match_operand 0 "" "")) |
480 (pc)))] | 595 (pc)))] |
481 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 596 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
482 "%*bc1any4f\t%1,%0%/" | 597 "%*bc1any4f\t%1,%0%/" |
483 [(set_attr "type" "branch")]) | 598 [(set_attr "type" "branch")]) |
484 | 599 |
485 ; Branch on Any of Two Floating Point Condition Codes True | 600 ; Branch on Any of Two Floating Point Condition Codes True |
486 (define_insn "bc1any2t" | 601 (define_insn "bc1any2t" |
487 [(set (pc) | 602 [(set (pc) |
488 (if_then_else (ne (match_operand:CCV2 1 "register_operand" "z") | 603 (if_then_else (ne (match_operand:CCV2 1 "register_operand" "z") |
489 (const_int 0)) | 604 (const_int 0)) |
490 (label_ref (match_operand 0 "" "")) | 605 (label_ref (match_operand 0 "" "")) |
491 (pc)))] | 606 (pc)))] |
492 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 607 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
493 "%*bc1any2t\t%1,%0%/" | 608 "%*bc1any2t\t%1,%0%/" |
494 [(set_attr "type" "branch")]) | 609 [(set_attr "type" "branch")]) |
495 | 610 |
496 ; Branch on Any of Two Floating Point Condition Codes False | 611 ; Branch on Any of Two Floating Point Condition Codes False |
497 (define_insn "bc1any2f" | 612 (define_insn "bc1any2f" |
498 [(set (pc) | 613 [(set (pc) |
499 (if_then_else (ne (match_operand:CCV2 1 "register_operand" "z") | 614 (if_then_else (ne (match_operand:CCV2 1 "register_operand" "z") |
500 (const_int -1)) | 615 (const_int -1)) |
501 (label_ref (match_operand 0 "" "")) | 616 (label_ref (match_operand 0 "" "")) |
502 (pc)))] | 617 (pc)))] |
503 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 618 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
504 "%*bc1any2f\t%1,%0%/" | 619 "%*bc1any2f\t%1,%0%/" |
505 [(set_attr "type" "branch")]) | 620 [(set_attr "type" "branch")]) |
506 | 621 |
507 ; Used to access one register in a CCV2 pair. Operand 0 is the register | 622 ; Used to access one register in a CCV2 pair. Operand 0 is the register |
508 ; pair and operand 1 is the index of the register we want (a CONST_INT). | 623 ; pair and operand 1 is the index of the register we want (a CONST_INT). |
561 | 676 |
562 (define_insn "mips_rsqrt1_<fmt>" | 677 (define_insn "mips_rsqrt1_<fmt>" |
563 [(set (match_operand:ANYF 0 "register_operand" "=f") | 678 [(set (match_operand:ANYF 0 "register_operand" "=f") |
564 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] | 679 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] |
565 UNSPEC_RSQRT1))] | 680 UNSPEC_RSQRT1))] |
566 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 681 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
567 "rsqrt1.<fmt>\t%0,%1" | 682 "rsqrt1.<fmt>\t%0,%1" |
568 [(set_attr "type" "frsqrt1") | 683 [(set_attr "type" "frsqrt1") |
569 (set_attr "mode" "<UNITMODE>")]) | 684 (set_attr "mode" "<UNITMODE>")]) |
570 | 685 |
571 (define_insn "mips_rsqrt2_<fmt>" | 686 (define_insn "mips_rsqrt2_<fmt>" |
572 [(set (match_operand:ANYF 0 "register_operand" "=f") | 687 [(set (match_operand:ANYF 0 "register_operand" "=f") |
573 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f") | 688 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f") |
574 (match_operand:ANYF 2 "register_operand" "f")] | 689 (match_operand:ANYF 2 "register_operand" "f")] |
575 UNSPEC_RSQRT2))] | 690 UNSPEC_RSQRT2))] |
576 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 691 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
577 "rsqrt2.<fmt>\t%0,%1,%2" | 692 "rsqrt2.<fmt>\t%0,%1,%2" |
578 [(set_attr "type" "frsqrt2") | 693 [(set_attr "type" "frsqrt2") |
579 (set_attr "mode" "<UNITMODE>")]) | 694 (set_attr "mode" "<UNITMODE>")]) |
580 | 695 |
581 (define_insn "mips_recip1_<fmt>" | 696 (define_insn "mips_recip1_<fmt>" |
582 [(set (match_operand:ANYF 0 "register_operand" "=f") | 697 [(set (match_operand:ANYF 0 "register_operand" "=f") |
583 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] | 698 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] |
584 UNSPEC_RECIP1))] | 699 UNSPEC_RECIP1))] |
585 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 700 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
586 "recip1.<fmt>\t%0,%1" | 701 "recip1.<fmt>\t%0,%1" |
587 [(set_attr "type" "frdiv1") | 702 [(set_attr "type" "frdiv1") |
588 (set_attr "mode" "<UNITMODE>")]) | 703 (set_attr "mode" "<UNITMODE>")]) |
589 | 704 |
590 (define_insn "mips_recip2_<fmt>" | 705 (define_insn "mips_recip2_<fmt>" |
591 [(set (match_operand:ANYF 0 "register_operand" "=f") | 706 [(set (match_operand:ANYF 0 "register_operand" "=f") |
592 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f") | 707 (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f") |
593 (match_operand:ANYF 2 "register_operand" "f")] | 708 (match_operand:ANYF 2 "register_operand" "f")] |
594 UNSPEC_RECIP2))] | 709 UNSPEC_RECIP2))] |
595 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | 710 "TARGET_HARD_FLOAT && TARGET_MIPS3D" |
596 "recip2.<fmt>\t%0,%1,%2" | 711 "recip2.<fmt>\t%0,%1,%2" |
597 [(set_attr "type" "frdiv2") | 712 [(set_attr "type" "frdiv2") |
598 (set_attr "mode" "<UNITMODE>")]) | 713 (set_attr "mode" "<UNITMODE>")]) |
599 | 714 |
600 (define_expand "vcondv2sf" | 715 (define_expand "vcondv2sfv2sf" |
601 [(set (match_operand:V2SF 0 "register_operand") | 716 [(set (match_operand:V2SF 0 "register_operand") |
602 (if_then_else:V2SF | 717 (if_then_else:V2SF |
603 (match_operator 3 "" | 718 (match_operator 3 "" |
604 [(match_operand:V2SF 4 "register_operand") | 719 [(match_operand:V2SF 4 "register_operand") |
605 (match_operand:V2SF 5 "register_operand")]) | 720 (match_operand:V2SF 5 "register_operand")]) |
631 { | 746 { |
632 mips_expand_vcondv2sf (operands[0], operands[1], operands[2], | 747 mips_expand_vcondv2sf (operands[0], operands[1], operands[2], |
633 LE, operands[2], operands[1]); | 748 LE, operands[2], operands[1]); |
634 DONE; | 749 DONE; |
635 }) | 750 }) |
751 | |
752 (define_expand "reduc_smin_scal_v2sf" | |
753 [(match_operand:SF 0 "register_operand") | |
754 (match_operand:V2SF 1 "register_operand")] | |
755 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | |
756 { | |
757 rtx temp = gen_reg_rtx (V2SFmode); | |
758 mips_expand_vec_reduc (temp, operands[1], gen_sminv2sf3); | |
759 rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; | |
760 emit_insn (gen_vec_extractv2sfsf (operands[0], temp, lane)); | |
761 DONE; | |
762 }) | |
763 | |
764 (define_expand "reduc_smax_scal_v2sf" | |
765 [(match_operand:SF 0 "register_operand") | |
766 (match_operand:V2SF 1 "register_operand")] | |
767 "TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT" | |
768 { | |
769 rtx temp = gen_reg_rtx (V2SFmode); | |
770 mips_expand_vec_reduc (temp, operands[1], gen_smaxv2sf3); | |
771 rtx lane = BYTES_BIG_ENDIAN ? const1_rtx : const0_rtx; | |
772 emit_insn (gen_vec_extractv2sfsf (operands[0], temp, lane)); | |
773 DONE; | |
774 }) |