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comparison gcc/config/mips/sb1.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 77e2b8dfacca
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Copyright (C) 2004, 2005, 2006, 2007 Free Software Foundation, Inc. 1 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc.
2 ;; 2 ;;
3 ;; This file is part of GCC. 3 ;; This file is part of GCC.
4 ;; 4 ;;
5 ;; GCC is free software; you can redistribute it and/or modify 5 ;; GCC is free software; you can redistribute it and/or modify
6 ;; it under the terms of the GNU General Public License as published by 6 ;; it under the terms of the GNU General Public License as published by
74 ;; Define an SB-1 specific attribute to simplify some FP descriptions. 74 ;; Define an SB-1 specific attribute to simplify some FP descriptions.
75 ;; We can use 2 FP pipes only if we have 64-bit FP code, and exceptions are 75 ;; We can use 2 FP pipes only if we have 64-bit FP code, and exceptions are
76 ;; disabled. 76 ;; disabled.
77 77
78 (define_attr "sb1_fp_pipes" "one,two" 78 (define_attr "sb1_fp_pipes" "one,two"
79 (cond [(and (ne (symbol_ref "TARGET_FLOAT64") (const_int 0)) 79 (cond [(and (match_test "TARGET_FLOAT64")
80 (eq (symbol_ref "TARGET_FP_EXCEPTIONS") (const_int 0))) 80 (not (match_test "TARGET_FP_EXCEPTIONS")))
81 (const_string "two")] 81 (const_string "two")]
82 (const_string "one"))) 82 (const_string "one")))
83 83
84 ;; Define reservations for common combinations. 84 ;; Define reservations for common combinations.
85 85
106 ;; reservation used! 106 ;; reservation used!
107 ;; 107 ;;
108 108
109 (define_insn_reservation "ir_sb1_unknown" 1 109 (define_insn_reservation "ir_sb1_unknown" 1
110 (and (eq_attr "cpu" "sb1,sb1a") 110 (and (eq_attr "cpu" "sb1,sb1a")
111 (eq_attr "type" "unknown,multi")) 111 (eq_attr "type" "unknown,multi,atomic,syncloop"))
112 "sb1_ls0+sb1_ls1+sb1_ex0+sb1_ex1+sb1_fp0+sb1_fp1") 112 "sb1_ls0+sb1_ls1+sb1_ex0+sb1_ex1+sb1_fp0+sb1_fp1")
113 113
114 ;; predicted taken branch causes 2 cycle ifetch bubble. predicted not 114 ;; predicted taken branch causes 2 cycle ifetch bubble. predicted not
115 ;; taken branch causes 0 cycle ifetch bubble. mispredicted branch causes 8 115 ;; taken branch causes 0 cycle ifetch bubble. mispredicted branch causes 8
116 ;; cycle ifetch bubble. We assume all branches predicted not taken. 116 ;; cycle ifetch bubble. We assume all branches predicted not taken.
147 ;; Can not co-issue fpload with fp exe when in 32-bit mode. 147 ;; Can not co-issue fpload with fp exe when in 32-bit mode.
148 148
149 (define_insn_reservation "ir_sb1_fpload" 0 149 (define_insn_reservation "ir_sb1_fpload" 0
150 (and (eq_attr "cpu" "sb1,sb1a") 150 (and (eq_attr "cpu" "sb1,sb1a")
151 (and (eq_attr "type" "fpload") 151 (and (eq_attr "type" "fpload")
152 (ne (symbol_ref "TARGET_FLOAT64") 152 (match_test "TARGET_FLOAT64")))
153 (const_int 0))))
154 "sb1_ls0 | sb1_ls1") 153 "sb1_ls0 | sb1_ls1")
155 154
156 (define_insn_reservation "ir_sb1_fpload_32bitfp" 1 155 (define_insn_reservation "ir_sb1_fpload_32bitfp" 1
157 (and (eq_attr "cpu" "sb1,sb1a") 156 (and (eq_attr "cpu" "sb1,sb1a")
158 (and (eq_attr "type" "fpload") 157 (and (eq_attr "type" "fpload")
159 (eq (symbol_ref "TARGET_FLOAT64") 158 (not (match_test "TARGET_FLOAT64"))))
160 (const_int 0))))
161 "sb1_ls0 | sb1_ls1") 159 "sb1_ls0 | sb1_ls1")
162 160
163 ;; Indexed loads can only execute on LS1 pipe. 161 ;; Indexed loads can only execute on LS1 pipe.
164 162
165 (define_insn_reservation "ir_sb1_fpidxload" 0 163 (define_insn_reservation "ir_sb1_fpidxload" 0
166 (and (eq_attr "cpu" "sb1,sb1a") 164 (and (eq_attr "cpu" "sb1,sb1a")
167 (and (eq_attr "type" "fpidxload") 165 (and (eq_attr "type" "fpidxload")
168 (ne (symbol_ref "TARGET_FLOAT64") 166 (match_test "TARGET_FLOAT64")))
169 (const_int 0))))
170 "sb1_ls1") 167 "sb1_ls1")
171 168
172 (define_insn_reservation "ir_sb1_fpidxload_32bitfp" 1 169 (define_insn_reservation "ir_sb1_fpidxload_32bitfp" 1
173 (and (eq_attr "cpu" "sb1,sb1a") 170 (and (eq_attr "cpu" "sb1,sb1a")
174 (and (eq_attr "type" "fpidxload") 171 (and (eq_attr "type" "fpidxload")
175 (eq (symbol_ref "TARGET_FLOAT64") 172 (not (match_test "TARGET_FLOAT64"))))
176 (const_int 0))))
177 "sb1_ls1") 173 "sb1_ls1")
178 174
179 ;; prefx can only execute on the ls1 pipe. 175 ;; prefx can only execute on the ls1 pipe.
180 176
181 (define_insn_reservation "ir_sb1_prefetchx" 0 177 (define_insn_reservation "ir_sb1_prefetchx" 0
218 214
219 (define_bypass 3 215 (define_bypass 3
220 "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, 216 "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
221 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp" 217 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp"
222 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" 218 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
223 "mips_store_data_bypass_p") 219 "!mips_store_data_bypass_p")
224 220
225 ;; On SB-1, simple alu instructions can execute on the LS1 unit. 221 ;; On SB-1, simple alu instructions can execute on the LS1 unit.
226 222
227 ;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX 223 ;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX
228 ;; insn, to a store (for data), and to an xfer insn. It has 1 cycle latency to 224 ;; insn, to a store (for data), and to an xfer insn. It has 1 cycle latency to
291 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") 287 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
292 288
293 (define_bypass 5 289 (define_bypass 5
294 "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo" 290 "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
295 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" 291 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
296 "mips_store_data_bypass_p") 292 "!mips_store_data_bypass_p")
297 293
298 ;; mf{hi,lo} is 1 cycle. 294 ;; mf{hi,lo} is 1 cycle.
299 295
300 (define_insn_reservation "ir_sb1_mfhi" 1 296 (define_insn_reservation "ir_sb1_mfhi" 1
301 (and (eq_attr "cpu" "sb1,sb1a") 297 (and (eq_attr "cpu" "sb1,sb1a")
302 (and (eq_attr "type" "mfhilo") 298 (eq_attr "type" "mfhi"))
303 (not (match_operand 1 "lo_operand"))))
304 "sb1_ex1") 299 "sb1_ex1")
305 300
306 (define_insn_reservation "ir_sb1_mflo" 1 301 (define_insn_reservation "ir_sb1_mflo" 1
307 (and (eq_attr "cpu" "sb1,sb1a") 302 (and (eq_attr "cpu" "sb1,sb1a")
308 (and (eq_attr "type" "mfhilo") 303 (eq_attr "type" "mflo"))
309 (match_operand 1 "lo_operand")))
310 "sb1_ex1") 304 "sb1_ex1")
311 305
312 ;; mt{hi,lo} to mul/div is 4 cycles. 306 ;; mt{hi,lo} to mul/div is 4 cycles.
313 307
314 (define_insn_reservation "ir_sb1_mthilo" 4 308 (define_insn_reservation "ir_sb1_mthilo" 4
315 (and (eq_attr "cpu" "sb1,sb1a") 309 (and (eq_attr "cpu" "sb1,sb1a")
316 (eq_attr "type" "mthilo")) 310 (eq_attr "type" "mthi,mtlo"))
317 "sb1_ex1") 311 "sb1_ex1")
318 312
319 ;; mt{hi,lo} to mf{hi,lo} is 3 cycles. 313 ;; mt{hi,lo} to mf{hi,lo} is 3 cycles.
320 314
321 (define_bypass 3 "ir_sb1_mthilo" "ir_sb1_mfhi,ir_sb1_mflo") 315 (define_bypass 3 "ir_sb1_mthilo" "ir_sb1_mfhi,ir_sb1_mflo")
355 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") 349 ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx")
356 350
357 (define_bypass 7 351 (define_bypass 7
358 "ir_sb1_mulsi,ir_sb1_muldi" 352 "ir_sb1_mulsi,ir_sb1_muldi"
359 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" 353 "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
360 "mips_store_data_bypass_p") 354 "!mips_store_data_bypass_p")
361 355
362 ;; The divide unit is not pipelined. Divide busy is asserted in the 4th 356 ;; The divide unit is not pipelined. Divide busy is asserted in the 4th
363 ;; cycle, and then deasserted on the latency cycle. So only one divide at 357 ;; cycle, and then deasserted on the latency cycle. So only one divide at
364 ;; a time, but the first/last 4 cycles can overlap. 358 ;; a time, but the first/last 4 cycles can overlap.
365 359