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comparison gcc/config/powerpcspe/e500mc64.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
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68:561a7518be6b 111:04ced10e8804
1 ;; Pipeline description for Freescale PowerPC e500mc64 core.
2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
20 ;;
21 ;; e500mc64 64-bit SU(2), LSU, FPU, BPU
22 ;; Max issue 3 insns/clock cycle (includes 1 branch)
23
24 (define_automaton "e500mc64_most,e500mc64_long,e500mc64_retire")
25 (define_cpu_unit "e500mc64_decode_0,e500mc64_decode_1" "e500mc64_most")
26 (define_cpu_unit "e500mc64_issue_0,e500mc64_issue_1" "e500mc64_most")
27 (define_cpu_unit "e500mc64_retire_0,e500mc64_retire_1" "e500mc64_retire")
28
29 ;; SU.
30 (define_cpu_unit "e500mc64_su0_stage0,e500mc64_su1_stage0" "e500mc64_most")
31
32 ;; MU.
33 (define_cpu_unit "e500mc64_mu_stage0,e500mc64_mu_stage1" "e500mc64_most")
34 (define_cpu_unit "e500mc64_mu_stage2,e500mc64_mu_stage3" "e500mc64_most")
35
36 ;; Non-pipelined division.
37 (define_cpu_unit "e500mc64_mu_div" "e500mc64_long")
38
39 ;; LSU.
40 (define_cpu_unit "e500mc64_lsu" "e500mc64_most")
41
42 ;; FPU.
43 (define_cpu_unit "e500mc64_fpu" "e500mc64_most")
44
45 ;; Branch unit.
46 (define_cpu_unit "e500mc64_bu" "e500mc64_most")
47
48 ;; The following units are used to make the automata deterministic.
49 (define_cpu_unit "present_e500mc64_decode_0" "e500mc64_most")
50 (define_cpu_unit "present_e500mc64_issue_0" "e500mc64_most")
51 (define_cpu_unit "present_e500mc64_retire_0" "e500mc64_retire")
52 (define_cpu_unit "present_e500mc64_su0_stage0" "e500mc64_most")
53
54 ;; The following sets to make automata deterministic when option ndfa is used.
55 (presence_set "present_e500mc64_decode_0" "e500mc64_decode_0")
56 (presence_set "present_e500mc64_issue_0" "e500mc64_issue_0")
57 (presence_set "present_e500mc64_retire_0" "e500mc64_retire_0")
58 (presence_set "present_e500mc64_su0_stage0" "e500mc64_su0_stage0")
59
60 ;; Some useful abbreviations.
61 (define_reservation "e500mc64_decode"
62 "e500mc64_decode_0|e500mc64_decode_1+present_e500mc64_decode_0")
63 (define_reservation "e500mc64_issue"
64 "e500mc64_issue_0|e500mc64_issue_1+present_e500mc64_issue_0")
65 (define_reservation "e500mc64_retire"
66 "e500mc64_retire_0|e500mc64_retire_1+present_e500mc64_retire_0")
67 (define_reservation "e500mc64_su_stage0"
68 "e500mc64_su0_stage0|e500mc64_su1_stage0+present_e500mc64_su0_stage0")
69
70 ;; Simple SU insns.
71 (define_insn_reservation "e500mc64_su" 1
72 (and (ior (eq_attr "type" "integer,insert,cntlz")
73 (and (eq_attr "type" "add,logical,exts")
74 (eq_attr "dot" "no"))
75 (and (eq_attr "type" "shift")
76 (eq_attr "dot" "no")
77 (eq_attr "var_shift" "no")))
78 (eq_attr "cpu" "ppce500mc64"))
79 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
80
81 (define_insn_reservation "e500mc64_su2" 2
82 (and (ior (eq_attr "type" "cmp,trap")
83 (and (eq_attr "type" "add,logical,exts")
84 (eq_attr "dot" "yes"))
85 (and (eq_attr "type" "shift")
86 (eq_attr "dot" "yes")
87 (eq_attr "var_shift" "no")))
88 (eq_attr "cpu" "ppce500mc64"))
89 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
90
91 (define_insn_reservation "e500mc64_delayed" 2
92 (and (eq_attr "type" "shift")
93 (eq_attr "var_shift" "yes")
94 (eq_attr "cpu" "ppce500mc64"))
95 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
96
97 (define_insn_reservation "e500mc64_two" 2
98 (and (eq_attr "type" "two")
99 (eq_attr "cpu" "ppce500mc64"))
100 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
101 e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
102
103 (define_insn_reservation "e500mc64_three" 3
104 (and (eq_attr "type" "three")
105 (eq_attr "cpu" "ppce500mc64"))
106 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
107 e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
108 e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
109
110 ;; Multiply.
111 (define_insn_reservation "e500mc64_multiply" 4
112 (and (eq_attr "type" "mul")
113 (eq_attr "cpu" "ppce500mc64"))
114 "e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0,e500mc64_mu_stage1,\
115 e500mc64_mu_stage2,e500mc64_mu_stage3+e500mc64_retire")
116
117 ;; Divide. We use the average latency time here.
118 (define_insn_reservation "e500mc64_divide" 14
119 (and (eq_attr "type" "div")
120 (eq_attr "cpu" "ppce500mc64"))
121 "e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0+e500mc64_mu_div,\
122 e500mc64_mu_div*13")
123
124 ;; Branch.
125 (define_insn_reservation "e500mc64_branch" 1
126 (and (eq_attr "type" "jmpreg,branch,isync")
127 (eq_attr "cpu" "ppce500mc64"))
128 "e500mc64_decode,e500mc64_bu,e500mc64_retire")
129
130 ;; CR logical.
131 (define_insn_reservation "e500mc64_cr_logical" 1
132 (and (eq_attr "type" "cr_logical,delayed_cr")
133 (eq_attr "cpu" "ppce500mc64"))
134 "e500mc64_decode,e500mc64_bu,e500mc64_retire")
135
136 ;; Mfcr.
137 (define_insn_reservation "e500mc64_mfcr" 4
138 (and (eq_attr "type" "mfcr")
139 (eq_attr "cpu" "ppce500mc64"))
140 "e500mc64_decode,e500mc64_issue+e500mc64_su1_stage0,e500mc64_su1_stage0*3+e500mc64_retire")
141
142 ;; Mtcrf.
143 (define_insn_reservation "e500mc64_mtcrf" 1
144 (and (eq_attr "type" "mtcr")
145 (eq_attr "cpu" "ppce500mc64"))
146 "e500mc64_decode,e500mc64_issue+e500mc64_su1_stage0+e500mc64_retire")
147
148 ;; Mtjmpr.
149 (define_insn_reservation "e500mc64_mtjmpr" 1
150 (and (eq_attr "type" "mtjmpr,mfjmpr")
151 (eq_attr "cpu" "ppce500mc64"))
152 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
153
154 ;; Brinc.
155 (define_insn_reservation "e500mc64_brinc" 1
156 (and (eq_attr "type" "brinc")
157 (eq_attr "cpu" "ppce500mc64"))
158 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
159
160 ;; Loads.
161 (define_insn_reservation "e500mc64_load" 3
162 (and (eq_attr "type" "load,load_l,sync")
163 (eq_attr "cpu" "ppce500mc64"))
164 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
165
166 (define_insn_reservation "e500mc64_fpload" 4
167 (and (eq_attr "type" "fpload")
168 (eq_attr "cpu" "ppce500mc64"))
169 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing*2,e500mc64_retire")
170
171 ;; Stores.
172 (define_insn_reservation "e500mc64_store" 3
173 (and (eq_attr "type" "store,store_c")
174 (eq_attr "cpu" "ppce500mc64"))
175 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
176
177 (define_insn_reservation "e500mc64_fpstore" 3
178 (and (eq_attr "type" "fpstore")
179 (eq_attr "cpu" "ppce500mc64"))
180 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
181
182 ;; The following ignores the retire unit to avoid a large automata.
183
184 ;; FP.
185 (define_insn_reservation "e500mc64_float" 7
186 (and (eq_attr "type" "fpsimple,fp,fpcompare,dmul")
187 (eq_attr "cpu" "ppce500mc64"))
188 "e500mc64_decode,e500mc64_issue+e500mc64_fpu")
189 ; "e500mc64_decode,e500mc64_issue+e500mc64_fpu,nothing*5,e500mc64_retire")
190
191 ;; FP divides are not pipelined.
192 (define_insn_reservation "e500mc64_sdiv" 20
193 (and (eq_attr "type" "sdiv")
194 (eq_attr "cpu" "ppce500mc64"))
195 "e500mc64_decode,e500mc64_issue+e500mc64_fpu,e500mc64_fpu*19")
196
197 (define_insn_reservation "e500mc64_ddiv" 35
198 (and (eq_attr "type" "ddiv")
199 (eq_attr "cpu" "ppce500mc64"))
200 "e500mc64_decode,e500mc64_issue+e500mc64_fpu,e500mc64_fpu*34")