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comparison gcc/config/rs6000/dfp.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents b7f97abdc517
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Decimal Floating Point (DFP) patterns. 1 ;; Decimal Floating Point (DFP) patterns.
2 ;; Copyright (C) 2007, 2008, 2010 2 ;; Copyright (C) 2007-2017 Free Software Foundation, Inc.
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner 3 ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner
5 ;; (bergner@vnet.ibm.com). 4 ;; (bergner@vnet.ibm.com).
6 5
7 ;; This file is part of GCC. 6 ;; This file is part of GCC.
8 7
22 21
23 ;; 22 ;;
24 ;; UNSPEC usage 23 ;; UNSPEC usage
25 ;; 24 ;;
26 25
27 (define_constants 26 (define_c_enum "unspec"
28 [(UNSPEC_MOVSD_LOAD 400) 27 [UNSPEC_MOVSD_LOAD
29 (UNSPEC_MOVSD_STORE 401) 28 UNSPEC_MOVSD_STORE
30 ]) 29 ])
31 30
32
33 (define_expand "movsd"
34 [(set (match_operand:SD 0 "nonimmediate_operand" "")
35 (match_operand:SD 1 "any_operand" ""))]
36 "TARGET_HARD_FLOAT && TARGET_FPRS"
37 "{ rs6000_emit_move (operands[0], operands[1], SDmode); DONE; }")
38
39 (define_split
40 [(set (match_operand:SD 0 "gpc_reg_operand" "")
41 (match_operand:SD 1 "const_double_operand" ""))]
42 "reload_completed
43 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
44 || (GET_CODE (operands[0]) == SUBREG
45 && GET_CODE (SUBREG_REG (operands[0])) == REG
46 && REGNO (SUBREG_REG (operands[0])) <= 31))"
47 [(set (match_dup 2) (match_dup 3))]
48 "
49 {
50 long l;
51 REAL_VALUE_TYPE rv;
52
53 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
54 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
55
56 if (! TARGET_POWERPC64)
57 operands[2] = operand_subword (operands[0], 0, 0, SDmode);
58 else
59 operands[2] = gen_lowpart (SImode, operands[0]);
60
61 operands[3] = gen_int_mode (l, SImode);
62 }")
63
64 (define_insn "movsd_hardfloat"
65 [(set (match_operand:SD 0 "nonimmediate_operand" "=r,r,m,f,*c*l,*q,!r,*h,!r,!r")
66 (match_operand:SD 1 "input_operand" "r,m,r,f,r,r,h,0,G,Fn"))]
67 "(gpc_reg_operand (operands[0], SDmode)
68 || gpc_reg_operand (operands[1], SDmode))
69 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
70 "@
71 mr %0,%1
72 {l%U1%X1|lwz%U1%X1} %0,%1
73 {st%U0%X0|stw%U0%X0} %1,%0
74 fmr %0,%1
75 mt%0 %1
76 mt%0 %1
77 mf%1 %0
78 {cror 0,0,0|nop}
79 #
80 #"
81 [(set_attr "type" "*,load,store,fp,mtjmpr,*,mfjmpr,*,*,*")
82 (set_attr "length" "4,4,4,4,4,4,4,4,4,8")])
83
84 (define_insn "movsd_softfloat"
85 [(set (match_operand:SD 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
86 (match_operand:SD 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
87 "(gpc_reg_operand (operands[0], SDmode)
88 || gpc_reg_operand (operands[1], SDmode))
89 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
90 "@
91 mr %0,%1
92 mt%0 %1
93 mt%0 %1
94 mf%1 %0
95 {l%U1%X1|lwz%U1%X1} %0,%1
96 {st%U0%X0|stw%U0%X0} %1,%0
97 {lil|li} %0,%1
98 {liu|lis} %0,%v1
99 {cal|la} %0,%a1
100 #
101 #
102 {cror 0,0,0|nop}"
103 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
104 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
105 31
106 (define_insn "movsd_store" 32 (define_insn "movsd_store"
107 [(set (match_operand:DD 0 "nonimmediate_operand" "=m") 33 [(set (match_operand:DD 0 "nonimmediate_operand" "=m")
108 (unspec:DD [(match_operand:SD 1 "input_operand" "d")] 34 (unspec:DD [(match_operand:SD 1 "input_operand" "d")]
109 UNSPEC_MOVSD_STORE))] 35 UNSPEC_MOVSD_STORE))]
110 "(gpc_reg_operand (operands[0], DDmode) 36 "(gpc_reg_operand (operands[0], DDmode)
111 || gpc_reg_operand (operands[1], SDmode)) 37 || gpc_reg_operand (operands[1], SDmode))
112 && TARGET_HARD_FLOAT && TARGET_FPRS" 38 && TARGET_HARD_FLOAT"
113 "stfd%U0%X0 %1,%0" 39 "stfd%U0%X0 %1,%0"
114 [(set_attr "type" "fpstore") 40 [(set_attr "type" "fpstore")
115 (set_attr "length" "4")]) 41 (set_attr "length" "4")])
116 42
117 (define_insn "movsd_load" 43 (define_insn "movsd_load"
118 [(set (match_operand:SD 0 "nonimmediate_operand" "=f") 44 [(set (match_operand:SD 0 "nonimmediate_operand" "=f")
119 (unspec:SD [(match_operand:DD 1 "input_operand" "m")] 45 (unspec:SD [(match_operand:DD 1 "input_operand" "m")]
120 UNSPEC_MOVSD_LOAD))] 46 UNSPEC_MOVSD_LOAD))]
121 "(gpc_reg_operand (operands[0], SDmode) 47 "(gpc_reg_operand (operands[0], SDmode)
122 || gpc_reg_operand (operands[1], DDmode)) 48 || gpc_reg_operand (operands[1], DDmode))
123 && TARGET_HARD_FLOAT && TARGET_FPRS" 49 && TARGET_HARD_FLOAT"
124 "lfd%U1%X1 %0,%1" 50 "lfd%U1%X1 %0,%1"
125 [(set_attr "type" "fpload") 51 [(set_attr "type" "fpload")
126 (set_attr "length" "4")]) 52 (set_attr "length" "4")])
127 53
128 ;; Hardware support for decimal floating point operations. 54 ;; Hardware support for decimal floating point operations.
130 (define_insn "extendsddd2" 56 (define_insn "extendsddd2"
131 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") 57 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
132 (float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))] 58 (float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))]
133 "TARGET_DFP" 59 "TARGET_DFP"
134 "dctdp %0,%1" 60 "dctdp %0,%1"
135 [(set_attr "type" "fp")]) 61 [(set_attr "type" "dfp")])
136 62
137 (define_expand "extendsdtd2" 63 (define_expand "extendsdtd2"
138 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") 64 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
139 (float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "d")))] 65 (float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "d")))]
140 "TARGET_DFP" 66 "TARGET_DFP"
148 (define_insn "truncddsd2" 74 (define_insn "truncddsd2"
149 [(set (match_operand:SD 0 "gpc_reg_operand" "=f") 75 [(set (match_operand:SD 0 "gpc_reg_operand" "=f")
150 (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))] 76 (float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))]
151 "TARGET_DFP" 77 "TARGET_DFP"
152 "drsp %0,%1" 78 "drsp %0,%1"
153 [(set_attr "type" "fp")]) 79 [(set_attr "type" "dfp")])
154 80
155 (define_expand "negdd2" 81 (define_insn "negdd2"
156 [(set (match_operand:DD 0 "gpc_reg_operand" "")
157 (neg:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
158 "TARGET_HARD_FLOAT && TARGET_FPRS"
159 "")
160
161 (define_insn "*negdd2_fpr"
162 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") 82 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
163 (neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] 83 (neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
164 "TARGET_HARD_FLOAT && TARGET_FPRS" 84 "TARGET_HARD_FLOAT"
165 "fneg %0,%1" 85 "fneg %0,%1"
166 [(set_attr "type" "fp")]) 86 [(set_attr "type" "fpsimple")])
167 87
168 (define_expand "absdd2" 88 (define_insn "absdd2"
169 [(set (match_operand:DD 0 "gpc_reg_operand" "")
170 (abs:DD (match_operand:DD 1 "gpc_reg_operand" "")))]
171 "TARGET_HARD_FLOAT && TARGET_FPRS"
172 "")
173
174 (define_insn "*absdd2_fpr"
175 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") 89 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
176 (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] 90 (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
177 "TARGET_HARD_FLOAT && TARGET_FPRS" 91 "TARGET_HARD_FLOAT"
178 "fabs %0,%1" 92 "fabs %0,%1"
179 [(set_attr "type" "fp")]) 93 [(set_attr "type" "fpsimple")])
180 94
181 (define_insn "*nabsdd2_fpr" 95 (define_insn "*nabsdd2_fpr"
182 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") 96 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
183 (neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))] 97 (neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
184 "TARGET_HARD_FLOAT && TARGET_FPRS" 98 "TARGET_HARD_FLOAT"
185 "fnabs %0,%1" 99 "fnabs %0,%1"
186 [(set_attr "type" "fp")]) 100 [(set_attr "type" "fpsimple")])
187 101
188 (define_expand "movdd" 102 (define_insn "negtd2"
189 [(set (match_operand:DD 0 "nonimmediate_operand" "") 103 [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
190 (match_operand:DD 1 "any_operand" ""))] 104 (neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
191 "" 105 "TARGET_HARD_FLOAT"
192 "{ rs6000_emit_move (operands[0], operands[1], DDmode); DONE; }")
193
194 (define_split
195 [(set (match_operand:DD 0 "gpc_reg_operand" "")
196 (match_operand:DD 1 "const_int_operand" ""))]
197 "! TARGET_POWERPC64 && reload_completed
198 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
199 || (GET_CODE (operands[0]) == SUBREG
200 && GET_CODE (SUBREG_REG (operands[0])) == REG
201 && REGNO (SUBREG_REG (operands[0])) <= 31))"
202 [(set (match_dup 2) (match_dup 4))
203 (set (match_dup 3) (match_dup 1))]
204 "
205 {
206 int endian = (WORDS_BIG_ENDIAN == 0);
207 HOST_WIDE_INT value = INTVAL (operands[1]);
208
209 operands[2] = operand_subword (operands[0], endian, 0, DDmode);
210 operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode);
211 #if HOST_BITS_PER_WIDE_INT == 32
212 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
213 #else
214 operands[4] = GEN_INT (value >> 32);
215 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
216 #endif
217 }")
218
219 (define_split
220 [(set (match_operand:DD 0 "gpc_reg_operand" "")
221 (match_operand:DD 1 "const_double_operand" ""))]
222 "! TARGET_POWERPC64 && reload_completed
223 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
224 || (GET_CODE (operands[0]) == SUBREG
225 && GET_CODE (SUBREG_REG (operands[0])) == REG
226 && REGNO (SUBREG_REG (operands[0])) <= 31))"
227 [(set (match_dup 2) (match_dup 4))
228 (set (match_dup 3) (match_dup 5))]
229 "
230 {
231 int endian = (WORDS_BIG_ENDIAN == 0);
232 long l[2];
233 REAL_VALUE_TYPE rv;
234
235 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
236 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
237
238 operands[2] = operand_subword (operands[0], endian, 0, DDmode);
239 operands[3] = operand_subword (operands[0], 1 - endian, 0, DDmode);
240 operands[4] = gen_int_mode (l[endian], SImode);
241 operands[5] = gen_int_mode (l[1 - endian], SImode);
242 }")
243
244 (define_split
245 [(set (match_operand:DD 0 "gpc_reg_operand" "")
246 (match_operand:DD 1 "const_double_operand" ""))]
247 "TARGET_POWERPC64 && reload_completed
248 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
249 || (GET_CODE (operands[0]) == SUBREG
250 && GET_CODE (SUBREG_REG (operands[0])) == REG
251 && REGNO (SUBREG_REG (operands[0])) <= 31))"
252 [(set (match_dup 2) (match_dup 3))]
253 "
254 {
255 int endian = (WORDS_BIG_ENDIAN == 0);
256 long l[2];
257 REAL_VALUE_TYPE rv;
258 #if HOST_BITS_PER_WIDE_INT >= 64
259 HOST_WIDE_INT val;
260 #endif
261
262 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
263 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
264
265 operands[2] = gen_lowpart (DImode, operands[0]);
266 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
267 #if HOST_BITS_PER_WIDE_INT >= 64
268 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
269 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
270
271 operands[3] = gen_int_mode (val, DImode);
272 #else
273 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
274 #endif
275 }")
276
277 ;; Don't have reload use general registers to load a constant. First,
278 ;; it might not work if the output operand is the equivalent of
279 ;; a non-offsettable memref, but also it is less efficient than loading
280 ;; the constant into an FP register, since it will probably be used there.
281 ;; The "??" is a kludge until we can figure out a more reasonable way
282 ;; of handling these non-offsettable values.
283 (define_insn "*movdd_hardfloat32"
284 [(set (match_operand:DD 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r")
285 (match_operand:DD 1 "input_operand" "r,m,r,d,m,d,G,H,F"))]
286 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
287 && (gpc_reg_operand (operands[0], DDmode)
288 || gpc_reg_operand (operands[1], DDmode))"
289 "*
290 {
291 switch (which_alternative)
292 {
293 default:
294 gcc_unreachable ();
295 case 0:
296 case 1:
297 case 2:
298 return \"#\";
299 case 3:
300 return \"fmr %0,%1\";
301 case 4:
302 return \"lfd%U1%X1 %0,%1\";
303 case 5:
304 return \"stfd%U0%X0 %1,%0\";
305 case 6:
306 case 7:
307 case 8:
308 return \"#\";
309 }
310 }"
311 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
312 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
313
314 (define_insn "*movdd_softfloat32"
315 [(set (match_operand:DD 0 "nonimmediate_operand" "=r,r,m,r,r,r")
316 (match_operand:DD 1 "input_operand" "r,m,r,G,H,F"))]
317 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
318 && (gpc_reg_operand (operands[0], DDmode)
319 || gpc_reg_operand (operands[1], DDmode))"
320 "#"
321 [(set_attr "type" "two,load,store,*,*,*")
322 (set_attr "length" "8,8,8,8,12,16")])
323
324 ; ld/std require word-aligned displacements -> 'Y' constraint.
325 ; List Y->r and r->Y before r->r for reload.
326 (define_insn "*movdd_hardfloat64_mfpgpr"
327 [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d")
328 (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))]
329 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
330 && (gpc_reg_operand (operands[0], DDmode)
331 || gpc_reg_operand (operands[1], DDmode))"
332 "@ 106 "@
333 std%U0%X0 %1,%0 107 fneg %0,%1
334 ld%U1%X1 %0,%1 108 fneg %0,%1\;fmr %L0,%L1"
335 mr %0,%1 109 [(set_attr "type" "fpsimple")
336 fmr %0,%1 110 (set_attr "length" "4,8")])
337 lfd%U1%X1 %0,%1 111
338 stfd%U0%X0 %1,%0 112 (define_insn "abstd2"
339 mt%0 %1 113 [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
340 mf%1 %0 114 (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
341 {cror 0,0,0|nop} 115 "TARGET_HARD_FLOAT"
342 #
343 #
344 #
345 mftgpr %0,%1
346 mffgpr %0,%1"
347 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
348 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
349
350 ; ld/std require word-aligned displacements -> 'Y' constraint.
351 ; List Y->r and r->Y before r->r for reload.
352 (define_insn "*movdd_hardfloat64"
353 [(set (match_operand:DD 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r")
354 (match_operand:DD 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))]
355 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
356 && (gpc_reg_operand (operands[0], DDmode)
357 || gpc_reg_operand (operands[1], DDmode))"
358 "@ 116 "@
359 std%U0%X0 %1,%0 117 fabs %0,%1
360 ld%U1%X1 %0,%1 118 fabs %0,%1\;fmr %L0,%L1"
361 mr %0,%1 119 [(set_attr "type" "fpsimple")
362 fmr %0,%1 120 (set_attr "length" "4,8")])
363 lfd%U1%X1 %0,%1 121
364 stfd%U0%X0 %1,%0 122 (define_insn "*nabstd2_fpr"
365 mt%0 %1 123 [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
366 mf%1 %0 124 (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]
367 {cror 0,0,0|nop} 125 "TARGET_HARD_FLOAT"
368 #
369 #
370 #"
371 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
372 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
373
374 (define_insn "*movdd_softfloat64"
375 [(set (match_operand:DD 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
376 (match_operand:DD 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
377 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
378 && (gpc_reg_operand (operands[0], DDmode)
379 || gpc_reg_operand (operands[1], DDmode))"
380 "@ 126 "@
381 ld%U1%X1 %0,%1 127 fnabs %0,%1
382 std%U0%X0 %1,%0 128 fnabs %0,%1\;fmr %L0,%L1"
383 mr %0,%1 129 [(set_attr "type" "fpsimple")
384 mt%0 %1 130 (set_attr "length" "4,8")])
385 mf%1 %0
386 #
387 #
388 #
389 {cror 0,0,0|nop}"
390 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
391 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
392
393 (define_expand "negtd2"
394 [(set (match_operand:TD 0 "gpc_reg_operand" "")
395 (neg:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
396 "TARGET_HARD_FLOAT && TARGET_FPRS"
397 "")
398
399 (define_insn "*negtd2_fpr"
400 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
401 (neg:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
402 "TARGET_HARD_FLOAT && TARGET_FPRS"
403 "fneg %0,%1"
404 [(set_attr "type" "fp")])
405
406 (define_expand "abstd2"
407 [(set (match_operand:TD 0 "gpc_reg_operand" "")
408 (abs:TD (match_operand:TD 1 "gpc_reg_operand" "")))]
409 "TARGET_HARD_FLOAT && TARGET_FPRS"
410 "")
411
412 (define_insn "*abstd2_fpr"
413 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
414 (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
415 "TARGET_HARD_FLOAT && TARGET_FPRS"
416 "fabs %0,%1"
417 [(set_attr "type" "fp")])
418
419 (define_insn "*nabstd2_fpr"
420 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
421 (neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "d"))))]
422 "TARGET_HARD_FLOAT && TARGET_FPRS"
423 "fnabs %0,%1"
424 [(set_attr "type" "fp")])
425
426 (define_expand "movtd"
427 [(set (match_operand:TD 0 "general_operand" "")
428 (match_operand:TD 1 "any_operand" ""))]
429 "TARGET_HARD_FLOAT && TARGET_FPRS"
430 "{ rs6000_emit_move (operands[0], operands[1], TDmode); DONE; }")
431
432 ; It's important to list the o->f and f->o moves before f->f because
433 ; otherwise reload, given m->f, will try to pick f->f and reload it,
434 ; which doesn't make progress. Likewise r->Y must be before r->r.
435 (define_insn_and_split "*movtd_internal"
436 [(set (match_operand:TD 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
437 (match_operand:TD 1 "input_operand" "d,o,d,YGHF,r,r"))]
438 "TARGET_HARD_FLOAT && TARGET_FPRS
439 && (gpc_reg_operand (operands[0], TDmode)
440 || gpc_reg_operand (operands[1], TDmode))"
441 "#"
442 "&& reload_completed"
443 [(pc)]
444 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
445 [(set_attr "length" "8,8,8,20,20,16")])
446 131
447 ;; Hardware support for decimal floating point operations. 132 ;; Hardware support for decimal floating point operations.
448 133
449 (define_insn "extendddtd2" 134 (define_insn "extendddtd2"
450 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") 135 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
451 (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))] 136 (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))]
452 "TARGET_DFP" 137 "TARGET_DFP"
453 "dctqpq %0,%1" 138 "dctqpq %0,%1"
454 [(set_attr "type" "fp")]) 139 [(set_attr "type" "dfp")])
455 140
456 ;; The result of drdpq is an even/odd register pair with the converted 141 ;; The result of drdpq is an even/odd register pair with the converted
457 ;; value in the even register and zero in the odd register. 142 ;; value in the even register and zero in the odd register.
458 ;; FIXME: Avoid the register move by using a reload constraint to ensure 143 ;; FIXME: Avoid the register move by using a reload constraint to ensure
459 ;; that the result is the first of the pair receiving the result of drdpq. 144 ;; that the result is the first of the pair receiving the result of drdpq.
462 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") 147 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
463 (float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d"))) 148 (float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d")))
464 (clobber (match_scratch:TD 2 "=d"))] 149 (clobber (match_scratch:TD 2 "=d"))]
465 "TARGET_DFP" 150 "TARGET_DFP"
466 "drdpq %2,%1\;fmr %0,%2" 151 "drdpq %2,%1\;fmr %0,%2"
467 [(set_attr "type" "fp")]) 152 [(set_attr "type" "dfp")
153 (set_attr "length" "8")])
468 154
469 (define_insn "adddd3" 155 (define_insn "adddd3"
470 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") 156 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
471 (plus:DD (match_operand:DD 1 "gpc_reg_operand" "%d") 157 (plus:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
472 (match_operand:DD 2 "gpc_reg_operand" "d")))] 158 (match_operand:DD 2 "gpc_reg_operand" "d")))]
473 "TARGET_DFP" 159 "TARGET_DFP"
474 "dadd %0,%1,%2" 160 "dadd %0,%1,%2"
475 [(set_attr "type" "fp")]) 161 [(set_attr "type" "dfp")])
476 162
477 (define_insn "addtd3" 163 (define_insn "addtd3"
478 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") 164 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
479 (plus:TD (match_operand:TD 1 "gpc_reg_operand" "%d") 165 (plus:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
480 (match_operand:TD 2 "gpc_reg_operand" "d")))] 166 (match_operand:TD 2 "gpc_reg_operand" "d")))]
481 "TARGET_DFP" 167 "TARGET_DFP"
482 "daddq %0,%1,%2" 168 "daddq %0,%1,%2"
483 [(set_attr "type" "fp")]) 169 [(set_attr "type" "dfp")])
484 170
485 (define_insn "subdd3" 171 (define_insn "subdd3"
486 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") 172 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
487 (minus:DD (match_operand:DD 1 "gpc_reg_operand" "d") 173 (minus:DD (match_operand:DD 1 "gpc_reg_operand" "d")
488 (match_operand:DD 2 "gpc_reg_operand" "d")))] 174 (match_operand:DD 2 "gpc_reg_operand" "d")))]
489 "TARGET_DFP" 175 "TARGET_DFP"
490 "dsub %0,%1,%2" 176 "dsub %0,%1,%2"
491 [(set_attr "type" "fp")]) 177 [(set_attr "type" "dfp")])
492 178
493 (define_insn "subtd3" 179 (define_insn "subtd3"
494 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") 180 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
495 (minus:TD (match_operand:TD 1 "gpc_reg_operand" "d") 181 (minus:TD (match_operand:TD 1 "gpc_reg_operand" "d")
496 (match_operand:TD 2 "gpc_reg_operand" "d")))] 182 (match_operand:TD 2 "gpc_reg_operand" "d")))]
497 "TARGET_DFP" 183 "TARGET_DFP"
498 "dsubq %0,%1,%2" 184 "dsubq %0,%1,%2"
499 [(set_attr "type" "fp")]) 185 [(set_attr "type" "dfp")])
500 186
501 (define_insn "muldd3" 187 (define_insn "muldd3"
502 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") 188 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
503 (mult:DD (match_operand:DD 1 "gpc_reg_operand" "%d") 189 (mult:DD (match_operand:DD 1 "gpc_reg_operand" "%d")
504 (match_operand:DD 2 "gpc_reg_operand" "d")))] 190 (match_operand:DD 2 "gpc_reg_operand" "d")))]
505 "TARGET_DFP" 191 "TARGET_DFP"
506 "dmul %0,%1,%2" 192 "dmul %0,%1,%2"
507 [(set_attr "type" "fp")]) 193 [(set_attr "type" "dfp")])
508 194
509 (define_insn "multd3" 195 (define_insn "multd3"
510 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") 196 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
511 (mult:TD (match_operand:TD 1 "gpc_reg_operand" "%d") 197 (mult:TD (match_operand:TD 1 "gpc_reg_operand" "%d")
512 (match_operand:TD 2 "gpc_reg_operand" "d")))] 198 (match_operand:TD 2 "gpc_reg_operand" "d")))]
513 "TARGET_DFP" 199 "TARGET_DFP"
514 "dmulq %0,%1,%2" 200 "dmulq %0,%1,%2"
515 [(set_attr "type" "fp")]) 201 [(set_attr "type" "dfp")])
516 202
517 (define_insn "divdd3" 203 (define_insn "divdd3"
518 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") 204 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
519 (div:DD (match_operand:DD 1 "gpc_reg_operand" "d") 205 (div:DD (match_operand:DD 1 "gpc_reg_operand" "d")
520 (match_operand:DD 2 "gpc_reg_operand" "d")))] 206 (match_operand:DD 2 "gpc_reg_operand" "d")))]
521 "TARGET_DFP" 207 "TARGET_DFP"
522 "ddiv %0,%1,%2" 208 "ddiv %0,%1,%2"
523 [(set_attr "type" "fp")]) 209 [(set_attr "type" "dfp")])
524 210
525 (define_insn "divtd3" 211 (define_insn "divtd3"
526 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") 212 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
527 (div:TD (match_operand:TD 1 "gpc_reg_operand" "d") 213 (div:TD (match_operand:TD 1 "gpc_reg_operand" "d")
528 (match_operand:TD 2 "gpc_reg_operand" "d")))] 214 (match_operand:TD 2 "gpc_reg_operand" "d")))]
529 "TARGET_DFP" 215 "TARGET_DFP"
530 "ddivq %0,%1,%2" 216 "ddivq %0,%1,%2"
531 [(set_attr "type" "fp")]) 217 [(set_attr "type" "dfp")])
532 218
533 (define_insn "*cmpdd_internal1" 219 (define_insn "*cmpdd_internal1"
534 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 220 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
535 (compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "d") 221 (compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "d")
536 (match_operand:DD 2 "gpc_reg_operand" "d")))] 222 (match_operand:DD 2 "gpc_reg_operand" "d")))]
537 "TARGET_DFP" 223 "TARGET_DFP"
538 "dcmpu %0,%1,%2" 224 "dcmpu %0,%1,%2"
539 [(set_attr "type" "fpcompare")]) 225 [(set_attr "type" "dfp")])
540 226
541 (define_insn "*cmptd_internal1" 227 (define_insn "*cmptd_internal1"
542 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 228 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
543 (compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "d") 229 (compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "d")
544 (match_operand:TD 2 "gpc_reg_operand" "d")))] 230 (match_operand:TD 2 "gpc_reg_operand" "d")))]
545 "TARGET_DFP" 231 "TARGET_DFP"
546 "dcmpuq %0,%1,%2" 232 "dcmpuq %0,%1,%2"
547 [(set_attr "type" "fpcompare")]) 233 [(set_attr "type" "dfp")])
234
235 (define_insn "floatdidd2"
236 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
237 (float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
238 "TARGET_DFP && TARGET_POPCNTD"
239 "dcffix %0,%1"
240 [(set_attr "type" "dfp")])
548 241
549 (define_insn "floatditd2" 242 (define_insn "floatditd2"
550 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") 243 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
551 (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))] 244 (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))]
552 "TARGET_DFP" 245 "TARGET_DFP"
553 "dcffixq %0,%1" 246 "dcffixq %0,%1"
554 [(set_attr "type" "fp")]) 247 [(set_attr "type" "dfp")])
555 248
556 ;; Convert a decimal64 to a decimal64 whose value is an integer. 249 ;; Convert a decimal64 to a decimal64 whose value is an integer.
557 ;; This is the first stage of converting it to an integer type. 250 ;; This is the first stage of converting it to an integer type.
558 251
559 (define_insn "ftruncdd2" 252 (define_insn "ftruncdd2"
560 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") 253 [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
561 (fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] 254 (fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
562 "TARGET_DFP" 255 "TARGET_DFP"
563 "drintn. 0,%0,%1,1" 256 "drintn. 0,%0,%1,1"
564 [(set_attr "type" "fp")]) 257 [(set_attr "type" "dfp")])
565 258
566 ;; Convert a decimal64 whose value is an integer to an actual integer. 259 ;; Convert a decimal64 whose value is an integer to an actual integer.
567 ;; This is the second stage of converting decimal float to integer type. 260 ;; This is the second stage of converting decimal float to integer type.
568 261
569 (define_insn "fixdddi2" 262 (define_insn "fixdddi2"
570 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") 263 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
571 (fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))] 264 (fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))]
572 "TARGET_DFP" 265 "TARGET_DFP"
573 "dctfix %0,%1" 266 "dctfix %0,%1"
574 [(set_attr "type" "fp")]) 267 [(set_attr "type" "dfp")])
575 268
576 ;; Convert a decimal128 to a decimal128 whose value is an integer. 269 ;; Convert a decimal128 to a decimal128 whose value is an integer.
577 ;; This is the first stage of converting it to an integer type. 270 ;; This is the first stage of converting it to an integer type.
578 271
579 (define_insn "ftrunctd2" 272 (define_insn "ftrunctd2"
580 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") 273 [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
581 (fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] 274 (fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))]
582 "TARGET_DFP" 275 "TARGET_DFP"
583 "drintnq. 0,%0,%1,1" 276 "drintnq. 0,%0,%1,1"
584 [(set_attr "type" "fp")]) 277 [(set_attr "type" "dfp")])
585 278
586 ;; Convert a decimal128 whose value is an integer to an actual integer. 279 ;; Convert a decimal128 whose value is an integer to an actual integer.
587 ;; This is the second stage of converting decimal float to integer type. 280 ;; This is the second stage of converting decimal float to integer type.
588 281
589 (define_insn "fixtddi2" 282 (define_insn "fixtddi2"
590 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") 283 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
591 (fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))] 284 (fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))]
592 "TARGET_DFP" 285 "TARGET_DFP"
593 "dctfixq %0,%1" 286 "dctfixq %0,%1"
287 [(set_attr "type" "dfp")])
288
289
290 ;; Decimal builtin support
291
292 (define_c_enum "unspec"
293 [UNSPEC_DDEDPD
294 UNSPEC_DENBCD
295 UNSPEC_DXEX
296 UNSPEC_DIEX
297 UNSPEC_DSCLI
298 UNSPEC_DTSTSFI
299 UNSPEC_DSCRI])
300
301 (define_code_iterator DFP_TEST [eq lt gt unordered])
302
303 (define_mode_iterator D64_D128 [DD TD])
304
305 (define_mode_attr dfp_suffix [(DD "")
306 (TD "q")])
307
308 (define_insn "dfp_ddedpd_<mode>"
309 [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
310 (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i")
311 (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
312 UNSPEC_DDEDPD))]
313 "TARGET_DFP"
314 "ddedpd<dfp_suffix> %1,%0,%2"
315 [(set_attr "type" "dfp")])
316
317 (define_insn "dfp_denbcd_<mode>"
318 [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
319 (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i")
320 (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
321 UNSPEC_DENBCD))]
322 "TARGET_DFP"
323 "denbcd<dfp_suffix> %1,%0,%2"
324 [(set_attr "type" "dfp")])
325
326 (define_insn "dfp_dxex_<mode>"
327 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
328 (unspec:DI [(match_operand:D64_D128 1 "gpc_reg_operand" "d")]
329 UNSPEC_DXEX))]
330 "TARGET_DFP"
331 "dxex<dfp_suffix> %0,%1"
332 [(set_attr "type" "dfp")])
333
334 (define_insn "dfp_diex_<mode>"
335 [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
336 (unspec:D64_D128 [(match_operand:DI 1 "gpc_reg_operand" "d")
337 (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
338 UNSPEC_DXEX))]
339 "TARGET_DFP"
340 "diex<dfp_suffix> %0,%1,%2"
341 [(set_attr "type" "dfp")])
342
343 (define_expand "dfptstsfi_<code>_<mode>"
344 [(set (match_dup 3)
345 (compare:CCFP
346 (unspec:D64_D128
347 [(match_operand:SI 1 "const_int_operand" "n")
348 (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
349 UNSPEC_DTSTSFI)
350 (match_dup 4)))
351 (set (match_operand:SI 0 "register_operand" "")
352 (DFP_TEST:SI (match_dup 3)
353 (const_int 0)))
354 ]
355 "TARGET_P9_MISC"
356 {
357 operands[3] = gen_reg_rtx (CCFPmode);
358 operands[4] = const0_rtx;
359 })
360
361 (define_insn "*dfp_sgnfcnc_<mode>"
362 [(set (match_operand:CCFP 0 "" "=y")
363 (compare:CCFP
364 (unspec:D64_D128 [(match_operand:SI 1 "const_int_operand" "n")
365 (match_operand:D64_D128 2 "gpc_reg_operand" "d")]
366 UNSPEC_DTSTSFI)
367 (match_operand:SI 3 "zero_constant" "j")))]
368 "TARGET_P9_MISC"
369 {
370 /* If immediate operand is greater than 63, it will behave as if
371 the value had been 63. The code generator does not support
372 immediate operand values greater than 63. */
373 if (!(IN_RANGE (INTVAL (operands[1]), 0, 63)))
374 operands[1] = GEN_INT (63);
375 return "dtstsfi<dfp_suffix> %0,%1,%2";
376 }
594 [(set_attr "type" "fp")]) 377 [(set_attr "type" "fp")])
378
379 (define_insn "dfp_dscli_<mode>"
380 [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
381 (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
382 (match_operand:QI 2 "immediate_operand" "i")]
383 UNSPEC_DSCLI))]
384 "TARGET_DFP"
385 "dscli<dfp_suffix> %0,%1,%2"
386 [(set_attr "type" "dfp")])
387
388 (define_insn "dfp_dscri_<mode>"
389 [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d")
390 (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d")
391 (match_operand:QI 2 "immediate_operand" "i")]
392 UNSPEC_DSCRI))]
393 "TARGET_DFP"
394 "dscri<dfp_suffix> %0,%1,%2"
395 [(set_attr "type" "dfp")])