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comparison gcc/config/rs6000/e500mc64.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 77e2b8dfacca
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Pipeline description for Freescale PowerPC e500mc64 core. 1 ;; Pipeline description for Freescale PowerPC e500mc64 core.
2 ;; Copyright (C) 2009 Free Software Foundation, Inc. 2 ;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com) 3 ;; Contributed by Edmar Wienskoski (edmar@freescale.com)
4 ;; 4 ;;
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 ;; 6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it 7 ;; GCC is free software; you can redistribute it and/or modify it
67 (define_reservation "e500mc64_su_stage0" 67 (define_reservation "e500mc64_su_stage0"
68 "e500mc64_su0_stage0|e500mc64_su1_stage0+present_e500mc64_su0_stage0") 68 "e500mc64_su0_stage0|e500mc64_su1_stage0+present_e500mc64_su0_stage0")
69 69
70 ;; Simple SU insns. 70 ;; Simple SU insns.
71 (define_insn_reservation "e500mc64_su" 1 71 (define_insn_reservation "e500mc64_su" 1
72 (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\ 72 (and (ior (eq_attr "type" "integer,insert,cntlz")
73 shift,cntlz,exts") 73 (and (eq_attr "type" "add,logical,exts")
74 (eq_attr "dot" "no"))
75 (and (eq_attr "type" "shift")
76 (eq_attr "dot" "no")
77 (eq_attr "var_shift" "no")))
74 (eq_attr "cpu" "ppce500mc64")) 78 (eq_attr "cpu" "ppce500mc64"))
75 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire") 79 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
76 80
77 (define_insn_reservation "e500mc64_su2" 2 81 (define_insn_reservation "e500mc64_su2" 2
78 (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare,trap") 82 (and (ior (eq_attr "type" "cmp,trap")
83 (and (eq_attr "type" "add,logical,exts")
84 (eq_attr "dot" "yes"))
85 (and (eq_attr "type" "shift")
86 (eq_attr "dot" "yes")
87 (eq_attr "var_shift" "no")))
79 (eq_attr "cpu" "ppce500mc64")) 88 (eq_attr "cpu" "ppce500mc64"))
80 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire") 89 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
81 90
82 (define_insn_reservation "e500mc64_delayed" 2 91 (define_insn_reservation "e500mc64_delayed" 2
83 (and (eq_attr "type" "var_shift_rotate,var_delayed_compare") 92 (and (eq_attr "type" "shift")
93 (eq_attr "var_shift" "yes")
84 (eq_attr "cpu" "ppce500mc64")) 94 (eq_attr "cpu" "ppce500mc64"))
85 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire") 95 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0,e500mc64_retire")
86 96
87 (define_insn_reservation "e500mc64_two" 2 97 (define_insn_reservation "e500mc64_two" 2
88 (and (eq_attr "type" "two") 98 (and (eq_attr "type" "two")
97 e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\ 107 e500mc64_issue+e500mc64_su_stage0+e500mc64_retire,\
98 e500mc64_issue+e500mc64_su_stage0+e500mc64_retire") 108 e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
99 109
100 ;; Multiply. 110 ;; Multiply.
101 (define_insn_reservation "e500mc64_multiply" 4 111 (define_insn_reservation "e500mc64_multiply" 4
102 (and (eq_attr "type" "imul,imul2,imul3,imul_compare") 112 (and (eq_attr "type" "mul")
103 (eq_attr "cpu" "ppce500mc64")) 113 (eq_attr "cpu" "ppce500mc64"))
104 "e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0,e500mc64_mu_stage1,\ 114 "e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0,e500mc64_mu_stage1,\
105 e500mc64_mu_stage2,e500mc64_mu_stage3+e500mc64_retire") 115 e500mc64_mu_stage2,e500mc64_mu_stage3+e500mc64_retire")
106 116
107 ;; Divide. We use the average latency time here. 117 ;; Divide. We use the average latency time here.
108 (define_insn_reservation "e500mc64_divide" 14 118 (define_insn_reservation "e500mc64_divide" 14
109 (and (eq_attr "type" "idiv") 119 (and (eq_attr "type" "div")
110 (eq_attr "cpu" "ppce500mc64")) 120 (eq_attr "cpu" "ppce500mc64"))
111 "e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0+e500mc64_mu_div,\ 121 "e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0+e500mc64_mu_div,\
112 e500mc64_mu_div*13") 122 e500mc64_mu_div*13")
113 123
114 ;; Branch. 124 ;; Branch.
139 (define_insn_reservation "e500mc64_mtjmpr" 1 149 (define_insn_reservation "e500mc64_mtjmpr" 1
140 (and (eq_attr "type" "mtjmpr,mfjmpr") 150 (and (eq_attr "type" "mtjmpr,mfjmpr")
141 (eq_attr "cpu" "ppce500mc64")) 151 (eq_attr "cpu" "ppce500mc64"))
142 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire") 152 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
143 153
144 ;; Brinc.
145 (define_insn_reservation "e500mc64_brinc" 1
146 (and (eq_attr "type" "brinc")
147 (eq_attr "cpu" "ppce500mc64"))
148 "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
149
150 ;; Loads. 154 ;; Loads.
151 (define_insn_reservation "e500mc64_load" 3 155 (define_insn_reservation "e500mc64_load" 3
152 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ 156 (and (eq_attr "type" "load,load_l,sync")
153 load_l,sync")
154 (eq_attr "cpu" "ppce500mc64")) 157 (eq_attr "cpu" "ppce500mc64"))
155 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire") 158 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
156 159
157 (define_insn_reservation "e500mc64_fpload" 4 160 (define_insn_reservation "e500mc64_fpload" 4
158 (and (eq_attr "type" "fpload,fpload_ux,fpload_u") 161 (and (eq_attr "type" "fpload")
159 (eq_attr "cpu" "ppce500mc64")) 162 (eq_attr "cpu" "ppce500mc64"))
160 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing*2,e500mc64_retire") 163 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing*2,e500mc64_retire")
161 164
162 ;; Stores. 165 ;; Stores.
163 (define_insn_reservation "e500mc64_store" 3 166 (define_insn_reservation "e500mc64_store" 3
164 (and (eq_attr "type" "store,store_ux,store_u,store_c") 167 (and (eq_attr "type" "store,store_c")
165 (eq_attr "cpu" "ppce500mc64")) 168 (eq_attr "cpu" "ppce500mc64"))
166 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire") 169 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
167 170
168 (define_insn_reservation "e500mc64_fpstore" 3 171 (define_insn_reservation "e500mc64_fpstore" 3
169 (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") 172 (and (eq_attr "type" "fpstore")
170 (eq_attr "cpu" "ppce500mc64")) 173 (eq_attr "cpu" "ppce500mc64"))
171 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire") 174 "e500mc64_decode,e500mc64_issue+e500mc64_lsu,nothing,e500mc64_retire")
172 175
173 ;; The following ignores the retire unit to avoid a large automata. 176 ;; The following ignores the retire unit to avoid a large automata.
174 177