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comparison gcc/config/rs6000/rs6000-cpus.def @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
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children 84e7813d76e9
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68:561a7518be6b 111:04ced10e8804
1 /* IBM RS/6000 CPU names..
2 Copyright (C) 1991-2017 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 /* ISA masks. */
22 #ifndef ISA_2_1_MASKS
23 #define ISA_2_1_MASKS OPTION_MASK_MFCRF
24 #define ISA_2_2_MASKS (ISA_2_1_MASKS | OPTION_MASK_POPCNTB)
25 #define ISA_2_4_MASKS (ISA_2_2_MASKS | OPTION_MASK_FPRND)
26
27 /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
28 ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
29 fre, fsqrt, etc. were no longer documented as optional. Group masks by
30 server and embedded. */
31 #define ISA_2_5_MASKS_EMBEDDED (ISA_2_4_MASKS \
32 | OPTION_MASK_CMPB \
33 | OPTION_MASK_RECIP_PRECISION \
34 | OPTION_MASK_PPC_GFXOPT \
35 | OPTION_MASK_PPC_GPOPT)
36
37 #define ISA_2_5_MASKS_SERVER (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_DFP)
38
39 /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
40 altivec is a win so enable it. */
41 #define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
42 #define ISA_2_6_MASKS_SERVER (ISA_2_5_MASKS_SERVER \
43 | OPTION_MASK_POPCNTD \
44 | OPTION_MASK_ALTIVEC \
45 | OPTION_MASK_VSX)
46
47 /* For now, don't provide an embedded version of ISA 2.07. */
48 #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
49 | OPTION_MASK_P8_FUSION \
50 | OPTION_MASK_P8_VECTOR \
51 | OPTION_MASK_CRYPTO \
52 | OPTION_MASK_DIRECT_MOVE \
53 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
54 | OPTION_MASK_HTM \
55 | OPTION_MASK_QUAD_MEMORY \
56 | OPTION_MASK_QUAD_MEMORY_ATOMIC)
57
58 /* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
59 FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
60 #define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \
61 | OPTION_MASK_ISEL \
62 | OPTION_MASK_MODULO \
63 | OPTION_MASK_P9_FUSION \
64 | OPTION_MASK_P9_MINMAX \
65 | OPTION_MASK_P9_MISC \
66 | OPTION_MASK_P9_VECTOR)
67
68 /* Support for the IEEE 128-bit floating point hardware requires a lot of the
69 VSX instructions that are part of ISA 3.0. */
70 #define ISA_3_0_MASKS_IEEE (OPTION_MASK_VSX \
71 | OPTION_MASK_P8_VECTOR \
72 | OPTION_MASK_P9_VECTOR \
73 | OPTION_MASK_DIRECT_MOVE)
74
75 /* Flags that need to be turned off if -mno-power9-vector. */
76 #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
77 | OPTION_MASK_P9_MINMAX)
78
79 /* Flags that need to be turned off if -mno-power8-vector. */
80 #define OTHER_P8_VECTOR_MASKS (OTHER_P9_VECTOR_MASKS \
81 | OPTION_MASK_P9_VECTOR \
82 | OPTION_MASK_DIRECT_MOVE \
83 | OPTION_MASK_CRYPTO)
84
85 /* Flags that need to be turned off if -mno-vsx. */
86 #define OTHER_VSX_VECTOR_MASKS (OTHER_P8_VECTOR_MASKS \
87 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
88 | OPTION_MASK_FLOAT128_KEYWORD \
89 | OPTION_MASK_P8_VECTOR)
90
91 #define POWERPC_7400_MASK (OPTION_MASK_PPC_GFXOPT | OPTION_MASK_ALTIVEC)
92
93 /* Deal with ports that do not have -mstrict-align. */
94 #ifdef OPTION_MASK_STRICT_ALIGN
95 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL OPTION_MASK_STRICT_ALIGN
96 #else
97 #define OPTION_MASK_STRICT_ALIGN 0
98 #define OPTION_MASK_STRICT_ALIGN_OPTIONAL 0
99 #ifndef MASK_STRICT_ALIGN
100 #define MASK_STRICT_ALIGN 0
101 #endif
102 #endif
103
104 /* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
105 #define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
106 | OPTION_MASK_CMPB \
107 | OPTION_MASK_CRYPTO \
108 | OPTION_MASK_DFP \
109 | OPTION_MASK_DIRECT_MOVE \
110 | OPTION_MASK_DLMZB \
111 | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
112 | OPTION_MASK_FLOAT128_HW \
113 | OPTION_MASK_FLOAT128_KEYWORD \
114 | OPTION_MASK_FPRND \
115 | OPTION_MASK_HTM \
116 | OPTION_MASK_ISEL \
117 | OPTION_MASK_MFCRF \
118 | OPTION_MASK_MFPGPR \
119 | OPTION_MASK_MODULO \
120 | OPTION_MASK_MULHW \
121 | OPTION_MASK_NO_UPDATE \
122 | OPTION_MASK_P8_FUSION \
123 | OPTION_MASK_P8_VECTOR \
124 | OPTION_MASK_P9_FUSION \
125 | OPTION_MASK_P9_MINMAX \
126 | OPTION_MASK_P9_MISC \
127 | OPTION_MASK_P9_VECTOR \
128 | OPTION_MASK_POPCNTB \
129 | OPTION_MASK_POPCNTD \
130 | OPTION_MASK_POWERPC64 \
131 | OPTION_MASK_PPC_GFXOPT \
132 | OPTION_MASK_PPC_GPOPT \
133 | OPTION_MASK_QUAD_MEMORY \
134 | OPTION_MASK_QUAD_MEMORY_ATOMIC \
135 | OPTION_MASK_RECIP_PRECISION \
136 | OPTION_MASK_SOFT_FLOAT \
137 | OPTION_MASK_STRICT_ALIGN_OPTIONAL \
138 | OPTION_MASK_TOC_FUSION \
139 | OPTION_MASK_VSX)
140
141 #endif
142
143 /* This table occasionally claims that a processor does not support a
144 particular feature even though it does, but the feature is slower than the
145 alternative. Thus, it shouldn't be relied on as a complete description of
146 the processor's support.
147
148 Please keep this list in order, and don't forget to update the documentation
149 in invoke.texi when adding a new processor or flag.
150
151 Before including this file, define a macro:
152
153 RS6000_CPU (NAME, CPU, FLAGS)
154
155 where the arguments are the fields of struct rs6000_ptt. */
156
157 RS6000_CPU ("401", PROCESSOR_PPC403, MASK_SOFT_FLOAT)
158 RS6000_CPU ("403", PROCESSOR_PPC403, MASK_SOFT_FLOAT | MASK_STRICT_ALIGN)
159 RS6000_CPU ("405", PROCESSOR_PPC405, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
160 RS6000_CPU ("405fp", PROCESSOR_PPC405, MASK_MULHW | MASK_DLMZB)
161 RS6000_CPU ("440", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
162 RS6000_CPU ("440fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
163 RS6000_CPU ("464", PROCESSOR_PPC440, MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB)
164 RS6000_CPU ("464fp", PROCESSOR_PPC440, MASK_MULHW | MASK_DLMZB)
165 RS6000_CPU ("476", PROCESSOR_PPC476,
166 MASK_SOFT_FLOAT | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB
167 | MASK_FPRND | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
168 RS6000_CPU ("476fp", PROCESSOR_PPC476,
169 MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
170 | MASK_CMPB | MASK_MULHW | MASK_DLMZB)
171 RS6000_CPU ("505", PROCESSOR_MPCCORE, 0)
172 RS6000_CPU ("601", PROCESSOR_PPC601, MASK_MULTIPLE | MASK_STRING)
173 RS6000_CPU ("602", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
174 RS6000_CPU ("603", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
175 RS6000_CPU ("603e", PROCESSOR_PPC603, MASK_PPC_GFXOPT)
176 RS6000_CPU ("604", PROCESSOR_PPC604, MASK_PPC_GFXOPT)
177 RS6000_CPU ("604e", PROCESSOR_PPC604e, MASK_PPC_GFXOPT)
178 RS6000_CPU ("620", PROCESSOR_PPC620, MASK_PPC_GFXOPT | MASK_POWERPC64)
179 RS6000_CPU ("630", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
180 RS6000_CPU ("740", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
181 RS6000_CPU ("7400", PROCESSOR_PPC7400, POWERPC_7400_MASK)
182 RS6000_CPU ("7450", PROCESSOR_PPC7450, POWERPC_7400_MASK)
183 RS6000_CPU ("750", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
184 RS6000_CPU ("801", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
185 RS6000_CPU ("821", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
186 RS6000_CPU ("823", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
187 RS6000_CPU ("8540", PROCESSOR_PPC8540, MASK_STRICT_ALIGN | MASK_ISEL)
188 RS6000_CPU ("8548", PROCESSOR_PPC8548, MASK_STRICT_ALIGN | MASK_ISEL)
189 RS6000_CPU ("a2", PROCESSOR_PPCA2,
190 MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB | MASK_CMPB
191 | MASK_NO_UPDATE)
192 RS6000_CPU ("e300c2", PROCESSOR_PPCE300C2, MASK_SOFT_FLOAT)
193 RS6000_CPU ("e300c3", PROCESSOR_PPCE300C3, 0)
194 RS6000_CPU ("e500mc", PROCESSOR_PPCE500MC, MASK_PPC_GFXOPT | MASK_ISEL)
195 RS6000_CPU ("e500mc64", PROCESSOR_PPCE500MC64,
196 MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
197 RS6000_CPU ("e5500", PROCESSOR_PPCE5500,
198 MASK_POWERPC64 | MASK_PPC_GFXOPT | MASK_ISEL)
199 RS6000_CPU ("e6500", PROCESSOR_PPCE6500, POWERPC_7400_MASK | MASK_POWERPC64
200 | MASK_MFCRF | MASK_ISEL)
201 RS6000_CPU ("860", PROCESSOR_MPCCORE, MASK_SOFT_FLOAT)
202 RS6000_CPU ("970", PROCESSOR_POWER4,
203 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
204 RS6000_CPU ("cell", PROCESSOR_CELL,
205 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
206 RS6000_CPU ("ec603e", PROCESSOR_PPC603, MASK_SOFT_FLOAT)
207 RS6000_CPU ("G3", PROCESSOR_PPC750, MASK_PPC_GFXOPT)
208 RS6000_CPU ("G4", PROCESSOR_PPC7450, POWERPC_7400_MASK)
209 RS6000_CPU ("G5", PROCESSOR_POWER4,
210 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64)
211 RS6000_CPU ("titan", PROCESSOR_TITAN, MASK_MULHW | MASK_DLMZB)
212 RS6000_CPU ("power3", PROCESSOR_PPC630, MASK_PPC_GFXOPT | MASK_POWERPC64)
213 RS6000_CPU ("power4", PROCESSOR_POWER4, MASK_POWERPC64 | MASK_PPC_GPOPT
214 | MASK_PPC_GFXOPT | MASK_MFCRF)
215 RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
216 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB)
217 RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 | MASK_PPC_GPOPT
218 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND)
219 RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
220 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
221 | MASK_CMPB | MASK_DFP | MASK_RECIP_PRECISION)
222 RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
223 | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND
224 | MASK_CMPB | MASK_DFP | MASK_MFPGPR | MASK_RECIP_PRECISION)
225 RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 | ISA_2_6_MASKS_SERVER)
226 RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
227 RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER)
228 RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
229 RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
230 RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
231 RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)