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comparison gcc/config/rs6000/rs64.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents 77e2b8dfacca
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Scheduling description for IBM RS64 processors. 1 ;; Scheduling description for IBM RS64 processors.
2 ;; Copyright (C) 2003, 2004, 2007, 2009 Free Software Foundation, Inc. 2 ;; Copyright (C) 2003-2017 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 5
6 ;; GCC is free software; you can redistribute it and/or modify it 6 ;; GCC is free software; you can redistribute it and/or modify it
7 ;; under the terms of the GNU General Public License as published 7 ;; under the terms of the GNU General Public License as published
24 (define_cpu_unit "lsu_rs64,bpu_rs64" "rs64") 24 (define_cpu_unit "lsu_rs64,bpu_rs64" "rs64")
25 25
26 ;; RS64a 64-bit IU, LSU, FPU, BPU 26 ;; RS64a 64-bit IU, LSU, FPU, BPU
27 27
28 (define_insn_reservation "rs64a-load" 2 28 (define_insn_reservation "rs64a-load" 2
29 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") 29 (and (eq_attr "type" "load")
30 (eq_attr "cpu" "rs64a")) 30 (eq_attr "cpu" "rs64a"))
31 "lsu_rs64") 31 "lsu_rs64")
32 32
33 (define_insn_reservation "rs64a-store" 2 33 (define_insn_reservation "rs64a-store" 2
34 (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") 34 (and (eq_attr "type" "store,fpstore")
35 (eq_attr "cpu" "rs64a")) 35 (eq_attr "cpu" "rs64a"))
36 "lsu_rs64") 36 "lsu_rs64")
37 37
38 (define_insn_reservation "rs64a-fpload" 3 38 (define_insn_reservation "rs64a-fpload" 3
39 (and (eq_attr "type" "fpload,fpload_ux,fpload_u") 39 (and (eq_attr "type" "fpload")
40 (eq_attr "cpu" "rs64a")) 40 (eq_attr "cpu" "rs64a"))
41 "lsu_rs64") 41 "lsu_rs64")
42 42
43 (define_insn_reservation "rs64a-llsc" 2 43 (define_insn_reservation "rs64a-llsc" 2
44 (and (eq_attr "type" "load_l,store_c") 44 (and (eq_attr "type" "load_l,store_c")
45 (eq_attr "cpu" "rs64a")) 45 (eq_attr "cpu" "rs64a"))
46 "lsu_rs64") 46 "lsu_rs64")
47 47
48 (define_insn_reservation "rs64a-integer" 1 48 (define_insn_reservation "rs64a-integer" 1
49 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ 49 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
50 var_shift_rotate,cntlz,exts,isel") 50 (and (eq_attr "type" "add,logical,shift,exts")
51 (eq_attr "dot" "no")))
51 (eq_attr "cpu" "rs64a")) 52 (eq_attr "cpu" "rs64a"))
52 "iu_rs64") 53 "iu_rs64")
53 54
54 (define_insn_reservation "rs64a-two" 1 55 (define_insn_reservation "rs64a-two" 1
55 (and (eq_attr "type" "two") 56 (and (eq_attr "type" "two")
60 (and (eq_attr "type" "three") 61 (and (eq_attr "type" "three")
61 (eq_attr "cpu" "rs64a")) 62 (eq_attr "cpu" "rs64a"))
62 "iu_rs64,iu_rs64,iu_rs64") 63 "iu_rs64,iu_rs64,iu_rs64")
63 64
64 (define_insn_reservation "rs64a-imul" 20 65 (define_insn_reservation "rs64a-imul" 20
65 (and (eq_attr "type" "imul,imul_compare") 66 (and (eq_attr "type" "mul")
67 (eq_attr "size" "32")
66 (eq_attr "cpu" "rs64a")) 68 (eq_attr "cpu" "rs64a"))
67 "mciu_rs64*13") 69 "mciu_rs64*13")
68 70
69 (define_insn_reservation "rs64a-imul2" 12 71 (define_insn_reservation "rs64a-imul2" 12
70 (and (eq_attr "type" "imul2") 72 (and (eq_attr "type" "mul")
73 (eq_attr "size" "16")
71 (eq_attr "cpu" "rs64a")) 74 (eq_attr "cpu" "rs64a"))
72 "mciu_rs64*5") 75 "mciu_rs64*5")
73 76
74 (define_insn_reservation "rs64a-imul3" 8 77 (define_insn_reservation "rs64a-imul3" 8
75 (and (eq_attr "type" "imul3") 78 (and (eq_attr "type" "mul")
79 (eq_attr "size" "8")
76 (eq_attr "cpu" "rs64a")) 80 (eq_attr "cpu" "rs64a"))
77 "mciu_rs64*2") 81 "mciu_rs64*2")
78 82
79 (define_insn_reservation "rs64a-lmul" 34 83 (define_insn_reservation "rs64a-lmul" 34
80 (and (eq_attr "type" "lmul,lmul_compare") 84 (and (eq_attr "type" "mul")
85 (eq_attr "size" "64")
81 (eq_attr "cpu" "rs64a")) 86 (eq_attr "cpu" "rs64a"))
82 "mciu_rs64*34") 87 "mciu_rs64*34")
83 88
84 (define_insn_reservation "rs64a-idiv" 66 89 (define_insn_reservation "rs64a-idiv" 66
85 (and (eq_attr "type" "idiv") 90 (and (eq_attr "type" "div")
91 (eq_attr "size" "32")
86 (eq_attr "cpu" "rs64a")) 92 (eq_attr "cpu" "rs64a"))
87 "mciu_rs64*66") 93 "mciu_rs64*66")
88 94
89 (define_insn_reservation "rs64a-ldiv" 66 95 (define_insn_reservation "rs64a-ldiv" 66
90 (and (eq_attr "type" "ldiv") 96 (and (eq_attr "type" "div")
97 (eq_attr "size" "64")
91 (eq_attr "cpu" "rs64a")) 98 (eq_attr "cpu" "rs64a"))
92 "mciu_rs64*66") 99 "mciu_rs64*66")
93 100
94 (define_insn_reservation "rs64a-compare" 3 101 (define_insn_reservation "rs64a-compare" 3
95 (and (eq_attr "type" "cmp,fast_compare,compare,\ 102 (and (ior (eq_attr "type" "cmp")
96 delayed_compare,var_delayed_compare") 103 (and (eq_attr "type" "add,logical,shift,exts")
104 (eq_attr "dot" "yes")))
97 (eq_attr "cpu" "rs64a")) 105 (eq_attr "cpu" "rs64a"))
98 "iu_rs64,nothing,bpu_rs64") 106 "iu_rs64,nothing,bpu_rs64")
99 107
100 (define_insn_reservation "rs64a-fpcompare" 5 108 (define_insn_reservation "rs64a-fpcompare" 5
101 (and (eq_attr "type" "fpcompare") 109 (and (eq_attr "type" "fpcompare")
102 (eq_attr "cpu" "rs64a")) 110 (eq_attr "cpu" "rs64a"))
103 "mciu_rs64,fpu_rs64,bpu_rs64") 111 "mciu_rs64,fpu_rs64,bpu_rs64")
104 112
105 (define_insn_reservation "rs64a-fp" 4 113 (define_insn_reservation "rs64a-fp" 4
106 (and (eq_attr "type" "fp,dmul") 114 (and (eq_attr "type" "fp,fpsimple,dmul")
107 (eq_attr "cpu" "rs64a")) 115 (eq_attr "cpu" "rs64a"))
108 "mciu_rs64,fpu_rs64") 116 "mciu_rs64,fpu_rs64")
109 117
110 (define_insn_reservation "rs64a-sdiv" 31 118 (define_insn_reservation "rs64a-sdiv" 31
111 (and (eq_attr "type" "sdiv,ddiv") 119 (and (eq_attr "type" "sdiv,ddiv")