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comparison gcc/config/rx/rx.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
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68:561a7518be6b 111:04ced10e8804
1 ;; Machine Description for Renesas RX processors 1 ;; Machine Description for Renesas RX processors
2 ;; Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc. 2 ;; Copyright (C) 2008-2017 Free Software Foundation, Inc.
3 ;; Contributed by Red Hat. 3 ;; Contributed by Red Hat.
4 4
5 ;; This file is part of GCC. 5 ;; This file is part of GCC.
6 6
7 ;; GCC is free software; you can redistribute it and/or modify 7 ;; GCC is free software; you can redistribute it and/or modify
19 ;; <http://www.gnu.org/licenses/>. 19 ;; <http://www.gnu.org/licenses/>.
20 20
21 21
22 ;; This code iterator is used for sign- and zero- extensions. 22 ;; This code iterator is used for sign- and zero- extensions.
23 (define_mode_iterator small_int_modes [(HI "") (QI "")]) 23 (define_mode_iterator small_int_modes [(HI "") (QI "")])
24
25 ;; This code iterator is used for max and min operations.
26 (define_mode_iterator int_modes [(SI "") (HI "") (QI "")])
24 27
25 ;; We do not handle DFmode here because it is either 28 ;; We do not handle DFmode here because it is either
26 ;; the same as SFmode, or if -m64bit-doubles is active 29 ;; the same as SFmode, or if -m64bit-doubles is active
27 ;; then all operations on doubles have to be handled by 30 ;; then all operations on doubles have to be handled by
28 ;; library functions. 31 ;; library functions.
29 (define_mode_iterator register_modes 32 (define_mode_iterator register_modes
30 [(SF "ALLOW_RX_FPU_INSNS") (SI "") (HI "") (QI "")]) 33 [(SF "") (SI "") (HI "") (QI "")])
31 34
32 (define_constants 35 (define_constants
33 [ 36 [
34 (SP_REG 0) 37 (SP_REG 0)
35 (CC_REG 16) 38 (CC_REG 16)
68 (UNSPEC_BUILTIN_RMPA 47) 71 (UNSPEC_BUILTIN_RMPA 47)
69 (UNSPEC_BUILTIN_ROUND 48) 72 (UNSPEC_BUILTIN_ROUND 48)
70 (UNSPEC_BUILTIN_SAT 49) 73 (UNSPEC_BUILTIN_SAT 49)
71 (UNSPEC_BUILTIN_SETPSW 50) 74 (UNSPEC_BUILTIN_SETPSW 50)
72 (UNSPEC_BUILTIN_WAIT 51) 75 (UNSPEC_BUILTIN_WAIT 51)
76
77 (UNSPEC_PID_ADDR 52)
78
79 (CTRLREG_PSW 0)
80 (CTRLREG_USP 2)
81 (CTRLREG_FPSW 3)
82 (CTRLREG_CPEN 4)
83 (CTRLREG_BPSW 8)
84 (CTRLREG_BPC 9)
85 (CTRLREG_ISP 10)
86 (CTRLREG_FINTV 11)
87 (CTRLREG_INTB 12)
73 ] 88 ]
74 ) 89 )
75 90
76 (define_attr "length" "" (const_int 8)) 91 (define_attr "length" "" (const_int 8))
77 92
325 (define_insn "tablejump" 340 (define_insn "tablejump"
326 [(set (pc) 341 [(set (pc)
327 (match_operand:SI 0 "register_operand" "r")) 342 (match_operand:SI 0 "register_operand" "r"))
328 (use (label_ref (match_operand 1 "" "")))] 343 (use (label_ref (match_operand 1 "" "")))]
329 "" 344 ""
330 { return flag_pic ? (TARGET_AS100_SYNTAX ? "\n?:\tbra\t%0" 345 { return TARGET_PID ? (TARGET_AS100_SYNTAX ? "\n?:\tbra\t%0"
331 : "\n1:\tbra\t%0") 346 : "\n1:\tbra\t%0")
332 : "jmp\t%0"; 347 : "\n1:jmp\t%0";
333 } 348 }
334 [(set_attr "timings" "33") 349 [(set_attr "timings" "33")
335 (set_attr "length" "2")] 350 (set_attr "length" "2")]
336 ) 351 )
337 352
353 (define_expand "return"
354 [(return)]
355 "rx_can_use_simple_return ()"
356 "rx_expand_epilogue (false); DONE;"
357 )
358
338 (define_insn "simple_return" 359 (define_insn "simple_return"
339 [(return)] 360 [(simple_return)]
340 "" 361 ""
341 "rts" 362 "rts"
342 [(set_attr "length" "1") 363 [(set_attr "length" "1")
343 (set_attr "timings" "55")] 364 (set_attr "timings" "55")]
344 ) 365 )
394 ) 415 )
395 416
396 417
397 ;; Note - the following set of patterns do not use the "memory_operand" 418 ;; Note - the following set of patterns do not use the "memory_operand"
398 ;; predicate or an "m" constraint because we do not allow symbol_refs 419 ;; predicate or an "m" constraint because we do not allow symbol_refs
399 ;; or label_refs as legitmate memory addresses. This matches the 420 ;; or label_refs as legitimate memory addresses. This matches the
400 ;; behaviour of most of the RX instructions. Only the call/branch 421 ;; behavior of most of the RX instructions. Only the call/branch
401 ;; instructions are allowed to refer to symbols/labels directly. 422 ;; instructions are allowed to refer to symbols/labels directly.
402 ;; The call operands are in QImode because that is the value of 423 ;; The call operands are in QImode because that is the value of
403 ;; FUNCTION_MODE 424 ;; FUNCTION_MODE
404 425
405 (define_expand "call" 426 (define_expand "call"
551 (define_expand "mov<register_modes:mode>" 572 (define_expand "mov<register_modes:mode>"
552 [(set (match_operand:register_modes 0 "general_operand") 573 [(set (match_operand:register_modes 0 "general_operand")
553 (match_operand:register_modes 1 "general_operand"))] 574 (match_operand:register_modes 1 "general_operand"))]
554 "" 575 ""
555 { 576 {
556 if (MEM_P (operand0) && MEM_P (operand1)) 577 if (MEM_P (operands[0]) && MEM_P (operands[1]))
557 operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operand1); 578 operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operands[1]);
579 operands[0] = rx_maybe_pidify_operand (operands[0], 0);
580 operands[1] = rx_maybe_pidify_operand (operands[1], 0);
581 if (GET_CODE (operands[0]) != REG
582 && GET_CODE (operands[1]) == PLUS)
583 operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operands[1]);
584 if (GET_CODE (operands[1]) == PLUS && GET_MODE (operands[1]) == SImode)
585 {
586 emit_insn (gen_addsi3 (operands[0], XEXP (operands[1], 0), XEXP (operands[1], 1)));
587 DONE;
588 }
558 if (CONST_INT_P (operand1) 589 if (CONST_INT_P (operand1)
559 && ! rx_is_legitimate_constant (operand1)) 590 && ! rx_is_legitimate_constant (<register_modes:MODE>mode, operand1))
560 FAIL; 591 FAIL;
561 } 592 }
562 ) 593 )
563 594
564 (define_insn "*mov<register_modes:mode>_internal" 595 (define_insn "*mov<register_modes:mode>_internal"
565 [(set (match_operand:register_modes 596 [(set (match_operand:register_modes
566 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,Q,Q,Q,Q") 597 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,Q,Q,Q,Q,r")
567 (match_operand:register_modes 598 (match_operand:register_modes
568 1 "general_operand" "Int08,Sint16,Sint24,i,r,m,r,Int08,Sint16,Sint24,i"))] 599 1 "general_operand" "Int08,Sint16,Sint24,i,r,m,r,Int08,Sint16,Sint24,i,RpdaRpid"))]
569 "" 600 ""
570 { return rx_gen_move_template (operands, false); } 601 { return rx_gen_move_template (operands, false); }
571 [(set_attr "length" "3,4,5,6,2,4,6,5,6,7,8") 602 [(set_attr "length" "3,4,5,6,2,4,6,5,6,7,8,8")
572 (set_attr "timings" "11,11,11,11,11,12,11,11,11,11,11")] 603 (set_attr "timings" "11,11,11,11,11,12,11,11,11,11,11,11")]
573 ) 604 )
574 605
575 (define_insn "extend<small_int_modes:mode>si2" 606 (define_insn "extend<small_int_modes:mode>si2"
576 [(set (match_operand:SI 0 "register_operand" "=r,r") 607 [(set (match_operand:SI 0 "register_operand" "=r,r")
577 (sign_extend:SI (match_operand:small_int_modes 608 (sign_extend:SI (match_operand:small_int_modes
594 625
595 (define_insn "stack_push" 626 (define_insn "stack_push"
596 [(set (reg:SI SP_REG) 627 [(set (reg:SI SP_REG)
597 (minus:SI (reg:SI SP_REG) 628 (minus:SI (reg:SI SP_REG)
598 (const_int 4))) 629 (const_int 4)))
599 (set (mem:SI (reg:SI SP_REG)) 630 (set (mem:SI (minus:SI (reg:SI SP_REG) (const_int 4)))
600 (match_operand:SI 0 "register_operand" "r"))] 631 (match_operand:SI 0 "register_operand" "r"))]
601 "" 632 ""
602 "push.l\t%0" 633 "push.l\t%0"
603 [(set_attr "length" "2")] 634 [(set_attr "length" "2")]
604 ) 635 )
656 { 687 {
657 rtx flags, x; 688 rtx flags, x;
658 689
659 flags = gen_rtx_REG (CCmode, CC_REG); 690 flags = gen_rtx_REG (CCmode, CC_REG);
660 x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]); 691 x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]);
661 x = gen_rtx_SET (VOIDmode, flags, x); 692 x = gen_rtx_SET (flags, x);
662 emit_insn (x); 693 emit_insn (x);
663 694
664 x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx); 695 x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx);
665 x = gen_rtx_SET (VOIDmode, operands[0], x); 696 x = gen_rtx_SET (operands[0], x);
666 emit_insn (x); 697 emit_insn (x);
667 DONE; 698 DONE;
668 }) 699 })
669 700
670 (define_insn "*sccc" 701 (define_insn "*sccc"
688 { 719 {
689 rtx flags, x; 720 rtx flags, x;
690 721
691 flags = gen_rtx_REG (CC_Fmode, CC_REG); 722 flags = gen_rtx_REG (CC_Fmode, CC_REG);
692 x = gen_rtx_COMPARE (CC_Fmode, operands[2], operands[3]); 723 x = gen_rtx_COMPARE (CC_Fmode, operands[2], operands[3]);
693 x = gen_rtx_SET (VOIDmode, flags, x); 724 x = gen_rtx_SET (flags, x);
694 emit_insn (x); 725 emit_insn (x);
695 726
696 x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx); 727 x = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, flags, const0_rtx);
697 x = gen_rtx_SET (VOIDmode, operands[0], x); 728 x = gen_rtx_SET (operands[0], x);
698 emit_insn (x); 729 emit_insn (x);
699 DONE; 730 DONE;
700 }) 731 })
701 732
702 (define_expand "movsicc" 733 (define_expand "movsicc"
706 (match_operand:SI 2 "nonmemory_operand") 737 (match_operand:SI 2 "nonmemory_operand")
707 (match_operand:SI 3 "nonmemory_operand"))) 738 (match_operand:SI 3 "nonmemory_operand")))
708 (clobber (reg:CC CC_REG))])] 739 (clobber (reg:CC CC_REG))])]
709 "" 740 ""
710 { 741 {
711 /* ??? Support other conditions via cstore into a temporary? */ 742 /* One operand must be a constant or a register, the other must be a register. */
712 if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE) 743 if ( ! CONSTANT_P (operands[2])
713 FAIL; 744 && ! CONSTANT_P (operands[3])
714 /* One operand must be a constant. */ 745 && ! (REG_P (operands[2]) && REG_P (operands[3])))
715 if (!CONSTANT_P (operands[2]) && !CONSTANT_P (operands[3]))
716 FAIL; 746 FAIL;
717 }) 747 })
718 748
719 (define_insn_and_split "*movsicc" 749 (define_insn_and_split "*movsicc"
720 [(set (match_operand:SI 0 "register_operand" "=r,r") 750 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
721 (if_then_else:SI 751 (if_then_else:SI
722 (match_operator 5 "rx_z_comparison_operator" 752 (match_operator 5 "comparison_operator"
723 [(match_operand:SI 3 "register_operand" "r,r") 753 [(match_operand:SI 3 "register_operand" "r,r,r")
724 (match_operand:SI 4 "rx_source_operand" "riQ,riQ")]) 754 (match_operand:SI 4 "rx_source_operand" "riQ,riQ,riQ")])
725 (match_operand:SI 1 "nonmemory_operand" "i,ri") 755 (match_operand:SI 1 "nonmemory_operand" "i,ri,r")
726 (match_operand:SI 2 "nonmemory_operand" "ri,i"))) 756 (match_operand:SI 2 "nonmemory_operand" "ri,i,r")))
727 (clobber (reg:CC CC_REG))] 757 (clobber (reg:CC CC_REG))]
728 "CONSTANT_P (operands[1]) || CONSTANT_P (operands[2])" 758 "(CONSTANT_P (operands[1]) || CONSTANT_P (operands[2]))
759 || (REG_P (operands[1]) && REG_P (operands[2]))"
729 "#" 760 "#"
730 "&& reload_completed" 761 "&& reload_completed"
731 [(const_int 0)] 762 [(const_int 0)]
732 { 763 {
733 rtx x, flags, op0, op1, op2; 764 rtx x, flags, op0, op1, op2;
734 enum rtx_code cmp_code; 765 enum rtx_code cmp_code;
735 766
736 flags = gen_rtx_REG (CCmode, CC_REG); 767 flags = gen_rtx_REG (CCmode, CC_REG);
737 x = gen_rtx_COMPARE (CCmode, operands[3], operands[4]); 768 x = gen_rtx_COMPARE (CCmode, operands[3], operands[4]);
738 emit_insn (gen_rtx_SET (VOIDmode, flags, x)); 769 emit_insn (gen_rtx_SET (flags, x));
739 770
740 cmp_code = GET_CODE (operands[5]); 771 cmp_code = GET_CODE (operands[5]);
741 op0 = operands[0]; 772 op0 = operands[0];
742 op1 = operands[1]; 773 op1 = operands[1];
743 op2 = operands[2]; 774 op2 = operands[2];
744 775
745 /* If OP2 is the constant, reverse the sense of the move. */ 776 /* If OP2 is the constant, reverse the sense of the move.
746 if (!CONSTANT_P (operands[1])) 777 Likewise if both operands are registers but OP1 == OP0. */
778 if ((! CONSTANT_P (operands[1]) && CONSTANT_P (operands[2]))
779 || (REG_P (operands[1]) && REG_P (operands[2])
780 && rtx_equal_p (op0, op1)))
747 { 781 {
748 x = op1, op1 = op2, op2 = x; 782 x = op1, op1 = op2, op2 = x;
749 cmp_code = reverse_condition (cmp_code); 783 cmp_code = reverse_condition (cmp_code);
750 } 784 }
751 785
752 /* If OP2 does not match the output, copy it into place. We have allowed 786 /* If OP2 does not match the output, copy it into place. We have allowed
753 these alternatives so that the destination can legitimately be one of 787 these alternatives so that the destination can legitimately be one of
754 the comparison operands without increasing register pressure. */ 788 the comparison operands without increasing register pressure. */
755 if (!rtx_equal_p (op0, op2)) 789 if (! rtx_equal_p (op0, op2))
756 emit_move_insn (op0, op2); 790 emit_move_insn (op0, op2);
757 791
758 x = gen_rtx_fmt_ee (cmp_code, VOIDmode, flags, const0_rtx); 792 x = gen_rtx_fmt_ee (cmp_code, VOIDmode, flags, const0_rtx);
759 x = gen_rtx_IF_THEN_ELSE (SImode, x, op1, op0); 793 x = gen_rtx_IF_THEN_ELSE (SImode, x, op1, op0);
760 emit_insn (gen_rtx_SET (VOIDmode, op0, x)); 794 emit_insn (gen_rtx_SET (op0, x));
761 DONE; 795 DONE;
762 }) 796 })
763 797
764 (define_insn "*stcc" 798 (define_insn "*stcc"
765 [(set (match_operand:SI 0 "register_operand" "+r,r,r,r") 799 [(set (match_operand:SI 0 "register_operand" "+r,r,r,r")
766 (if_then_else:SI 800 (if_then_else:SI
767 (match_operator 2 "rx_z_comparison_operator" 801 (match_operator 2 "rx_z_comparison_operator"
768 [(reg CC_REG) (const_int 0)]) 802 [(reg CC_REG) (const_int 0)])
769 (match_operand:SI 1 "immediate_operand" "Sint08,Sint16,Sint24,i") 803 (match_operand:SI 1 "immediate_operand" "Sint08,Sint16,Sint24,i")
770 (match_dup 0)))] 804 (match_dup 0)))]
805 "reload_completed
806 && ((GET_CODE (operands[2]) == EQ) || (GET_CODE (operands[2]) == NE))"
807 {
808 if (GET_CODE (operands[2]) == EQ)
809 return "stz\t%1, %0";
810 else
811 return "stnz\t%1, %0";
812 }
813 [(set_attr "length" "4,5,6,7")]
814 )
815
816 (define_insn "*stcc_reg"
817 [(set (match_operand:SI 0 "register_operand" "+r,r,r,r,r,r")
818 (if_then_else:SI
819 (match_operator 2 "comparison_operator"
820 [(reg CC_REG) (const_int 0)])
821 (match_operand:SI 1 "nonmemory_operand"
822 "r,Uint04,Sint08,Sint16,Sint24,i")
823 (match_dup 0)))]
771 "reload_completed" 824 "reload_completed"
772 { 825 {
773 if (GET_CODE (operands[2]) == EQ) 826 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
774 return "stz\t%1, %0"; 827 return "b%B2 1f\n\tmov %1, %0\n1:";
775 else 828 }
776 return "stnz\t%1, %0"; 829 [(set_attr "length" "3,3,4,5,6,7")]
777 }
778 [(set_attr "length" "4,5,6,7")]
779 ) 830 )
780 831
781 ;; Arithmetic Instructions 832 ;; Arithmetic Instructions
782 833
783 (define_insn "abssi2" 834 (define_insn "abssi2"
790 abs\t%1, %0" 841 abs\t%1, %0"
791 [(set_attr "length" "2,3")] 842 [(set_attr "length" "2,3")]
792 ) 843 )
793 844
794 (define_insn "*abssi2_flags" 845 (define_insn "*abssi2_flags"
795 [(set (match_operand:SI 0 "register_operand" "=r,r") 846 [(set (reg CC_REG)
796 (abs:SI (match_operand:SI 1 "register_operand" "0,r"))) 847 (compare (abs:SI (match_operand:SI 1 "register_operand" "0,r"))
797 (set (reg CC_REG) 848 (const_int 0)))
798 (compare (abs:SI (match_dup 1)) 849 (set (match_operand:SI 0 "register_operand" "=r,r")
799 (const_int 0)))] 850 (abs:SI (match_dup 1)))]
800 ;; Note - although the ABS instruction does set the O bit in the processor 851 ;; Note - although the ABS instruction does set the O bit in the processor
801 ;; status word, it does not do so in a way that is comparable with the CMP 852 ;; status word, it does not do so in a way that is comparable with the CMP
802 ;; instruction. Hence we use CC_ZSmode rather than CC_ZSOmode. 853 ;; instruction. Hence we use CC_ZSmode rather than CC_ZSOmode.
803 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" 854 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
804 "@ 855 "@
805 abs\t%0 856 abs\t%0
806 abs\t%1, %0" 857 abs\t%1, %0"
807 [(set_attr "length" "2,3")] 858 [(set_attr "length" "2,3")]
808 ) 859 )
809 860
810 (define_insn "addsi3" 861 (define_expand "addsi3"
862 [(parallel [(set (match_operand:SI 0 "register_operand" "")
863 (plus:SI (match_operand:SI 1 "register_operand" "")
864 (match_operand:SI 2 "rx_source_operand" "")))
865 (clobber (reg:CC CC_REG))])]
866 ""
867 "
868 operands[0] = rx_maybe_pidify_operand (operands[0], 1);
869 operands[1] = rx_maybe_pidify_operand (operands[1], 1);
870 operands[2] = rx_maybe_pidify_operand (operands[2], 1);
871 "
872 )
873
874 (define_insn "addsi3_internal"
811 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r") 875 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
812 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0") 876 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
813 (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q"))) 877 (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q")))
814 (clobber (reg:CC CC_REG))] 878 (clobber (reg:CC CC_REG))]
815 "" 879 ""
831 [(set_attr "timings" "11,11,11,11,11,11,11,11,11,11,11,11,11,33") 895 [(set_attr "timings" "11,11,11,11,11,11,11,11,11,11,11,11,11,33")
832 (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")] 896 (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
833 ) 897 )
834 898
835 (define_insn "*addsi3_flags" 899 (define_insn "*addsi3_flags"
836 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r") 900 [(set (reg CC_REG)
837 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0") 901 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r,r,r,r,r,0")
838 (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q"))) 902 (match_operand:SI 2 "rx_source_operand" "r,Uint04,NEGint4,Sint08,Sint16,Sint24,i,0,r,Sint08,Sint16,Sint24,i,Q"))
839 (set (reg CC_REG) 903 (const_int 0)))
840 (compare (plus:SI (match_dup 1) (match_dup 2)) 904 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r,r,r,r,r,r")
841 (const_int 0)))] 905 (plus:SI (match_dup 1) (match_dup 2)))]
842 "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)" 906 "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
843 "@ 907 "@
844 add\t%2, %0 908 add\t%2, %0
845 add\t%2, %0 909 add\t%2, %0
846 sub\t%N2, %0 910 sub\t%N2, %0
859 (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")] 923 (set_attr "length" "2,2,2,3,4,5,6,2,3,3,4,5,6,5")]
860 ) 924 )
861 925
862 ;; A helper to expand the above with the CC_MODE filled in. 926 ;; A helper to expand the above with the CC_MODE filled in.
863 (define_expand "addsi3_flags" 927 (define_expand "addsi3_flags"
864 [(parallel [(set (match_operand:SI 0 "register_operand") 928 [(parallel [(set (reg:CC_ZSC CC_REG)
865 (plus:SI (match_operand:SI 1 "register_operand") 929 (compare:CC_ZSC
866 (match_operand:SI 2 "rx_source_operand"))) 930 (plus:SI (match_operand:SI 1 "register_operand")
867 (set (reg:CC_ZSC CC_REG) 931 (match_operand:SI 2 "rx_source_operand"))
868 (compare:CC_ZSC (plus:SI (match_dup 1) (match_dup 2)) 932 (const_int 0)))
869 (const_int 0)))])] 933 (set (match_operand:SI 0 "register_operand")
934 (plus:SI (match_dup 1) (match_dup 2)))])]
870 ) 935 )
871 936
872 (define_insn "adc_internal" 937 (define_insn "adc_internal"
873 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") 938 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
874 (plus:SI 939 (plus:SI
876 (ltu:SI (reg:CC CC_REG) (const_int 0)) 941 (ltu:SI (reg:CC CC_REG) (const_int 0))
877 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")) 942 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0"))
878 (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q"))) 943 (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q")))
879 (clobber (reg:CC CC_REG))] 944 (clobber (reg:CC CC_REG))]
880 "reload_completed" 945 "reload_completed"
881 "adc %2,%0" 946 "adc\t%2, %0"
882 [(set_attr "timings" "11,11,11,11,11,33") 947 [(set_attr "timings" "11,11,11,11,11,33")
883 (set_attr "length" "3,4,5,6,7,6")] 948 (set_attr "length" "3,4,5,6,7,6")]
884 ) 949 )
885 950
886 (define_insn "*adc_flags" 951 (define_insn "*adc_flags"
887 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") 952 [(set (reg CC_REG)
953 (compare
954 (plus:SI
955 (plus:SI
956 (ltu:SI (reg:CC CC_REG) (const_int 0))
957 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0"))
958 (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q"))
959 (const_int 0)))
960 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
888 (plus:SI 961 (plus:SI
889 (plus:SI 962 (plus:SI
890 (ltu:SI (reg:CC CC_REG) (const_int 0)) 963 (ltu:SI (reg:CC CC_REG) (const_int 0))
891 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")) 964 (match_dup 1))
892 (match_operand:SI 2 "rx_source_operand" "r,Sint08,Sint16,Sint24,i,Q"))) 965 (match_dup 2)))]
893 (set (reg CC_REG)
894 (compare
895 (plus:SI
896 (plus:SI
897 (ltu:SI (reg:CC CC_REG) (const_int 0))
898 (match_dup 1))
899 (match_dup 2))
900 (const_int 0)))]
901 "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)" 966 "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
902 "adc %2,%0" 967 "adc\t%2, %0"
903 [(set_attr "timings" "11,11,11,11,11,33") 968 [(set_attr "timings" "11,11,11,11,11,33")
904 (set_attr "length" "3,4,5,6,7,6")] 969 (set_attr "length" "3,4,5,6,7,6")]
970 )
971
972 ;; Peepholes to match:
973 ;; (set (reg A) (reg B))
974 ;; (set (CC) (compare:CC (reg A/reg B) (const_int 0)))
975 ;; and replace them with the addsi3_flags pattern, using an add
976 ;; of zero to copy the register and set the condition code bits.
977 (define_peephole2
978 [(set (match_operand:SI 0 "register_operand")
979 (match_operand:SI 1 "register_operand"))
980 (set (reg:CC CC_REG)
981 (compare:CC (match_dup 0)
982 (const_int 0)))]
983 ""
984 [(parallel [(set (reg:CC_ZSC CC_REG)
985 (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
986 (const_int 0)))
987 (set (match_dup 0)
988 (plus:SI (match_dup 1) (const_int 0))) ])]
989 )
990
991 (define_peephole2
992 [(set (match_operand:SI 0 "register_operand")
993 (match_operand:SI 1 "register_operand"))
994 (set (reg:CC CC_REG)
995 (compare:CC (match_dup 1)
996 (const_int 0)))]
997 ""
998 [(parallel [(set (reg:CC_ZSC CC_REG)
999 (compare:CC_ZSC (plus:SI (match_dup 1) (const_int 0))
1000 (const_int 0)))
1001 (set (match_dup 0)
1002 (plus:SI (match_dup 1) (const_int 0)))])]
905 ) 1003 )
906 1004
907 (define_expand "adddi3" 1005 (define_expand "adddi3"
908 [(set (match_operand:DI 0 "register_operand") 1006 [(set (match_operand:DI 0 "register_operand")
909 (plus:DI (match_operand:DI 1 "register_operand") 1007 (plus:DI (match_operand:DI 1 "register_operand")
922 emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h)); 1020 emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));
923 DONE; 1021 DONE;
924 }) 1022 })
925 1023
926 (define_insn_and_split "adddi3_internal" 1024 (define_insn_and_split "adddi3_internal"
927 [(set (match_operand:SI 0 "register_operand" "=r") 1025 [(set (match_operand:SI 0 "register_operand" "=&r")
928 (plus:SI (match_operand:SI 2 "register_operand" "r") 1026 (plus:SI (match_operand:SI 2 "register_operand" "r")
929 (match_operand:SI 3 "rx_source_operand" "riQ"))) 1027 (match_operand:SI 3 "rx_source_operand" "riQ")))
930 (set (match_operand:SI 1 "register_operand" "=r") 1028 (set (match_operand:SI 1 "register_operand" "=r")
931 (plus:SI 1029 (plus:SI
932 (plus:SI 1030 (plus:SI
1010 [(set_attr "timings" "11,11,11,11,11,11,11,11,33") 1108 [(set_attr "timings" "11,11,11,11,11,11,11,11,33")
1011 (set_attr "length" "2,2,3,4,5,6,2,5,5")] 1109 (set_attr "length" "2,2,3,4,5,6,2,5,5")]
1012 ) 1110 )
1013 1111
1014 (define_insn "*andsi3_flags" 1112 (define_insn "*andsi3_flags"
1015 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") 1113 [(set (reg CC_REG)
1016 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") 1114 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
1017 (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) 1115 (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))
1018 (set (reg CC_REG) 1116 (const_int 0)))
1019 (compare (and:SI (match_dup 1) (match_dup 2)) 1117 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
1020 (const_int 0)))] 1118 (and:SI (match_dup 1) (match_dup 2)))]
1021 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" 1119 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1022 "@ 1120 "@
1023 and\t%2, %0 1121 and\t%2, %0
1024 and\t%2, %0 1122 and\t%2, %0
1025 and\t%2, %0 1123 and\t%2, %0
1127 "min\t%Q2, %0" 1225 "min\t%Q2, %0"
1128 [(set_attr "length" "3,4,5,6,7,6") 1226 [(set_attr "length" "3,4,5,6,7,6")
1129 (set_attr "timings" "11,11,11,11,11,33")] 1227 (set_attr "timings" "11,11,11,11,11,33")]
1130 ) 1228 )
1131 1229
1230 (define_insn "umax<small_int_modes:mode>3_u"
1231 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1232 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
1233 (zero_extend:SI (match_operand:small_int_modes 2 "rx_minmaxex_operand"
1234 "r,Sint08,Sint16,Sint24,i,Q"))))]
1235 ""
1236 "max\t%R2, %0"
1237 [(set_attr "length" "3,4,5,6,7,6")
1238 (set_attr "timings" "11,11,11,11,11,33")]
1239 )
1240
1241 (define_insn "umin<small_int_modes:mode>3_ur"
1242 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1243 (smin:SI (zero_extend:SI (match_operand:small_int_modes 2 "rx_minmaxex_operand"
1244 "r,Sint08,Sint16,Sint24,i,Q"))
1245 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")))]
1246 ""
1247 "min\t%R2, %0"
1248 [(set_attr "length" "3,4,5,6,7,6")
1249 (set_attr "timings" "11,11,11,11,11,33")]
1250 )
1251
1252 (define_insn "umax<small_int_modes:mode>3_ur"
1253 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1254 (smax:SI (zero_extend:SI (match_operand:small_int_modes 2 "rx_minmaxex_operand"
1255 "r,Sint08,Sint16,Sint24,i,Q"))
1256 (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")))]
1257 ""
1258 "max\t%R2, %0"
1259 [(set_attr "length" "3,4,5,6,7,6")
1260 (set_attr "timings" "11,11,11,11,11,33")]
1261 )
1262
1263 (define_expand "umax<small_int_modes:mode>3"
1264 [(set (match_dup 4)
1265 (zero_extend:SI (match_operand:small_int_modes 1 "register_operand" "%0,0,0,0,0,0")))
1266 (set (match_dup 3)
1267 (smax:SI (match_dup 4)
1268 (match_operand:small_int_modes 2 "rx_source_operand"
1269 "r,Sint08,Sint16,Sint24,i,Q")))
1270 (set (match_operand:small_int_modes 0 "register_operand" "=r,r,r,r,r,r")
1271 (match_dup 6))
1272 ]
1273 ""
1274 "operands[3] = gen_reg_rtx (SImode);
1275 operands[4] = gen_reg_rtx (SImode);
1276 operands[5] = gen_reg_rtx (SImode);
1277 operands[6] = gen_rtx_SUBREG (GET_MODE (operands[0]), operands[3],
1278 TARGET_BIG_ENDIAN_DATA ? (GET_MODE (operands[0]) == HImode ? 2 : 3) : 0);
1279 if (GET_CODE (operands[2]) != CONST_INT)
1280 {
1281 emit_move_insn (operands[5], gen_rtx_ZERO_EXTEND (SImode, operands[2]));
1282 operands[2] = operands[5];
1283 }
1284 "
1285 )
1286
1287 (define_expand "umin<small_int_modes:mode>3"
1288 [(set (match_dup 4)
1289 (zero_extend:SI (match_operand:small_int_modes 1 "register_operand" "%0,0,0,0,0,0")))
1290 (set (match_dup 3)
1291 (smin:SI (match_dup 4)
1292 (match_operand:small_int_modes 2 "rx_source_operand"
1293 "r,Sint08,Sint16,Sint24,i,Q")))
1294 (set (match_operand:small_int_modes 0 "register_operand" "=r,r,r,r,r,r")
1295 (match_dup 6))
1296 ]
1297 ""
1298 "operands[3] = gen_reg_rtx (SImode);
1299 operands[4] = gen_reg_rtx (SImode);
1300 operands[5] = gen_reg_rtx (SImode);
1301 operands[6] = gen_rtx_SUBREG (GET_MODE (operands[0]), operands[3],
1302 TARGET_BIG_ENDIAN_DATA ? (GET_MODE (operands[0]) == HImode ? 2 : 3) : 0);
1303 if (GET_CODE (operands[2]) != CONST_INT)
1304 {
1305 emit_move_insn (operands[5], gen_rtx_ZERO_EXTEND (SImode, operands[2]));
1306 operands[2] = operands[5];
1307 }
1308 "
1309 )
1310
1132 (define_insn "mulsi3" 1311 (define_insn "mulsi3"
1133 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") 1312 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
1134 (mult:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r") 1313 (mult:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,0,r,r")
1135 (match_operand:SI 2 "rx_source_operand" 1314 (match_operand:SI 2 "rx_source_operand"
1136 "r,Uint04,Sint08,Sint16,Sint24,i,Q,0,r")))] 1315 "r,Uint04,Sint08,Sint16,Sint24,i,Q,0,r")))]
1161 ) 1340 )
1162 1341
1163 ;; Note that the O and C flags are not set as per a normal compare, 1342 ;; Note that the O and C flags are not set as per a normal compare,
1164 ;; and thus are unusable in that context. 1343 ;; and thus are unusable in that context.
1165 (define_insn "*negsi2_flags" 1344 (define_insn "*negsi2_flags"
1166 [(set (match_operand:SI 0 "register_operand" "=r,r") 1345 [(set (reg CC_REG)
1167 (neg:SI (match_operand:SI 1 "register_operand" "0,r"))) 1346 (compare (neg:SI (match_operand:SI 1 "register_operand" "0,r"))
1168 (set (reg CC_REG) 1347 (const_int 0)))
1169 (compare (neg:SI (match_dup 1)) 1348 (set (match_operand:SI 0 "register_operand" "=r,r")
1170 (const_int 0)))] 1349 (neg:SI (match_dup 1)))]
1171 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" 1350 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1172 "@ 1351 "@
1173 neg\t%0 1352 neg\t%0
1174 neg\t%1, %0" 1353 neg\t%1, %0"
1175 [(set_attr "length" "2,3")] 1354 [(set_attr "length" "2,3")]
1185 not\t%1, %0" 1364 not\t%1, %0"
1186 [(set_attr "length" "2,3")] 1365 [(set_attr "length" "2,3")]
1187 ) 1366 )
1188 1367
1189 (define_insn "*one_cmplsi2_flags" 1368 (define_insn "*one_cmplsi2_flags"
1190 [(set (match_operand:SI 0 "register_operand" "=r,r") 1369 [(set (reg CC_REG)
1191 (not:SI (match_operand:SI 1 "register_operand" "0,r"))) 1370 (compare (not:SI (match_operand:SI 1 "register_operand" "0,r"))
1192 (set (reg CC_REG) 1371 (const_int 0)))
1193 (compare (not:SI (match_dup 1)) 1372 (set (match_operand:SI 0 "register_operand" "=r,r")
1194 (const_int 0)))] 1373 (not:SI (match_dup 1)))]
1195 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" 1374 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1196 "@ 1375 "@
1197 not\t%0 1376 not\t%0
1198 not\t%1, %0" 1377 not\t%1, %0"
1199 [(set_attr "length" "2,3")] 1378 [(set_attr "length" "2,3")]
1218 [(set_attr "timings" "11,11,11,11,11,11,11,11,33") 1397 [(set_attr "timings" "11,11,11,11,11,11,11,11,33")
1219 (set_attr "length" "2,2,3,4,5,6,2,3,5")] 1398 (set_attr "length" "2,2,3,4,5,6,2,3,5")]
1220 ) 1399 )
1221 1400
1222 (define_insn "*iorsi3_flags" 1401 (define_insn "*iorsi3_flags"
1223 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r") 1402 [(set (reg CC_REG)
1224 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0") 1403 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r,0")
1225 (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))) 1404 (match_operand:SI 2 "rx_source_operand" "r,Uint04,Sint08,Sint16,Sint24,i,0,r,Q"))
1226 (set (reg CC_REG) 1405 (const_int 0)))
1227 (compare (ior:SI (match_dup 1) (match_dup 2)) 1406 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r,r")
1228 (const_int 0)))] 1407 (ior:SI (match_dup 1) (match_dup 2)))]
1229 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" 1408 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1230 "@ 1409 "@
1231 or\t%2, %0 1410 or\t%2, %0
1232 or\t%2, %0 1411 or\t%2, %0
1233 or\t%2, %0 1412 or\t%2, %0
1250 "rotl\t%2, %0" 1429 "rotl\t%2, %0"
1251 [(set_attr "length" "3")] 1430 [(set_attr "length" "3")]
1252 ) 1431 )
1253 1432
1254 (define_insn "*rotlsi3_flags" 1433 (define_insn "*rotlsi3_flags"
1255 [(set (match_operand:SI 0 "register_operand" "=r") 1434 [(set (reg CC_REG)
1256 (rotate:SI (match_operand:SI 1 "register_operand" "0") 1435 (compare (rotate:SI (match_operand:SI 1 "register_operand" "0")
1257 (match_operand:SI 2 "rx_shift_operand" "rn"))) 1436 (match_operand:SI 2 "rx_shift_operand" "rn"))
1258 (set (reg CC_REG) 1437 (const_int 0)))
1259 (compare (rotate:SI (match_dup 1) (match_dup 2)) 1438 (set (match_operand:SI 0 "register_operand" "=r")
1260 (const_int 0)))] 1439 (rotate:SI (match_dup 1) (match_dup 2)))]
1261 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" 1440 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1262 "rotl\t%2, %0" 1441 "rotl\t%2, %0"
1263 [(set_attr "length" "3")] 1442 [(set_attr "length" "3")]
1264 ) 1443 )
1265 1444
1272 "rotr\t%2, %0" 1451 "rotr\t%2, %0"
1273 [(set_attr "length" "3")] 1452 [(set_attr "length" "3")]
1274 ) 1453 )
1275 1454
1276 (define_insn "*rotrsi3_flags" 1455 (define_insn "*rotrsi3_flags"
1277 [(set (match_operand:SI 0 "register_operand" "=r") 1456 [(set (reg CC_REG)
1278 (rotatert:SI (match_operand:SI 1 "register_operand" "0") 1457 (compare (rotatert:SI (match_operand:SI 1 "register_operand" "0")
1279 (match_operand:SI 2 "rx_shift_operand" "rn"))) 1458 (match_operand:SI 2 "rx_shift_operand" "rn"))
1280 (set (reg CC_REG) 1459 (const_int 0)))
1281 (compare (rotatert:SI (match_dup 1) (match_dup 2)) 1460 (set (match_operand:SI 0 "register_operand" "=r")
1282 (const_int 0)))] 1461 (rotatert:SI (match_dup 1) (match_dup 2)))]
1283 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" 1462 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1284 "rotr\t%2, %0" 1463 "rotr\t%2, %0"
1285 [(set_attr "length" "3")] 1464 [(set_attr "length" "3")]
1286 ) 1465 )
1287 1466
1297 shar\t%2, %1, %0" 1476 shar\t%2, %1, %0"
1298 [(set_attr "length" "3,2,3")] 1477 [(set_attr "length" "3,2,3")]
1299 ) 1478 )
1300 1479
1301 (define_insn "*ashrsi3_flags" 1480 (define_insn "*ashrsi3_flags"
1302 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 1481 [(set (reg CC_REG)
1303 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r") 1482 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1304 (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) 1483 (match_operand:SI 2 "rx_shift_operand" "r,n,n"))
1305 (set (reg CC_REG) 1484 (const_int 0)))
1306 (compare (ashiftrt:SI (match_dup 1) (match_dup 2)) 1485 (set (match_operand:SI 0 "register_operand" "=r,r,r")
1307 (const_int 0)))] 1486 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
1308 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" 1487 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1309 "@ 1488 "@
1310 shar\t%2, %0 1489 shar\t%2, %0
1311 shar\t%2, %0 1490 shar\t%2, %0
1312 shar\t%2, %1, %0" 1491 shar\t%2, %1, %0"
1325 shlr\t%2, %1, %0" 1504 shlr\t%2, %1, %0"
1326 [(set_attr "length" "3,2,3")] 1505 [(set_attr "length" "3,2,3")]
1327 ) 1506 )
1328 1507
1329 (define_insn "*lshrsi3_flags" 1508 (define_insn "*lshrsi3_flags"
1330 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 1509 [(set (reg CC_REG)
1331 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r") 1510 (compare (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r")
1332 (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) 1511 (match_operand:SI 2 "rx_shift_operand" "r,n,n"))
1333 (set (reg CC_REG) 1512 (const_int 0)))
1334 (compare (lshiftrt:SI (match_dup 1) (match_dup 2)) 1513 (set (match_operand:SI 0 "register_operand" "=r,r,r")
1335 (const_int 0)))] 1514 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
1336 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" 1515 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1337 "@ 1516 "@
1338 shlr\t%2, %0 1517 shlr\t%2, %0
1339 shlr\t%2, %0 1518 shlr\t%2, %0
1340 shlr\t%2, %1, %0" 1519 shlr\t%2, %1, %0"
1353 shll\t%2, %1, %0" 1532 shll\t%2, %1, %0"
1354 [(set_attr "length" "3,2,3")] 1533 [(set_attr "length" "3,2,3")]
1355 ) 1534 )
1356 1535
1357 (define_insn "*ashlsi3_flags" 1536 (define_insn "*ashlsi3_flags"
1358 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 1537 [(set (reg CC_REG)
1359 (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r") 1538 (compare (ashift:SI (match_operand:SI 1 "register_operand" "0,0,r")
1360 (match_operand:SI 2 "rx_shift_operand" "r,n,n"))) 1539 (match_operand:SI 2 "rx_shift_operand" "r,n,n"))
1361 (set (reg CC_REG) 1540 (const_int 0)))
1362 (compare (ashift:SI (match_dup 1) (match_dup 2)) 1541 (set (match_operand:SI 0 "register_operand" "=r,r,r")
1363 (const_int 0)))] 1542 (ashift:SI (match_dup 1) (match_dup 2)))]
1364 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" 1543 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1365 "@ 1544 "@
1366 shll\t%2, %0 1545 shll\t%2, %0
1367 shll\t%2, %0 1546 shll\t%2, %0
1368 shll\t%2, %1, %0" 1547 shll\t%2, %1, %0"
1376 (match_operand:SI 2 "rx_source_operand" "riQ"))) 1555 (match_operand:SI 2 "rx_source_operand" "riQ")))
1377 (clobber (reg:CC CC_REG))] 1556 (clobber (reg:CC CC_REG))]
1378 "" 1557 ""
1379 "#" 1558 "#"
1380 "reload_completed" 1559 "reload_completed"
1381 [(parallel [(set (match_dup 0) 1560 [(parallel [(set (reg:CC_ZSC CC_REG)
1382 (plus:SI (match_dup 1) (match_dup 2)))
1383 (set (reg:CC_ZSC CC_REG)
1384 (compare:CC_ZSC 1561 (compare:CC_ZSC
1385 (plus:SI (match_dup 1) (match_dup 2)) 1562 (plus:SI (match_dup 1) (match_dup 2))
1386 (const_int 0)))]) 1563 (const_int 0)))
1564 (set (match_dup 0)
1565 (plus:SI (match_dup 1) (match_dup 2)))])
1387 (set (match_dup 0) 1566 (set (match_dup 0)
1388 (unspec:SI [(match_dup 0) (reg:CC CC_REG)] 1567 (unspec:SI [(match_dup 0) (reg:CC CC_REG)]
1389 UNSPEC_BUILTIN_SAT))] 1568 UNSPEC_BUILTIN_SAT))]
1390 "" 1569 ""
1391 ) 1570 )
1417 ) 1596 )
1418 1597
1419 ;; Note that the O flag is set as if (compare op1 op2) not for 1598 ;; Note that the O flag is set as if (compare op1 op2) not for
1420 ;; what is described here, (compare op0 0). 1599 ;; what is described here, (compare op0 0).
1421 (define_insn "*subsi3_flags" 1600 (define_insn "*subsi3_flags"
1422 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r") 1601 [(set (reg CC_REG)
1423 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0") 1602 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0")
1424 (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q"))) 1603 (match_operand:SI 2 "rx_source_operand" "r,Uint04,n,r,Q"))
1425 (set (reg CC_REG) 1604 (const_int 0)))
1426 (compare (minus:SI (match_dup 1) (match_dup 2)) 1605 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1427 (const_int 0)))] 1606 (minus:SI (match_dup 1) (match_dup 2)))]
1428 "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)" 1607 "reload_completed && rx_match_ccmode (insn, CC_ZSCmode)"
1429 "@ 1608 "@
1430 sub\t%2, %0 1609 sub\t%2, %0
1431 sub\t%2, %0 1610 sub\t%2, %0
1432 add\t%N2, %0 1611 add\t%N2, %0
1436 (set_attr "length" "2,2,6,3,5")] 1615 (set_attr "length" "2,2,6,3,5")]
1437 ) 1616 )
1438 1617
1439 ;; A helper to expand the above with the CC_MODE filled in. 1618 ;; A helper to expand the above with the CC_MODE filled in.
1440 (define_expand "subsi3_flags" 1619 (define_expand "subsi3_flags"
1441 [(parallel [(set (match_operand:SI 0 "register_operand") 1620 [(parallel [(set (reg:CC_ZSC CC_REG)
1442 (minus:SI (match_operand:SI 1 "register_operand") 1621 (compare:CC_ZSC
1443 (match_operand:SI 2 "rx_source_operand"))) 1622 (minus:SI (match_operand:SI 1 "register_operand")
1444 (set (reg:CC_ZSC CC_REG) 1623 (match_operand:SI 2 "rx_source_operand"))
1445 (compare:CC_ZSC (minus:SI (match_dup 1) (match_dup 2)) 1624 (const_int 0)))
1446 (const_int 0)))])] 1625 (set (match_operand:SI 0 "register_operand")
1626 (minus:SI (match_dup 1) (match_dup 2)))])]
1447 ) 1627 )
1448 1628
1449 (define_insn "sbb_internal" 1629 (define_insn "sbb_internal"
1450 [(set (match_operand:SI 0 "register_operand" "=r,r") 1630 [(set (match_operand:SI 0 "register_operand" "=r,r")
1451 (minus:SI 1631 (minus:SI
1459 [(set_attr "timings" "11,33") 1639 [(set_attr "timings" "11,33")
1460 (set_attr "length" "3,6")] 1640 (set_attr "length" "3,6")]
1461 ) 1641 )
1462 1642
1463 (define_insn "*sbb_flags" 1643 (define_insn "*sbb_flags"
1464 [(set (match_operand:SI 0 "register_operand" "=r,r") 1644 [(set (reg CC_REG)
1465 (minus:SI
1466 (minus:SI
1467 (match_operand:SI 1 "register_operand" " 0,0")
1468 (match_operand:SI 2 "rx_compare_operand" " r,Q"))
1469 (geu:SI (reg:CC CC_REG) (const_int 0))))
1470 (set (reg CC_REG)
1471 (compare 1645 (compare
1472 (minus:SI 1646 (minus:SI
1473 (minus:SI (match_dup 1) (match_dup 2)) 1647 (minus:SI
1648 (match_operand:SI 1 "register_operand" " 0,0")
1649 (match_operand:SI 2 "rx_compare_operand" " r,Q"))
1474 (geu:SI (reg:CC CC_REG) (const_int 0))) 1650 (geu:SI (reg:CC CC_REG) (const_int 0)))
1475 (const_int 0)))] 1651 (const_int 0)))
1652 (set (match_operand:SI 0 "register_operand" "=r,r")
1653 (minus:SI
1654 (minus:SI (match_dup 1) (match_dup 2))
1655 (geu:SI (reg:CC CC_REG) (const_int 0))))]
1476 "reload_completed" 1656 "reload_completed"
1477 "sbb\t%2, %0" 1657 "sbb\t%2, %0"
1478 [(set_attr "timings" "11,33") 1658 [(set_attr "timings" "11,33")
1479 (set_attr "length" "3,6")] 1659 (set_attr "length" "3,6")]
1480 ) 1660 )
1481 1661
1482 (define_expand "subdi3" 1662 (define_expand "subdi3"
1483 [(set (match_operand:DI 0 "register_operand") 1663 [(set (match_operand:DI 0 "register_operand")
1484 (minus:DI (match_operand:DI 1 "register_operand") 1664 (minus:DI (match_operand:DI 1 "register_operand")
1485 (match_operand:DI 2 "rx_compare_operand")))] 1665 (match_operand:DI 2 "register_operand")))]
1486 "" 1666 ""
1487 { 1667 {
1488 rtx op0l, op0h, op1l, op1h, op2l, op2h; 1668 rtx op0l, op0h, op1l, op1h, op2l, op2h;
1489 1669
1490 op0l = gen_lowpart (SImode, operands[0]); 1670 op0l = gen_lowpart (SImode, operands[0]);
1530 [(set_attr "timings" "11,11,11,11,11,33") 1710 [(set_attr "timings" "11,11,11,11,11,33")
1531 (set_attr "length" "3,4,5,6,7,6")] 1711 (set_attr "length" "3,4,5,6,7,6")]
1532 ) 1712 )
1533 1713
1534 (define_insn "*xorsi3_flags" 1714 (define_insn "*xorsi3_flags"
1535 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r") 1715 [(set (reg CC_REG)
1536 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0") 1716 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0")
1537 (match_operand:SI 2 "rx_source_operand" 1717 (match_operand:SI 2 "rx_source_operand"
1538 "r,Sint08,Sint16,Sint24,i,Q"))) 1718 "r,Sint08,Sint16,Sint24,i,Q"))
1539 (set (reg CC_REG) 1719 (const_int 0)))
1540 (compare (xor:SI (match_dup 1) (match_dup 2)) 1720 (set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
1541 (const_int 0)))] 1721 (xor:SI (match_dup 1) (match_dup 2)))]
1542 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)" 1722 "reload_completed && rx_match_ccmode (insn, CC_ZSmode)"
1543 "xor\t%Q2, %0" 1723 "xor\t%Q2, %0"
1544 [(set_attr "timings" "11,11,11,11,11,33") 1724 [(set_attr "timings" "11,11,11,11,11,33")
1545 (set_attr "length" "3,4,5,6,7,6")] 1725 (set_attr "length" "3,4,5,6,7,6")]
1726 )
1727
1728 ;; A set of peepholes to catch extending loads followed by arithmetic operations.
1729 ;; We use iterators where possible to reduce the amount of typing and hence the
1730 ;; possibilities for typos.
1731
1732 (define_code_iterator extend_types [(zero_extend "") (sign_extend "")])
1733 (define_code_attr letter [(zero_extend "R") (sign_extend "Q")])
1734
1735 (define_code_iterator memex_commutative [(plus "") (and "") (ior "") (xor "")])
1736 (define_code_iterator memex_noncomm [(div "") (udiv "") (minus "")])
1737 (define_code_iterator memex_nocc [(smax "") (smin "") (mult "")])
1738
1739 (define_code_attr op [(plus "add") (and "and") (div "div") (udiv "divu") (smax "max") (smin "min") (mult "mul") (ior "or") (minus "sub") (xor "xor")])
1740
1741 (define_peephole2
1742 [(set (match_operand:SI 0 "register_operand")
1743 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
1744 (parallel [(set (match_operand:SI 2 "register_operand")
1745 (memex_commutative:SI (match_dup 0)
1746 (match_dup 2)))
1747 (clobber (reg:CC CC_REG))])]
1748 "peep2_regno_dead_p (2, REGNO (operands[0])) && (optimize < 3 || optimize_size)"
1749 [(parallel [(set (match_dup 2)
1750 (memex_commutative:SI (match_dup 2)
1751 (extend_types:SI (match_dup 1))))
1752 (clobber (reg:CC CC_REG))])]
1753 )
1754
1755 (define_peephole2
1756 [(set (match_operand:SI 0 "register_operand")
1757 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
1758 (parallel [(set (match_operand:SI 2 "register_operand")
1759 (memex_commutative:SI (match_dup 2)
1760 (match_dup 0)))
1761 (clobber (reg:CC CC_REG))])]
1762 "peep2_regno_dead_p (2, REGNO (operands[0])) && (optimize < 3 || optimize_size)"
1763 [(parallel [(set (match_dup 2)
1764 (memex_commutative:SI (match_dup 2)
1765 (extend_types:SI (match_dup 1))))
1766 (clobber (reg:CC CC_REG))])]
1767 )
1768
1769 (define_peephole2
1770 [(set (match_operand:SI 0 "register_operand")
1771 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
1772 (parallel [(set (match_operand:SI 2 "register_operand")
1773 (memex_noncomm:SI (match_dup 2)
1774 (match_dup 0)))
1775 (clobber (reg:CC CC_REG))])]
1776 "peep2_regno_dead_p (2, REGNO (operands[0])) && (optimize < 3 || optimize_size)"
1777 [(parallel [(set (match_dup 2)
1778 (memex_noncomm:SI (match_dup 2)
1779 (extend_types:SI (match_dup 1))))
1780 (clobber (reg:CC CC_REG))])]
1781 )
1782
1783 (define_peephole2
1784 [(set (match_operand:SI 0 "register_operand")
1785 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
1786 (set (match_operand:SI 2 "register_operand")
1787 (memex_nocc:SI (match_dup 0)
1788 (match_dup 2)))]
1789 "peep2_regno_dead_p (2, REGNO (operands[0])) && (optimize < 3 || optimize_size)"
1790 [(set (match_dup 2)
1791 (memex_nocc:SI (match_dup 2)
1792 (extend_types:SI (match_dup 1))))]
1793 )
1794
1795 (define_peephole2
1796 [(set (match_operand:SI 0 "register_operand")
1797 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
1798 (set (match_operand:SI 2 "register_operand")
1799 (memex_nocc:SI (match_dup 2)
1800 (match_dup 0)))]
1801 "peep2_regno_dead_p (2, REGNO (operands[0])) && (optimize < 3 || optimize_size)"
1802 [(set (match_dup 2)
1803 (memex_nocc:SI (match_dup 2)
1804 (extend_types:SI (match_dup 1))))]
1805 )
1806
1807 (define_insn "<memex_commutative:code>si3_<extend_types:code><small_int_modes:mode>"
1808 [(set (match_operand:SI 0 "register_operand" "=r")
1809 (memex_commutative:SI (match_operand:SI 1 "register_operand" "%0")
1810 (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))
1811 (clobber (reg:CC CC_REG))]
1812 "(optimize < 3 || optimize_size)"
1813 "<memex_commutative:op>\t%<extend_types:letter>2, %0"
1814 [(set_attr "timings" "33")
1815 (set_attr "length" "5")] ;; This length is corrected in rx_adjust_insn_length
1816 )
1817
1818 (define_insn "<memex_noncomm:code>si3_<extend_types:code><small_int_modes:mode>"
1819 [(set (match_operand:SI 0 "register_operand" "=r")
1820 (memex_noncomm:SI (match_operand:SI 1 "register_operand" "0")
1821 (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))
1822 (clobber (reg:CC CC_REG))]
1823 "(optimize < 3 || optimize_size)"
1824 "<memex_noncomm:op>\t%<extend_types:letter>2, %0"
1825 [(set_attr "timings" "33")
1826 (set_attr "length" "5")] ;; This length is corrected in rx_adjust_insn_length
1827 )
1828
1829 (define_insn "<memex_nocc:code>si3_<extend_types:code><small_int_modes:mode>"
1830 [(set (match_operand:SI 0 "register_operand" "=r")
1831 (memex_nocc:SI (match_operand:SI 1 "register_operand" "%0")
1832 (extend_types:SI (match_operand:small_int_modes 2 "rx_restricted_mem_operand" "Q"))))]
1833 "(optimize < 3 || optimize_size)"
1834 "<memex_nocc:op>\t%<extend_types:letter>2, %0"
1835 [(set_attr "timings" "33")
1836 (set_attr "length" "5")] ;; This length is corrected in rx_adjust_insn_length
1837 )
1838
1839 (define_peephole2
1840 [(set (match_operand:SI 0 "register_operand")
1841 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand")))
1842 (set (reg:CC CC_REG)
1843 (compare:CC (match_operand:SI 2 "register_operand")
1844 (match_dup 0)))]
1845 "peep2_regno_dead_p (2, REGNO (operands[0])) && (optimize < 3 || optimize_size)"
1846 [(set (reg:CC CC_REG)
1847 (compare:CC (match_dup 2)
1848 (extend_types:SI (match_dup 1))))]
1849 )
1850
1851 ;; Convert:
1852 ;; (set (reg1) (sign_extend (mem))
1853 ;; (set (reg2) (zero_extend (reg1))
1854 ;; into
1855 ;; (set (reg2) (zero_extend (mem)))
1856 (define_peephole2
1857 [(set (match_operand:SI 0 "register_operand")
1858 (sign_extend:SI (match_operand:small_int_modes 1 "memory_operand")))
1859 (set (match_operand:SI 2 "register_operand")
1860 (zero_extend:SI (match_operand:small_int_modes 3 "register_operand")))]
1861 "REGNO (operands[0]) == REGNO (operands[3])
1862 && (REGNO (operands[0]) == REGNO (operands[2])
1863 || peep2_regno_dead_p (2, REGNO (operands[0])))"
1864 [(set (match_dup 2)
1865 (zero_extend:SI (match_dup 1)))]
1866 )
1867
1868 ;; Remove the redundant sign extension from:
1869 ;; (set (reg) (extend (mem)))
1870 ;; (set (reg) (extend (reg)))
1871 (define_peephole2
1872 [(set (match_operand:SI 0 "register_operand")
1873 (extend_types:SI (match_operand:small_int_modes 1 "memory_operand")))
1874 (set (match_dup 0)
1875 (extend_types:SI (match_operand:small_int_modes 2 "register_operand")))]
1876 "REGNO (operands[0]) == REGNO (operands[2])"
1877 [(set (match_dup 0) (extend_types:SI (match_dup 1)))]
1878 )
1879
1880 (define_insn "comparesi3_<extend_types:code><small_int_modes:mode>"
1881 [(set (reg:CC CC_REG)
1882 (compare:CC (match_operand:SI 0 "register_operand" "r")
1883 (extend_types:SI (match_operand:small_int_modes 1 "rx_restricted_mem_operand" "Q"))))]
1884 "(optimize < 3 || optimize_size)"
1885 "cmp\t%<extend_types:letter>1, %0"
1886 [(set_attr "timings" "33")
1887 (set_attr "length" "5")] ;; This length is corrected in rx_adjust_insn_length
1546 ) 1888 )
1547 1889
1548 ;; Floating Point Instructions 1890 ;; Floating Point Instructions
1549 1891
1550 (define_insn "addsf3" 1892 (define_insn "addsf3"
1634 "bset\t%1, %0" 1976 "bset\t%1, %0"
1635 [(set_attr "length" "3")] 1977 [(set_attr "length" "3")]
1636 ) 1978 )
1637 1979
1638 (define_insn "*bitset_in_memory" 1980 (define_insn "*bitset_in_memory"
1639 [(set (match_operand:QI 0 "memory_operand" "+Q") 1981 [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
1640 (ior:QI (ashift:QI (const_int 1) 1982 (ior:QI (ashift:QI (const_int 1)
1641 (match_operand:QI 1 "nonmemory_operand" "ri")) 1983 (match_operand:QI 1 "nonmemory_operand" "ri"))
1642 (match_dup 0)))] 1984 (match_dup 0)))]
1643 "" 1985 ""
1644 "bset\t%1, %0.B" 1986 "bset\t%1, %0.B"
1655 "bnot\t%1, %0" 1997 "bnot\t%1, %0"
1656 [(set_attr "length" "3")] 1998 [(set_attr "length" "3")]
1657 ) 1999 )
1658 2000
1659 (define_insn "*bitinvert_in_memory" 2001 (define_insn "*bitinvert_in_memory"
1660 [(set (match_operand:QI 0 "memory_operand" "+Q") 2002 [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
1661 (xor:QI (ashift:QI (const_int 1) 2003 (xor:QI (ashift:QI (const_int 1)
1662 (match_operand:QI 1 "nonmemory_operand" "ri")) 2004 (match_operand:QI 1 "nonmemory_operand" "ri"))
1663 (match_dup 0)))] 2005 (match_dup 0)))]
1664 "" 2006 ""
1665 "bnot\t%1, %0.B" 2007 "bnot\t%1, %0.B"
1678 "bclr\t%1, %0" 2020 "bclr\t%1, %0"
1679 [(set_attr "length" "3")] 2021 [(set_attr "length" "3")]
1680 ) 2022 )
1681 2023
1682 (define_insn "*bitclr_in_memory" 2024 (define_insn "*bitclr_in_memory"
1683 [(set (match_operand:QI 0 "memory_operand" "+Q") 2025 [(set (match_operand:QI 0 "rx_restricted_mem_operand" "+Q")
1684 (and:QI (not:QI 2026 (and:QI (not:QI
1685 (ashift:QI 2027 (ashift:QI
1686 (const_int 1) 2028 (const_int 1)
1687 (match_operand:QI 1 "nonmemory_operand" "ri"))) 2029 (match_operand:QI 1 "nonmemory_operand" "ri")))
1688 (match_dup 0)))] 2030 (match_dup 0)))]
1725 2067
1726 /* Emit tst #1, op2. */ 2068 /* Emit tst #1, op2. */
1727 flags = gen_rtx_REG (CC_ZSmode, CC_REG); 2069 flags = gen_rtx_REG (CC_ZSmode, CC_REG);
1728 x = gen_rtx_AND (SImode, operands[2], const1_rtx); 2070 x = gen_rtx_AND (SImode, operands[2], const1_rtx);
1729 x = gen_rtx_COMPARE (CC_ZSmode, x, const0_rtx); 2071 x = gen_rtx_COMPARE (CC_ZSmode, x, const0_rtx);
1730 x = gen_rtx_SET (VOIDmode, flags, x); 2072 x = gen_rtx_SET (flags, x);
1731 emit_insn (x); 2073 emit_insn (x);
1732 2074
1733 /* Emit bmne. */ 2075 /* Emit bmne. */
1734 operands[3] = gen_rtx_NE (SImode, flags, const0_rtx); 2076 operands[3] = gen_rtx_NE (SImode, flags, const0_rtx);
1735 }) 2077 })
1751 { 2093 {
1752 rtx flags, x; 2094 rtx flags, x;
1753 2095
1754 flags = gen_rtx_REG (CCmode, CC_REG); 2096 flags = gen_rtx_REG (CCmode, CC_REG);
1755 x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]); 2097 x = gen_rtx_COMPARE (CCmode, operands[2], operands[3]);
1756 x = gen_rtx_SET (VOIDmode, flags, x); 2098 x = gen_rtx_SET (flags, x);
1757 emit_insn (x); 2099 emit_insn (x);
1758 2100
1759 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode, 2101 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1760 flags, const0_rtx); 2102 flags, const0_rtx);
1761 }) 2103 })
1813 } 2155 }
1814 else 2156 else
1815 FAIL; 2157 FAIL;
1816 }) 2158 })
1817 2159
1818 ;; Atomic exchange operation. 2160 ;; Atomic operations.
2161
2162 (define_code_iterator FETCHOP [plus minus ior xor and])
2163 (define_code_iterator FETCHOP_NO_MINUS [plus ior xor and])
2164
2165 (define_code_attr fetchop_name
2166 [(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
2167
2168 (define_code_attr fetchop_name2
2169 [(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
2170
2171 (define_mode_iterator QIHI [QI HI])
1819 2172
1820 (define_insn "sync_lock_test_and_setsi" 2173 (define_insn "sync_lock_test_and_setsi"
1821 [(set (match_operand:SI 0 "register_operand" "=r,r") 2174 [(set (match_operand:SI 0 "register_operand" "=r,r")
1822 (match_operand:SI 1 "rx_compare_operand" "=r,Q")) 2175 (match_operand:SI 1 "rx_compare_operand" "=r,Q"))
1823 (set (match_dup 1) 2176 (set (match_dup 1)
1825 "" 2178 ""
1826 "xchg\t%1, %0" 2179 "xchg\t%1, %0"
1827 [(set_attr "length" "3,6") 2180 [(set_attr "length" "3,6")
1828 (set_attr "timings" "22")] 2181 (set_attr "timings" "22")]
1829 ) 2182 )
2183
2184 (define_expand "atomic_exchange<mode>"
2185 [(match_operand:QIHI 0 "register_operand") ;; oldval output
2186 (match_operand:QIHI 1 "rx_restricted_mem_operand") ;; memory
2187 (match_operand:QIHI 2 "register_operand") ;; newval input
2188 (match_operand:QIHI 3 "const_int_operand")] ;; memory model
2189 ""
2190 {
2191 emit_insn (gen_xchg_mem<mode> (operands[0], operands[1], operands[2]));
2192 DONE;
2193 })
2194
2195 (define_expand "atomic_exchangesi"
2196 [(match_operand:SI 0 "register_operand") ;; oldval output
2197 (match_operand:SI 1 "rx_restricted_mem_operand") ;; memory
2198 (match_operand:SI 2 "register_operand") ;; newval input
2199 (match_operand:SI 3 "const_int_operand")] ;; memory model
2200 ""
2201 {
2202 emit_insn (gen_sync_lock_test_and_setsi (operands[0], operands[1],
2203 operands[2]));
2204 DONE;
2205 })
2206
2207 (define_insn "xchg_mem<mode>"
2208 [(set (match_operand:QIHI 0 "register_operand" "=r")
2209 (match_operand:QIHI 1 "rx_compare_operand" "=Q"))
2210 (set (match_dup 1)
2211 (match_operand:QIHI 2 "register_operand" "0"))]
2212 ""
2213 "xchg\t%1, %0"
2214 [(set_attr "length" "6")
2215 (set_attr "timings" "22")]
2216 )
2217
2218 ;; read - modify - write - return old value
2219 (define_expand "atomic_fetch_<fetchop_name>si"
2220 [(set (match_operand:SI 0 "register_operand")
2221 (match_operand:SI 1 "memory_operand"))
2222 (set (match_dup 1)
2223 (FETCHOP:SI (match_dup 1) (match_operand:SI 2 "rx_source_operand")))
2224 (match_operand:SI 3 "const_int_operand")] ;; memory model
2225 ""
2226 {
2227 {
2228 rx_atomic_sequence seq (current_function_decl);
2229
2230 emit_move_insn (operands[0], operands[1]);
2231
2232 rtx tmp = gen_reg_rtx (SImode);
2233 emit_insn (gen_<fetchop_name2>si3 (tmp, operands[0], operands[2]));
2234
2235 emit_move_insn (operands[1], tmp);
2236 }
2237 DONE;
2238 })
2239
2240 (define_expand "atomic_fetch_nandsi"
2241 [(set (match_operand:SI 0 "register_operand")
2242 (match_operand:SI 1 "memory_operand"))
2243 (set (match_dup 1)
2244 (not:SI (and:SI (match_dup 1)
2245 (match_operand:SI 2 "rx_source_operand"))))
2246 (match_operand:SI 3 "const_int_operand")] ;; memory model
2247 ""
2248 {
2249 {
2250 rx_atomic_sequence seq (current_function_decl);
2251
2252 emit_move_insn (operands[0], operands[1]);
2253
2254 rtx tmp = gen_reg_rtx (SImode);
2255 emit_insn (gen_andsi3 (tmp, operands[0], operands[2]));
2256 emit_insn (gen_one_cmplsi2 (tmp, tmp));
2257
2258 emit_move_insn (operands[1], tmp);
2259 }
2260 DONE;
2261 })
2262
2263 ;; read - modify - write - return new value
2264 ;; Because subtraction is not commutative we need to specify a different
2265 ;; set of patterns for it.
2266 (define_expand "atomic_<fetchop_name>_fetchsi"
2267 [(set (match_operand:SI 0 "register_operand")
2268 (FETCHOP_NO_MINUS:SI (match_operand:SI 1 "rx_restricted_mem_operand")
2269 (match_operand:SI 2 "register_operand")))
2270 (set (match_dup 1)
2271 (FETCHOP_NO_MINUS:SI (match_dup 1) (match_dup 2)))
2272 (match_operand:SI 3 "const_int_operand")] ;; memory model
2273 ""
2274 {
2275 {
2276 rx_atomic_sequence seq (current_function_decl);
2277
2278 emit_move_insn (operands[0], operands[2]);
2279 emit_insn (gen_<fetchop_name2>si3 (operands[0], operands[0], operands[1]));
2280 emit_move_insn (operands[1], operands[0]);
2281 }
2282 DONE;
2283 })
2284
2285 (define_expand "atomic_sub_fetchsi"
2286 [(set (match_operand:SI 0 "register_operand")
2287 (minus:SI (match_operand:SI 1 "rx_restricted_mem_operand")
2288 (match_operand:SI 2 "rx_source_operand")))
2289 (set (match_dup 1)
2290 (minus:SI (match_dup 1) (match_dup 2)))
2291 (match_operand:SI 3 "const_int_operand")] ;; memory model
2292 ""
2293 {
2294 {
2295 rx_atomic_sequence seq (current_function_decl);
2296
2297 emit_move_insn (operands[0], operands[1]);
2298 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
2299 emit_move_insn (operands[1], operands[0]);
2300 }
2301 DONE;
2302 })
2303
2304 (define_expand "atomic_nand_fetchsi"
2305 [(set (match_operand:SI 0 "register_operand")
2306 (not:SI (and:SI (match_operand:SI 1 "rx_restricted_mem_operand")
2307 (match_operand:SI 2 "register_operand"))))
2308 (set (match_dup 1)
2309 (not:SI (and:SI (match_dup 1) (match_dup 2))))
2310 (match_operand:SI 3 "const_int_operand")] ;; memory model
2311 ""
2312 {
2313 {
2314 rx_atomic_sequence seq (current_function_decl);
2315
2316 emit_move_insn (operands[0], operands[2]);
2317 emit_insn (gen_andsi3 (operands[0], operands[0], operands[1]));
2318 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
2319 emit_move_insn (operands[1], operands[0]);
2320 }
2321 DONE;
2322 });
2323
1830 2324
1831 ;; Block move functions. 2325 ;; Block move functions.
1832 2326
1833 (define_expand "movstr" 2327 (define_expand "movstr"
1834 [(set (match_operand:BLK 1 "memory_operand") ;; Dest 2328 [(set (match_operand:BLK 1 "memory_operand") ;; Dest
1835 (match_operand:BLK 2 "memory_operand")) ;; Source 2329 (match_operand:BLK 2 "memory_operand")) ;; Source
1836 (use (match_operand:SI 0 "register_operand")) ;; Updated Dest 2330 (use (match_operand:SI 0 "register_operand")) ;; Updated Dest
1837 ] 2331 ]
1838 "" 2332 "rx_allow_string_insns"
1839 { 2333 {
1840 rtx addr1 = gen_rtx_REG (SImode, 1); 2334 rtx addr1 = gen_rtx_REG (SImode, 1);
1841 rtx addr2 = gen_rtx_REG (SImode, 2); 2335 rtx addr2 = gen_rtx_REG (SImode, 2);
1842 rtx len = gen_rtx_REG (SImode, 3); 2336 rtx len = gen_rtx_REG (SImode, 3);
1843 rtx dest_copy = gen_reg_rtx (SImode); 2337 rtx dest_copy = gen_reg_rtx (SImode);
1860 (mem:BLK (reg:SI 2))) 2354 (mem:BLK (reg:SI 2)))
1861 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVSTR) 2355 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVSTR)
1862 (clobber (reg:SI 1)) 2356 (clobber (reg:SI 1))
1863 (clobber (reg:SI 2)) 2357 (clobber (reg:SI 2))
1864 (clobber (reg:SI 3))] 2358 (clobber (reg:SI 3))]
1865 "" 2359 "rx_allow_string_insns"
1866 "smovu" 2360 "smovu"
1867 [(set_attr "length" "2") 2361 [(set_attr "length" "2")
1868 (set_attr "timings" "1111")] ;; The timing is a guesstimate. 2362 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
1869 ) 2363 )
1870 2364
1875 (clobber (reg:SI 1)) 2369 (clobber (reg:SI 1))
1876 (clobber (reg:SI 2)) 2370 (clobber (reg:SI 2))
1877 (clobber (reg:SI 3)) 2371 (clobber (reg:SI 3))
1878 (clobber (reg:CC CC_REG)) 2372 (clobber (reg:CC CC_REG))
1879 ] 2373 ]
1880 "" 2374 "rx_allow_string_insns"
1881 "mov\t%1, r1\n\tmov\t#0, r2\n\tsuntil.b\n\tmov\tr1, %0\n\tsub\t#1, %0" 2375 "mov\t%1, r1\n\tmov\t#0, r2\n\tsuntil.b\n\tmov\tr1, %0\n\tsub\t#1, %0"
1882 [(set_attr "length" "10") 2376 [(set_attr "length" "10")
1883 (set_attr "timings" "1111")] ;; The timing is a guesstimate. 2377 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
1884 ) 2378 )
1885 2379
1889 (match_operand:BLK 1 "memory_operand")) ;; Source 2383 (match_operand:BLK 1 "memory_operand")) ;; Source
1890 (use (match_operand:SI 2 "register_operand")) ;; Length in bytes 2384 (use (match_operand:SI 2 "register_operand")) ;; Length in bytes
1891 (match_operand 3 "immediate_operand") ;; Align 2385 (match_operand 3 "immediate_operand") ;; Align
1892 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVMEM)] 2386 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVMEM)]
1893 )] 2387 )]
1894 "" 2388 "rx_allow_string_insns"
1895 { 2389 {
1896 rtx addr1 = gen_rtx_REG (SImode, 1); 2390 rtx addr1 = gen_rtx_REG (SImode, 1);
1897 rtx addr2 = gen_rtx_REG (SImode, 2); 2391 rtx addr2 = gen_rtx_REG (SImode, 2);
1898 rtx len = gen_rtx_REG (SImode, 3); 2392 rtx len = gen_rtx_REG (SImode, 3);
1899 2393
1931 (use (reg:SI 3)) 2425 (use (reg:SI 3))
1932 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVMEM) 2426 (unspec_volatile:BLK [(reg:SI 1) (reg:SI 2) (reg:SI 3)] UNSPEC_MOVMEM)
1933 (clobber (reg:SI 1)) 2427 (clobber (reg:SI 1))
1934 (clobber (reg:SI 2)) 2428 (clobber (reg:SI 2))
1935 (clobber (reg:SI 3))] 2429 (clobber (reg:SI 3))]
1936 "" 2430 "rx_allow_string_insns"
1937 "smovf" 2431 "smovf"
1938 [(set_attr "length" "2") 2432 [(set_attr "length" "2")
1939 (set_attr "timings" "1111")] ;; The timing is a guesstimate. 2433 (set_attr "timings" "1111")] ;; The timing is a guesstimate.
1940 ) 2434 )
1941 2435
1975 (unspec_volatile:SI [(match_operand:BLK 1 "memory_operand") ;; String1 2469 (unspec_volatile:SI [(match_operand:BLK 1 "memory_operand") ;; String1
1976 (match_operand:BLK 2 "memory_operand")] ;; String2 2470 (match_operand:BLK 2 "memory_operand")] ;; String2
1977 UNSPEC_CMPSTRN)) 2471 UNSPEC_CMPSTRN))
1978 (use (match_operand:SI 3 "register_operand")) ;; Max Length 2472 (use (match_operand:SI 3 "register_operand")) ;; Max Length
1979 (match_operand:SI 4 "immediate_operand")] ;; Known Align 2473 (match_operand:SI 4 "immediate_operand")] ;; Known Align
1980 "" 2474 "rx_allow_string_insns"
1981 { 2475 {
1982 rtx str1 = gen_rtx_REG (SImode, 1); 2476 rtx str1 = gen_rtx_REG (SImode, 1);
1983 rtx str2 = gen_rtx_REG (SImode, 2); 2477 rtx str2 = gen_rtx_REG (SImode, 2);
1984 rtx len = gen_rtx_REG (SImode, 3); 2478 rtx len = gen_rtx_REG (SImode, 3);
1985 2479
1986 emit_move_insn (str1, force_operand (XEXP (operands[1], 0), NULL_RTX)); 2480 emit_move_insn (str1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1987 emit_move_insn (str2, force_operand (XEXP (operands[2], 0), NULL_RTX)); 2481 emit_move_insn (str2, force_operand (XEXP (operands[2], 0), NULL_RTX));
1988 emit_move_insn (len, force_operand (operands[3], NULL_RTX)); 2482 emit_move_insn (len, operands[3]);
1989 2483
1990 emit_insn (gen_rx_cmpstrn (operands[0], operands[1], operands[2])); 2484 emit_insn (gen_rx_cmpstrn (operands[0], operands[1], operands[2]));
1991 DONE; 2485 DONE;
1992 } 2486 }
1993 ) 2487 )
1996 [(set (match_operand:SI 0 "register_operand") ;; Result 2490 [(set (match_operand:SI 0 "register_operand") ;; Result
1997 (unspec_volatile:SI [(match_operand:BLK 1 "memory_operand") ;; String1 2491 (unspec_volatile:SI [(match_operand:BLK 1 "memory_operand") ;; String1
1998 (match_operand:BLK 2 "memory_operand")] ;; String2 2492 (match_operand:BLK 2 "memory_operand")] ;; String2
1999 UNSPEC_CMPSTRN)) 2493 UNSPEC_CMPSTRN))
2000 (match_operand:SI 3 "immediate_operand")] ;; Known Align 2494 (match_operand:SI 3 "immediate_operand")] ;; Known Align
2001 "" 2495 "rx_allow_string_insns"
2002 { 2496 {
2003 rtx str1 = gen_rtx_REG (SImode, 1); 2497 rtx str1 = gen_rtx_REG (SImode, 1);
2004 rtx str2 = gen_rtx_REG (SImode, 2); 2498 rtx str2 = gen_rtx_REG (SImode, 2);
2005 rtx len = gen_rtx_REG (SImode, 3); 2499 rtx len = gen_rtx_REG (SImode, 3);
2006 2500
2021 (use (match_operand:BLK 2 "memory_operand" "m")) 2515 (use (match_operand:BLK 2 "memory_operand" "m"))
2022 (clobber (reg:SI 1)) 2516 (clobber (reg:SI 1))
2023 (clobber (reg:SI 2)) 2517 (clobber (reg:SI 2))
2024 (clobber (reg:SI 3)) 2518 (clobber (reg:SI 3))
2025 (clobber (reg:CC CC_REG))] 2519 (clobber (reg:CC CC_REG))]
2026 "" 2520 "rx_allow_string_insns"
2027 "scmpu ; Perform the string comparison 2521 "scmpu ; Perform the string comparison
2028 mov #-1, %0 ; Set up -1 result (which cannot be created 2522 mov #-1, %0 ; Set up -1 result (which cannot be created
2029 ; by the SC insn) 2523 ; by the SC insn)
2030 bnc ?+ ; If Carry is not set skip over 2524 bnc ?+ ; If Carry is not set skip over
2031 scne.L %0 ; Set result based on Z flag 2525 scne.L %0 ; Set result based on Z flag
2139 (reg:SI 4) (reg:SI 5) (reg:SI 6)] 2633 (reg:SI 4) (reg:SI 5) (reg:SI 6)]
2140 UNSPEC_BUILTIN_RMPA) 2634 UNSPEC_BUILTIN_RMPA)
2141 (clobber (reg:SI 1)) 2635 (clobber (reg:SI 1))
2142 (clobber (reg:SI 2)) 2636 (clobber (reg:SI 2))
2143 (clobber (reg:SI 3))] 2637 (clobber (reg:SI 3))]
2144 "" 2638 "rx_allow_string_insns"
2145 "rmpa" 2639 "rmpa"
2146 [(set_attr "length" "2") 2640 [(set_attr "length" "2")
2147 (set_attr "timings" "1010")] 2641 (set_attr "timings" "1010")]
2148 ) 2642 )
2149 2643
2202 "mvfc\t%C1, %0" 2696 "mvfc\t%C1, %0"
2203 [(set_attr "length" "3")] 2697 [(set_attr "length" "3")]
2204 ) 2698 )
2205 2699
2206 ;; Move to control register 2700 ;; Move to control register
2701 ;; This insn can be used in atomic sequences to restore the previous PSW
2702 ;; and re-enable interrupts. Because of that it always clobbers the CC_REG.
2207 (define_insn "mvtc" 2703 (define_insn "mvtc"
2208 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i,i") 2704 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i,i")
2209 (match_operand:SI 1 "nonmemory_operand" "r,i")] 2705 (match_operand:SI 1 "nonmemory_operand" "r,i")]
2210 UNSPEC_BUILTIN_MVTC)] 2706 UNSPEC_BUILTIN_MVTC)
2707 (clobber (reg:CC CC_REG))]
2211 "" 2708 ""
2212 "mvtc\t%1, %C0" 2709 "mvtc\t%1, %C0"
2213 [(set_attr "length" "3,7")] 2710 [(set_attr "length" "3,7")]
2214 ;; Ignore possible clobbering of the comparison flags in the
2215 ;; PSW register. This is a cc0 target so any cc0 setting
2216 ;; instruction will always be paired with a cc0 user, without
2217 ;; the possibility of this instruction being placed in between
2218 ;; them.
2219 ) 2711 )
2220 2712
2221 ;; Move to interrupt priority level 2713 ;; Move to interrupt priority level
2222 (define_insn "mvtipl" 2714 (define_insn "mvtipl"
2223 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "Uint04")] 2715 [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "Uint04")]
2282 [(const_int 0)] 2774 [(const_int 0)]
2283 "" 2775 ""
2284 "nop" 2776 "nop"
2285 [(set_attr "length" "1")] 2777 [(set_attr "length" "1")]
2286 ) 2778 )
2779
2780 (define_expand "pid_addr"
2781 [(plus:SI (match_operand:SI 0)
2782 (const:SI (unspec:SI [(match_operand:SI 1)] UNSPEC_PID_ADDR)))]
2783 ""
2784 ""
2785 )
2786
2787 (define_insn "movdi"
2788 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
2789 (match_operand:DI 1 "general_operand" "rmi"))]
2790 "TARGET_ENABLE_LRA"
2791 { return rx_gen_move_template (operands, false); }
2792 [(set_attr "length" "16")
2793 (set_attr "timings" "22")]
2794 )
2795
2796 (define_insn "movdf"
2797 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm")
2798 (match_operand:DF 1 "general_operand" "rmi"))]
2799 "TARGET_ENABLE_LRA"
2800 { return rx_gen_move_template (operands, false); }
2801 [(set_attr "length" "16")
2802 (set_attr "timings" "22")]
2803 )