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comparison gcc/config/sparc/ultra1_2.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents a06113de4d67
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Scheduling description for UltraSPARC-I/II. 1 ;; Scheduling description for UltraSPARC-I/II.
2 ;; Copyright (C) 2002, 2004, 2007 Free Software Foundation, Inc. 2 ;; Copyright (C) 2002-2017 Free Software Foundation, Inc.
3 ;; 3 ;;
4 ;; This file is part of GCC. 4 ;; This file is part of GCC.
5 ;; 5 ;;
6 ;; GCC is free software; you can redistribute it and/or modify 6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by 7 ;; it under the terms of the GNU General Public License as published by
77 (absence_set "us1_slot1" "us1_slot2,us1_slot3") 77 (absence_set "us1_slot1" "us1_slot2,us1_slot3")
78 (absence_set "us1_slot2" "us1_slot3") 78 (absence_set "us1_slot2" "us1_slot3")
79 79
80 (define_insn_reservation "us1_single" 1 80 (define_insn_reservation "us1_single" 1
81 (and (eq_attr "cpu" "ultrasparc") 81 (and (eq_attr "cpu" "ultrasparc")
82 (eq_attr "type" "multi,savew,flushw,iflush,trap")) 82 (eq_attr "type" "multi,savew,flushw,iflush,trap,gsr"))
83 "us1_single_issue") 83 "us1_single_issue")
84 84
85 (define_insn_reservation "us1_simple_ieuN" 1 85 (define_insn_reservation "us1_simple_ieuN" 1
86 (and (eq_attr "cpu" "ultrasparc") 86 (and (eq_attr "cpu" "ultrasparc")
87 (eq_attr "type" "ialu")) 87 (eq_attr "type" "ialu"))
92 (eq_attr "type" "shift")) 92 (eq_attr "type" "shift"))
93 "us1_ieu0 + us1_slot012") 93 "us1_ieu0 + us1_slot012")
94 94
95 (define_insn_reservation "us1_simple_ieu1" 1 95 (define_insn_reservation "us1_simple_ieu1" 1
96 (and (eq_attr "cpu" "ultrasparc") 96 (and (eq_attr "cpu" "ultrasparc")
97 (eq_attr "type" "compare")) 97 (eq_attr "type" "compare,edge,edgen,array"))
98 "us1_ieu1 + us1_slot012") 98 "us1_ieu1 + us1_slot012")
99 99
100 (define_insn_reservation "us1_ialuX" 1 100 (define_insn_reservation "us1_ialuX" 1
101 (and (eq_attr "cpu" "ultrasparc") 101 (and (eq_attr "cpu" "ultrasparc")
102 (eq_attr "type" "ialuX")) 102 (eq_attr "type" "ialuX"))
253 ;; VIS scheduling 253 ;; VIS scheduling
254 (define_insn_reservation "us1_fga_single" 254 (define_insn_reservation "us1_fga_single"
255 2 255 2
256 (and (and 256 (and (and
257 (eq_attr "cpu" "ultrasparc") 257 (eq_attr "cpu" "ultrasparc")
258 (eq_attr "type" "fga")) 258 (eq_attr "type" "fga,visl,vismv"))
259 (eq_attr "fptype" "single")) 259 (eq_attr "fptype" "single"))
260 "us1_fpa + us1_fp_single + us1_slotany, nothing") 260 "us1_fpa + us1_fp_single + us1_slotany, nothing")
261 261
262 (define_bypass 1 "us1_fga_single" "us1_fga_single") 262 (define_bypass 1 "us1_fga_single" "us1_fga_single")
263 263
264 (define_insn_reservation "us1_fga_double" 264 (define_insn_reservation "us1_fga_double"
265 2 265 2
266 (and (and 266 (and (eq_attr "cpu" "ultrasparc")
267 (eq_attr "cpu" "ultrasparc") 267 (ior (and (eq_attr "type" "fga,visl,vismv")
268 (eq_attr "type" "fga")) 268 (eq_attr "fptype" "double"))
269 (eq_attr "fptype" "double")) 269 (eq_attr "type" "viscmp")))
270 "us1_fpa + us1_fp_double + us1_slotany, nothing") 270 "us1_fpa + us1_fp_double + us1_slotany, nothing")
271 271
272 (define_bypass 1 "us1_fga_double" "us1_fga_double") 272 (define_bypass 1 "us1_fga_double" "us1_fga_double")
273 273
274 (define_insn_reservation "us1_fgm_single" 274 (define_insn_reservation "us1_fgm_single"
275 4 275 4
276 (and (and 276 (and (and
277 (eq_attr "cpu" "ultrasparc") 277 (eq_attr "cpu" "ultrasparc")
278 (eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp")) 278 (eq_attr "type" "fgm_pack,fgm_mul"))
279 (eq_attr "fptype" "single")) 279 (eq_attr "fptype" "single"))
280 "us1_fpm + us1_fp_single + us1_slotany, nothing*3") 280 "us1_fpm + us1_fp_single + us1_slotany, nothing*3")
281 281
282 (define_bypass 3 "us1_fgm_single" "us1_fga_single") 282 (define_bypass 3 "us1_fgm_single" "us1_fga_single")
283 283
284 (define_insn_reservation "us1_fgm_double" 284 (define_insn_reservation "us1_fgm_double"
285 4 285 4
286 (and (and 286 (and (and
287 (eq_attr "cpu" "ultrasparc") 287 (eq_attr "cpu" "ultrasparc")
288 (eq_attr "type" "fgm_pack,fgm_mul,fgm_cmp")) 288 (eq_attr "type" "fgm_pack,fgm_mul"))
289 (eq_attr "fptype" "double")) 289 (eq_attr "fptype" "double"))
290 "us1_fpm + us1_fp_double + us1_slotany, nothing*3") 290 "us1_fpm + us1_fp_double + us1_slotany, nothing*3")
291 291
292 (define_bypass 3 "us1_fgm_double" "us1_fga_double") 292 (define_bypass 3 "us1_fgm_double" "us1_fga_double")
293 293
294 (define_insn_reservation "us1_pdist" 294 (define_insn_reservation "us1_pdist"
295 4 295 4
296 (and (eq_attr "cpu" "ultrasparc") 296 (and (eq_attr "cpu" "ultrasparc")
297 (eq_attr "type" "fgm_pdist")) 297 (eq_attr "type" "pdist"))
298 "us1_fpm + us1_fp_double + us1_slotany, nothing*3") 298 "us1_fpm + us1_fp_double + us1_slotany, nothing*3")
299 299
300 (define_bypass 3 "us1_pdist" "us1_fga_double,us1_fga_single") 300 (define_bypass 3 "us1_pdist" "us1_fga_double,us1_fga_single")
301 (define_bypass 1 "us1_pdist" "us1_pdist") 301 (define_bypass 1 "us1_pdist" "us1_pdist")