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comparison gcc/config/spu/spu.h @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 /* Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. 1 /* Copyright (C) 2006-2017 Free Software Foundation, Inc.
2 2
3 This file is free software; you can redistribute it and/or modify it under 3 This file is free software; you can redistribute it and/or modify it under
4 the terms of the GNU General Public License as published by the Free 4 the terms of the GNU General Public License as published by the Free
5 Software Foundation; either version 3 of the License, or (at your option) 5 Software Foundation; either version 3 of the License, or (at your option)
6 any later version. 6 any later version.
15 <http://www.gnu.org/licenses/>. */ 15 <http://www.gnu.org/licenses/>. */
16 16
17 17
18 /* Run-time Target */ 18 /* Run-time Target */
19 #define TARGET_CPU_CPP_BUILTINS() spu_cpu_cpp_builtins(pfile) 19 #define TARGET_CPU_CPP_BUILTINS() spu_cpu_cpp_builtins(pfile)
20
21 #define TARGET_VERSION fprintf (stderr, " (spu %s)", __DATE__);
22 20
23 #define C_COMMON_OVERRIDE_OPTIONS spu_c_common_override_options() 21 #define C_COMMON_OVERRIDE_OPTIONS spu_c_common_override_options()
24 22
25 #define INIT_EXPANDERS spu_init_expanders() 23 #define INIT_EXPANDERS spu_init_expanders()
26 24
53 #define BITS_BIG_ENDIAN 1 51 #define BITS_BIG_ENDIAN 1
54 52
55 #define BYTES_BIG_ENDIAN 1 53 #define BYTES_BIG_ENDIAN 1
56 54
57 #define WORDS_BIG_ENDIAN 1 55 #define WORDS_BIG_ENDIAN 1
58
59 #define BITS_PER_UNIT 8
60 56
61 /* GCC uses word_mode in many places, assuming that it is the fastest 57 /* GCC uses word_mode in many places, assuming that it is the fastest
62 integer mode. That is not the case for SPU though. We can't use 58 integer mode. That is not the case for SPU though. We can't use
63 32 here because (of some reason I can't remember.) */ 59 32 here because (of some reason I can't remember.) */
64 #define BITS_PER_WORD 128 60 #define BITS_PER_WORD 128
98 they are also padded to 16-bytes, which means we can use a single 94 they are also padded to 16-bytes, which means we can use a single
99 load or store instruction to access them. Do the same for objects 95 load or store instruction to access them. Do the same for objects
100 on the stack. (Except a bug (?) allows some stack objects to be 96 on the stack. (Except a bug (?) allows some stack objects to be
101 unaligned.) */ 97 unaligned.) */
102 #define DATA_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128) 98 #define DATA_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
103 #define CONSTANT_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
104 #define LOCAL_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128) 99 #define LOCAL_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128)
105 100
106 #define EMPTY_FIELD_BOUNDARY 32 101 #define EMPTY_FIELD_BOUNDARY 32
107 102
108 #define STRICT_ALIGNMENT 1 103 #define STRICT_ALIGNMENT 1
173 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 168 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
174 1, 1, 1 \ 169 1, 1, 1 \
175 } 170 }
176 171
177 172
178 /* Values in Registers */
179
180 #define HARD_REGNO_NREGS(REGNO, MODE) \
181 ((GET_MODE_BITSIZE(MODE)+MAX_FIXED_MODE_SIZE-1)/MAX_FIXED_MODE_SIZE)
182
183 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
184
185 #define MODES_TIEABLE_P(MODE1, MODE2) \
186 (GET_MODE_BITSIZE (MODE1) <= MAX_FIXED_MODE_SIZE \
187 && GET_MODE_BITSIZE (MODE2) <= MAX_FIXED_MODE_SIZE)
188
189
190 /* Register Classes */ 173 /* Register Classes */
191 174
192 enum reg_class { 175 enum reg_class {
193 NO_REGS, 176 NO_REGS,
194 GENERAL_REGS, 177 GENERAL_REGS,
195 ALL_REGS, 178 ALL_REGS,
196 LIM_REG_CLASSES 179 LIM_REG_CLASSES
197 }; 180 };
198 181
199 /* SPU is simple, it really only has one class of registers. */
200 #define IRA_COVER_CLASSES { GENERAL_REGS, LIM_REG_CLASSES }
201
202 #define N_REG_CLASSES (int) LIM_REG_CLASSES 182 #define N_REG_CLASSES (int) LIM_REG_CLASSES
203 183
204 #define REG_CLASS_NAMES \ 184 #define REG_CLASS_NAMES \
205 { "NO_REGS", \ 185 { "NO_REGS", \
206 "GENERAL_REGS", \ 186 "GENERAL_REGS", \
210 #define REG_CLASS_CONTENTS { \ 190 #define REG_CLASS_CONTENTS { \
211 {0, 0, 0, 0, 0}, /* no regs */ \ 191 {0, 0, 0, 0, 0}, /* no regs */ \
212 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x3}, /* general regs */ \ 192 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x3}, /* general regs */ \
213 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x3}} /* all regs */ 193 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x3}} /* all regs */
214 194
215 #define REGNO_REG_CLASS(REGNO) (GENERAL_REGS) 195 #define REGNO_REG_CLASS(REGNO) ((void)(REGNO), GENERAL_REGS)
196
216 197
217 #define BASE_REG_CLASS GENERAL_REGS 198 #define BASE_REG_CLASS GENERAL_REGS
218 199
219 #define INDEX_REG_CLASS GENERAL_REGS 200 #define INDEX_REG_CLASS GENERAL_REGS
220 201
227 #define INT_REG_OK_FOR_INDEX_P(X,STRICT) \ 208 #define INT_REG_OK_FOR_INDEX_P(X,STRICT) \
228 ((!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X)))) 209 ((!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X))))
229 #define INT_REG_OK_FOR_BASE_P(X,STRICT) \ 210 #define INT_REG_OK_FOR_BASE_P(X,STRICT) \
230 ((!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X)))) 211 ((!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X))))
231 212
232 #define CLASS_MAX_NREGS(CLASS, MODE) \
233 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
234
235 /* GCC assumes that modes are in the lowpart of a register, which is
236 only true for SPU. */
237 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
238 ((GET_MODE_SIZE (FROM) > 4 || GET_MODE_SIZE (TO) > 4) \
239 && (GET_MODE_SIZE (FROM) < 16 || GET_MODE_SIZE (TO) < 16) \
240 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
241
242 #define REGISTER_TARGET_PRAGMAS() do { \ 213 #define REGISTER_TARGET_PRAGMAS() do { \
243 c_register_addr_space ("__ea", ADDR_SPACE_EA); \ 214 c_register_addr_space ("__ea", ADDR_SPACE_EA); \
244 targetm.resolve_overloaded_builtin = spu_resolve_overloaded_builtin; \ 215 targetm.resolve_overloaded_builtin = spu_resolve_overloaded_builtin; \
245 }while (0); 216 }while (0);
246 217
247 218
248 /* Frame Layout */ 219 /* Frame Layout */
249 220
250 #define STACK_GROWS_DOWNWARD 221 #define STACK_GROWS_DOWNWARD 1
251 222
252 #define FRAME_GROWS_DOWNWARD 1 223 #define FRAME_GROWS_DOWNWARD 1
253 224
254 #define STARTING_FRAME_OFFSET (0)
255
256 #define STACK_POINTER_OFFSET 32 225 #define STACK_POINTER_OFFSET 32
257 226
258 #define FIRST_PARM_OFFSET(FNDECL) (0) 227 #define FIRST_PARM_OFFSET(FNDECL) (0)
259 228
260 #define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant ((FP), -16) 229 #define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant (Pmode, (FP), -16)
261 230
262 #define RETURN_ADDR_RTX(COUNT,FP) (spu_return_addr (COUNT, FP)) 231 #define RETURN_ADDR_RTX(COUNT,FP) (spu_return_addr (COUNT, FP))
263 232
264 /* Should this be defined? Would it simplify our implementation. */ 233 /* Should this be defined? Would it simplify our implementation. */
265 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 234 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
335 #define CUMULATIVE_ARGS int 304 #define CUMULATIVE_ARGS int
336 305
337 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \ 306 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
338 ((CUM) = 0) 307 ((CUM) = 0)
339 308
340 /* The SPU ABI wants 32/64-bit types at offset 0 in the quad-word on the
341 stack. 8/16-bit types should be at offsets 3/2 respectively. */
342 #define FUNCTION_ARG_OFFSET(MODE, TYPE) \
343 (((TYPE) && INTEGRAL_TYPE_P (TYPE) && GET_MODE_SIZE (MODE) < 4) \
344 ? (4 - GET_MODE_SIZE (MODE)) \
345 : 0)
346
347 #define FUNCTION_ARG_PADDING(MODE,TYPE) upward
348
349 #define PAD_VARARGS_DOWN 0 309 #define PAD_VARARGS_DOWN 0
350 310
351 #define FUNCTION_ARG_REGNO_P(N) ((N) >= (FIRST_ARG_REGNUM) && (N) <= (LAST_ARG_REGNUM)) 311 #define FUNCTION_ARG_REGNO_P(N) ((N) >= (FIRST_ARG_REGNUM) && (N) <= (LAST_ARG_REGNUM))
352 312
353 /* Scalar Return */ 313 /* Scalar Return */
395 355
396 #define CONSTANT_ADDRESS_P(X) spu_constant_address_p(X) 356 #define CONSTANT_ADDRESS_P(X) spu_constant_address_p(X)
397 357
398 #define MAX_REGS_PER_ADDRESS 2 358 #define MAX_REGS_PER_ADDRESS 2
399 359
400 #define LEGITIMATE_CONSTANT_P(X) spu_legitimate_constant_p(X) 360 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
361 do { \
362 rtx new_rtx = spu_legitimize_reload_address (AD, MODE, OPNUM, \
363 (int)(TYPE)); \
364 if (new_rtx) \
365 { \
366 (AD) = new_rtx; \
367 goto WIN; \
368 } \
369 } while (0)
401 370
402 371
403 /* Costs */ 372 /* Costs */
404 373
405 #define BRANCH_COST(speed_p, predictable_p) spu_branch_cost 374 #define BRANCH_COST(speed_p, predictable_p) spu_branch_cost
406 375
407 #define SLOW_BYTE_ACCESS 0 376 #define SLOW_BYTE_ACCESS 0
408 377
409 #define MOVE_RATIO(speed) ((speed)? 32 : 4) 378 #define MOVE_RATIO(speed) ((speed)? 32 : 4)
410 379
411 #define NO_FUNCTION_CSE 380 #define NO_FUNCTION_CSE 1
412 381
413 382
414 /* Sections */ 383 /* Sections */
415 384
416 #define TEXT_SECTION_ASM_OP ".text" 385 #define TEXT_SECTION_ASM_OP ".text"
506 475
507 #define CASE_VECTOR_MODE SImode 476 #define CASE_VECTOR_MODE SImode
508 477
509 #define MOVE_MAX 16 478 #define MOVE_MAX 16
510 479
511 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) ((INPREC) <= 32 && (OUTPREC) <= (INPREC))
512
513 #define STORE_FLAG_VALUE -1 480 #define STORE_FLAG_VALUE -1
514 481
515 #define Pmode SImode 482 #define Pmode SImode
516 483
517 #define FUNCTION_MODE QImode 484 #define FUNCTION_MODE QImode
518 485
519 #define NO_IMPLICIT_EXTERN_C 1 486 #define NO_IMPLICIT_EXTERN_C 1
520
521 /* Canonicalize a comparison from one we don't have to one we do have. */
522 #define CANONICALIZE_COMPARISON(CODE,OP0,OP1) \
523 do { \
524 if (((CODE) == LE || (CODE) == LT || (CODE) == LEU || (CODE) == LTU)) \
525 { \
526 rtx tem = (OP0); \
527 (OP0) = (OP1); \
528 (OP1) = tem; \
529 (CODE) = swap_condition (CODE); \
530 } \
531 } while (0)
532 487
533 488
534 /* Address spaces. */ 489 /* Address spaces. */
535 #define ADDR_SPACE_EA 1 490 #define ADDR_SPACE_EA 1
536 491