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comparison gcc/config/spu/spu.md @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
comparison
equal deleted inserted replaced
68:561a7518be6b 111:04ced10e8804
1 ;; Copyright (C) 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. 1 ;; Copyright (C) 2006-2017 Free Software Foundation, Inc.
2 2
3 ;; This file is free software; you can redistribute it and/or modify it under 3 ;; This file is free software; you can redistribute it and/or modify it under
4 ;; the terms of the GNU General Public License as published by the Free 4 ;; the terms of the GNU General Public License as published by the Free
5 ;; Software Foundation; either version 3 of the License, or (at your option) 5 ;; Software Foundation; either version 3 of the License, or (at your option)
6 ;; any later version. 6 ;; any later version.
99 99
100 ;; Force pipe0 to occur before pipe 1 in a cycle. 100 ;; Force pipe0 to occur before pipe 1 in a cycle.
101 (absence_set "pipe0" "pipe1") 101 (absence_set "pipe0" "pipe1")
102 102
103 103
104 (define_constants [ 104 (define_c_enum "unspec" [
105 (UNSPEC_BLOCKAGE 0) 105 UNSPEC_IPREFETCH
106 (UNSPEC_IPREFETCH 1) 106 UNSPEC_FREST
107 (UNSPEC_FREST 2) 107 UNSPEC_FRSQEST
108 (UNSPEC_FRSQEST 3) 108 UNSPEC_FI
109 (UNSPEC_FI 4) 109 UNSPEC_EXTEND_CMP
110 (UNSPEC_EXTEND_CMP 5) 110 UNSPEC_CG
111 (UNSPEC_CG 6) 111 UNSPEC_CGX
112 (UNSPEC_CGX 7) 112 UNSPEC_ADDX
113 (UNSPEC_ADDX 8) 113 UNSPEC_BG
114 (UNSPEC_BG 9) 114 UNSPEC_BGX
115 (UNSPEC_BGX 10) 115 UNSPEC_SFX
116 (UNSPEC_SFX 11) 116 UNSPEC_FSM
117 (UNSPEC_FSM 12) 117 UNSPEC_HBR
118 (UNSPEC_HBR 13) 118 UNSPEC_NOP
119 (UNSPEC_LNOP 14) 119 UNSPEC_CONVERT
120 (UNSPEC_NOP 15) 120 UNSPEC_SELB
121 (UNSPEC_CONVERT 16) 121 UNSPEC_SHUFB
122 (UNSPEC_SELB 17) 122 UNSPEC_CPAT
123 (UNSPEC_SHUFB 18) 123 UNSPEC_CNTB
124 (UNSPEC_CPAT 19) 124 UNSPEC_SUMB
125 (UNSPEC_SYNC 20) 125 UNSPEC_FSMB
126 (UNSPEC_CNTB 21) 126 UNSPEC_FSMH
127 (UNSPEC_SUMB 22) 127 UNSPEC_GBB
128 (UNSPEC_FSMB 23) 128 UNSPEC_GBH
129 (UNSPEC_FSMH 24) 129 UNSPEC_GB
130 (UNSPEC_GBB 25) 130 UNSPEC_AVGB
131 (UNSPEC_GBH 26) 131 UNSPEC_ABSDB
132 (UNSPEC_GB 27) 132 UNSPEC_ORX
133 (UNSPEC_AVGB 28) 133 UNSPEC_HEQ
134 (UNSPEC_ABSDB 29) 134 UNSPEC_HGT
135 (UNSPEC_ORX 30) 135 UNSPEC_HLGT
136 (UNSPEC_HEQ 31) 136 UNSPEC_STOP
137 (UNSPEC_HGT 32) 137 UNSPEC_STOPD
138 (UNSPEC_HLGT 33) 138 UNSPEC_SET_INTR
139 (UNSPEC_STOP 38) 139 UNSPEC_FSCRRD
140 (UNSPEC_STOPD 39) 140 UNSPEC_FSCRWR
141 (UNSPEC_SET_INTR 40) 141 UNSPEC_MFSPR
142 (UNSPEC_FSCRRD 42) 142 UNSPEC_MTSPR
143 (UNSPEC_FSCRWR 43) 143 UNSPEC_RDCH
144 (UNSPEC_MFSPR 44) 144 UNSPEC_RCHCNT
145 (UNSPEC_MTSPR 45) 145 UNSPEC_WRCH
146 (UNSPEC_RDCH 46) 146 UNSPEC_SPU_REALIGN_LOAD
147 (UNSPEC_RCHCNT 47) 147 UNSPEC_SPU_MASK_FOR_LOAD
148 (UNSPEC_WRCH 48) 148 UNSPEC_DFTSV
149 (UNSPEC_SPU_REALIGN_LOAD 49) 149 UNSPEC_FLOAT_EXTEND
150 (UNSPEC_SPU_MASK_FOR_LOAD 50) 150 UNSPEC_FLOAT_TRUNCATE
151 (UNSPEC_DFTSV 51) 151 UNSPEC_SP_SET
152 (UNSPEC_FLOAT_EXTEND 52) 152 UNSPEC_SP_TEST
153 (UNSPEC_FLOAT_TRUNCATE 53) 153 ])
154 (UNSPEC_SP_SET 54) 154
155 (UNSPEC_SP_TEST 55) 155 (define_c_enum "unspecv" [
156 UNSPECV_BLOCKAGE
157 UNSPECV_LNOP
158 UNSPECV_NOP
159 UNSPECV_SYNC
156 ]) 160 ])
157 161
158 (include "predicates.md") 162 (include "predicates.md")
159 (include "constraints.md") 163 (include "constraints.md")
160 164
250 (V8HI "HI") 254 (V8HI "HI")
251 (V4SI "SI") 255 (V4SI "SI")
252 (V2DI "DI") 256 (V2DI "DI")
253 (V4SF "SF") 257 (V4SF "SF")
254 (V2DF "DF")]) 258 (V2DF "DF")])
259 ;; Like above, but in lower case
260 (define_mode_attr inner_l [(V16QI "qi")
261 (V8HI "hi")
262 (V4SI "si")
263 (V2DI "di")
264 (V4SF "sf")
265 (V2DF "df")])
255 (define_mode_attr vmult [(V16QI "1") 266 (define_mode_attr vmult [(V16QI "1")
256 (V8HI "2") 267 (V8HI "2")
257 (V4SI "4") 268 (V4SI "4")
258 (V2DI "8") 269 (V2DI "8")
259 (V4SF "4") 270 (V4SF "4")
745 756
746 emit_insn (gen_floatunsv4siv4sf2 (op2_v4sf, op1_v4si)); 757 emit_insn (gen_floatunsv4siv4sf2 (op2_v4sf, op1_v4si));
747 emit_insn (gen_shlqby_ti (op3_ti, op2_ti, GEN_INT (4))); 758 emit_insn (gen_shlqby_ti (op3_ti, op2_ti, GEN_INT (4)));
748 759
749 emit_move_insn (operands[4], 760 emit_move_insn (operands[4],
750 CONST_DOUBLE_FROM_REAL_VALUE (scale, SFmode)); 761 const_double_from_real_value (scale, SFmode));
751 emit_insn (gen_fmasf4 (operands[0], 762 emit_insn (gen_fmasf4 (operands[0],
752 operands[2], operands[4], operands[3])); 763 operands[2], operands[4], operands[3]));
753 DONE; 764 DONE;
754 }) 765 })
755 766
804 815
805 emit_insn (gen_floatunsv4siv4sf2 (op2_v4sf, op1_v4si)); 816 emit_insn (gen_floatunsv4siv4sf2 (op2_v4sf, op1_v4si));
806 emit_insn (gen_shlqby_ti (op3_ti, op2_ti, GEN_INT (4))); 817 emit_insn (gen_shlqby_ti (op3_ti, op2_ti, GEN_INT (4)));
807 818
808 emit_move_insn (operands[4], 819 emit_move_insn (operands[4],
809 CONST_DOUBLE_FROM_REAL_VALUE (scale, SFmode)); 820 const_double_from_real_value (scale, SFmode));
810 emit_insn (gen_fmasf4 (operands[2], 821 emit_insn (gen_fmasf4 (operands[2],
811 operands[2], operands[4], operands[3])); 822 operands[2], operands[4], operands[3]));
812 823
813 emit_insn (gen_shlqby_ti (op3_ti, op3_ti, GEN_INT (4))); 824 emit_insn (gen_shlqby_ti (op3_ti, op3_ti, GEN_INT (4)));
814 emit_insn (gen_fmasf4 (operands[2], 825 emit_insn (gen_fmasf4 (operands[2],
842 (define_expand "floatunssidf2" 853 (define_expand "floatunssidf2"
843 [(set (match_operand:DF 0 "register_operand" "=r") 854 [(set (match_operand:DF 0 "register_operand" "=r")
844 (unsigned_float:DF (match_operand:SI 1 "register_operand" "r")))] 855 (unsigned_float:DF (match_operand:SI 1 "register_operand" "r")))]
845 "" 856 ""
846 "{ 857 "{
847 rtx value, insns; 858 rtx value;
848 rtx c0 = spu_const_from_ints (V16QImode, 0x02031011, 0x12138080, 859 rtx c0 = spu_const_from_ints (V16QImode, 0x02031011, 0x12138080,
849 0x06071415, 0x16178080); 860 0x06071415, 0x16178080);
850 rtx r0 = gen_reg_rtx (V16QImode); 861 rtx r0 = gen_reg_rtx (V16QImode);
851 862
852 if (optimize_size) 863 if (optimize_size)
853 { 864 {
854 start_sequence (); 865 start_sequence ();
855 value = 866 value =
856 emit_library_call_value (convert_optab_libfunc (ufloat_optab, 867 emit_library_call_value (convert_optab_libfunc (ufloat_optab,
857 DFmode, SImode), 868 DFmode, SImode),
858 NULL_RTX, LCT_NORMAL, DFmode, 1, operands[1], SImode); 869 NULL_RTX, LCT_NORMAL, DFmode,
859 insns = get_insns (); 870 operands[1], SImode);
871 rtx_insn *insns = get_insns ();
860 end_sequence (); 872 end_sequence ();
861 emit_libcall_block (insns, operands[0], value, 873 emit_libcall_block (insns, operands[0], value,
862 gen_rtx_UNSIGNED_FLOAT (DFmode, operands[1])); 874 gen_rtx_UNSIGNED_FLOAT (DFmode, operands[1]));
863 } 875 }
864 else 876 else
933 (define_expand "floatunsdidf2" 945 (define_expand "floatunsdidf2"
934 [(set (match_operand:DF 0 "register_operand" "=r") 946 [(set (match_operand:DF 0 "register_operand" "=r")
935 (unsigned_float:DF (match_operand:DI 1 "register_operand" "r")))] 947 (unsigned_float:DF (match_operand:DI 1 "register_operand" "r")))]
936 "" 948 ""
937 "{ 949 "{
938 rtx value, insns; 950 rtx value;
939 rtx c0 = spu_const_from_ints (V16QImode, 0x02031011, 0x12138080, 951 rtx c0 = spu_const_from_ints (V16QImode, 0x02031011, 0x12138080,
940 0x06071415, 0x16178080); 952 0x06071415, 0x16178080);
941 rtx c1 = spu_const_from_ints (V4SImode, 1023+63, 1023+31, 0, 0); 953 rtx c1 = spu_const_from_ints (V4SImode, 1023+63, 1023+31, 0, 0);
942 rtx r0 = gen_reg_rtx (V16QImode); 954 rtx r0 = gen_reg_rtx (V16QImode);
943 rtx r1 = gen_reg_rtx (V4SImode); 955 rtx r1 = gen_reg_rtx (V4SImode);
946 { 958 {
947 start_sequence (); 959 start_sequence ();
948 value = 960 value =
949 emit_library_call_value (convert_optab_libfunc (ufloat_optab, 961 emit_library_call_value (convert_optab_libfunc (ufloat_optab,
950 DFmode, DImode), 962 DFmode, DImode),
951 NULL_RTX, LCT_NORMAL, DFmode, 1, operands[1], DImode); 963 NULL_RTX, LCT_NORMAL, DFmode,
952 insns = get_insns (); 964 operands[1], DImode);
965 rtx_insn *insns = get_insns ();
953 end_sequence (); 966 end_sequence ();
954 emit_libcall_block (insns, operands[0], value, 967 emit_libcall_block (insns, operands[0], value,
955 gen_rtx_UNSIGNED_FLOAT (DFmode, operands[1])); 968 gen_rtx_UNSIGNED_FLOAT (DFmode, operands[1]));
956 } 969 }
957 else 970 else
1060 1073
1061 (define_insn "cg_<mode>" 1074 (define_insn "cg_<mode>"
1062 [(set (match_operand:CBOP 0 "spu_reg_operand" "=r") 1075 [(set (match_operand:CBOP 0 "spu_reg_operand" "=r")
1063 (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") 1076 (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r")
1064 (match_operand 2 "spu_reg_operand" "r")] UNSPEC_CG))] 1077 (match_operand 2 "spu_reg_operand" "r")] UNSPEC_CG))]
1065 "operands" 1078 "operands != NULL"
1066 "cg\t%0,%1,%2") 1079 "cg\t%0,%1,%2")
1067 1080
1068 (define_insn "cgx_<mode>" 1081 (define_insn "cgx_<mode>"
1069 [(set (match_operand:CBOP 0 "spu_reg_operand" "=r") 1082 [(set (match_operand:CBOP 0 "spu_reg_operand" "=r")
1070 (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") 1083 (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r")
1071 (match_operand 2 "spu_reg_operand" "r") 1084 (match_operand 2 "spu_reg_operand" "r")
1072 (match_operand 3 "spu_reg_operand" "0")] UNSPEC_CGX))] 1085 (match_operand 3 "spu_reg_operand" "0")] UNSPEC_CGX))]
1073 "operands" 1086 "operands != NULL"
1074 "cgx\t%0,%1,%2") 1087 "cgx\t%0,%1,%2")
1075 1088
1076 (define_insn "addx_<mode>" 1089 (define_insn "addx_<mode>"
1077 [(set (match_operand:CBOP 0 "spu_reg_operand" "=r") 1090 [(set (match_operand:CBOP 0 "spu_reg_operand" "=r")
1078 (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") 1091 (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r")
1079 (match_operand 2 "spu_reg_operand" "r") 1092 (match_operand 2 "spu_reg_operand" "r")
1080 (match_operand 3 "spu_reg_operand" "0")] UNSPEC_ADDX))] 1093 (match_operand 3 "spu_reg_operand" "0")] UNSPEC_ADDX))]
1081 "operands" 1094 "operands != NULL"
1082 "addx\t%0,%1,%2") 1095 "addx\t%0,%1,%2")
1083 1096
1084 1097
1085 ;; This is not the most efficient implementation of addti3. 1098 ;; This is not the most efficient implementation of addti3.
1086 ;; We include this here because 1) the compiler needs it to be 1099 ;; We include this here because 1) the compiler needs it to be
1183 1196
1184 (define_insn "bg_<mode>" 1197 (define_insn "bg_<mode>"
1185 [(set (match_operand:CBOP 0 "spu_reg_operand" "=r") 1198 [(set (match_operand:CBOP 0 "spu_reg_operand" "=r")
1186 (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") 1199 (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r")
1187 (match_operand 2 "spu_reg_operand" "r")] UNSPEC_BG))] 1200 (match_operand 2 "spu_reg_operand" "r")] UNSPEC_BG))]
1188 "operands" 1201 "operands != NULL"
1189 "bg\t%0,%2,%1") 1202 "bg\t%0,%2,%1")
1190 1203
1191 (define_insn "bgx_<mode>" 1204 (define_insn "bgx_<mode>"
1192 [(set (match_operand:CBOP 0 "spu_reg_operand" "=r") 1205 [(set (match_operand:CBOP 0 "spu_reg_operand" "=r")
1193 (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") 1206 (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r")
1194 (match_operand 2 "spu_reg_operand" "r") 1207 (match_operand 2 "spu_reg_operand" "r")
1195 (match_operand 3 "spu_reg_operand" "0")] UNSPEC_BGX))] 1208 (match_operand 3 "spu_reg_operand" "0")] UNSPEC_BGX))]
1196 "operands" 1209 "operands != NULL"
1197 "bgx\t%0,%2,%1") 1210 "bgx\t%0,%2,%1")
1198 1211
1199 (define_insn "sfx_<mode>" 1212 (define_insn "sfx_<mode>"
1200 [(set (match_operand:CBOP 0 "spu_reg_operand" "=r") 1213 [(set (match_operand:CBOP 0 "spu_reg_operand" "=r")
1201 (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r") 1214 (unspec:CBOP [(match_operand 1 "spu_reg_operand" "r")
1202 (match_operand 2 "spu_reg_operand" "r") 1215 (match_operand 2 "spu_reg_operand" "r")
1203 (match_operand 3 "spu_reg_operand" "0")] UNSPEC_SFX))] 1216 (match_operand 3 "spu_reg_operand" "0")] UNSPEC_SFX))]
1204 "operands" 1217 "operands != NULL"
1205 "sfx\t%0,%2,%1") 1218 "sfx\t%0,%2,%1")
1206 1219
1207 (define_insn "subti3" 1220 (define_insn "subti3"
1208 [(set (match_operand:TI 0 "spu_reg_operand" "=r") 1221 [(set (match_operand:TI 0 "spu_reg_operand" "=r")
1209 (minus:TI (match_operand:TI 1 "spu_reg_operand" "r") 1222 (minus:TI (match_operand:TI 1 "spu_reg_operand" "r")
1381 rtx high = gen_reg_rtx (V4SImode); 1394 rtx high = gen_reg_rtx (V4SImode);
1382 rtx shift = gen_reg_rtx (V4SImode); 1395 rtx shift = gen_reg_rtx (V4SImode);
1383 rtx mask = gen_reg_rtx (V4SImode); 1396 rtx mask = gen_reg_rtx (V4SImode);
1384 1397
1385 emit_move_insn (mask, spu_const (V4SImode, 0x0000ffff)); 1398 emit_move_insn (mask, spu_const (V4SImode, 0x0000ffff));
1386 emit_insn (gen_spu_mpyhh (high, operands[1], operands[2])); 1399 emit_insn (gen_vec_widen_smult_even_v8hi (high, operands[1], operands[2]));
1387 emit_insn (gen_spu_mpy (low, operands[1], operands[2])); 1400 emit_insn (gen_vec_widen_smult_odd_v8hi (low, operands[1], operands[2]));
1388 emit_insn (gen_vashlv4si3 (shift, high, spu_const(V4SImode, 16))); 1401 emit_insn (gen_vashlv4si3 (shift, high, spu_const(V4SImode, 16)));
1389 emit_insn (gen_selb (result, shift, low, mask)); 1402 emit_insn (gen_selb (result, shift, low, mask));
1390 DONE; 1403 DONE;
1391 }") 1404 }")
1392 1405
1476 rtx d = operands[6]; 1489 rtx d = operands[6];
1477 rtx op1 = simplify_gen_subreg (V8HImode, operands[1], V4SImode, 0); 1490 rtx op1 = simplify_gen_subreg (V8HImode, operands[1], V4SImode, 0);
1478 rtx op2 = simplify_gen_subreg (V8HImode, operands[2], V4SImode, 0); 1491 rtx op2 = simplify_gen_subreg (V8HImode, operands[2], V4SImode, 0);
1479 emit_insn (gen_spu_mpyh(a, op1, op2)); 1492 emit_insn (gen_spu_mpyh(a, op1, op2));
1480 emit_insn (gen_spu_mpyh(b, op2, op1)); 1493 emit_insn (gen_spu_mpyh(b, op2, op1));
1481 emit_insn (gen_spu_mpyu(c, op1, op2)); 1494 emit_insn (gen_vec_widen_umult_odd_v8hi (c, op1, op2));
1482 emit_insn (gen_addv4si3(d, a, b)); 1495 emit_insn (gen_addv4si3(d, a, b));
1483 emit_insn (gen_addv4si3(operands[0], d, c)); 1496 emit_insn (gen_addv4si3(operands[0], d, c));
1484 DONE; 1497 DONE;
1485 }) 1498 })
1486 1499
1727 rtx op1_hi = gen_rtx_SUBREG (HImode, operands[1], 2); 1740 rtx op1_hi = gen_rtx_SUBREG (HImode, operands[1], 2);
1728 rtx op2_hi = gen_rtx_SUBREG (HImode, operands[2], 2); 1741 rtx op2_hi = gen_rtx_SUBREG (HImode, operands[2], 2);
1729 rtx t0_hi = gen_rtx_SUBREG (HImode, t0, 2); 1742 rtx t0_hi = gen_rtx_SUBREG (HImode, t0, 2);
1730 rtx t1_hi = gen_rtx_SUBREG (HImode, t1, 2); 1743 rtx t1_hi = gen_rtx_SUBREG (HImode, t1, 2);
1731 1744
1732 rtx insn = emit_insn (gen_lshrsi3 (t0, operands[1], GEN_INT (16))); 1745 rtx_insn *insn = emit_insn (gen_lshrsi3 (t0, operands[1], GEN_INT (16)));
1733 emit_insn (gen_lshrsi3 (t1, operands[2], GEN_INT (16))); 1746 emit_insn (gen_lshrsi3 (t1, operands[2], GEN_INT (16)));
1734 emit_insn (gen_umulhisi3 (t2, op1_hi, op2_hi)); 1747 emit_insn (gen_umulhisi3 (t2, op1_hi, op2_hi));
1735 emit_insn (gen_mpyh_si (t3, operands[1], operands[2])); 1748 emit_insn (gen_mpyh_si (t3, operands[1], operands[2]));
1736 emit_insn (gen_mpyh_si (t4, operands[2], operands[1])); 1749 emit_insn (gen_mpyh_si (t4, operands[2], operands[1]));
1737 emit_insn (gen_mpyhh_si (t5, operands[1], operands[2])); 1750 emit_insn (gen_mpyhh_si (t5, operands[1], operands[2]));
1788 rtx t14 = gen_reg_rtx (SImode); 1801 rtx t14 = gen_reg_rtx (SImode);
1789 rtx op1_hi = gen_rtx_SUBREG (HImode, operands[1], 2); 1802 rtx op1_hi = gen_rtx_SUBREG (HImode, operands[1], 2);
1790 rtx op2_hi = gen_rtx_SUBREG (HImode, operands[2], 2); 1803 rtx op2_hi = gen_rtx_SUBREG (HImode, operands[2], 2);
1791 rtx t0_hi = gen_rtx_SUBREG (HImode, t0, 2); 1804 rtx t0_hi = gen_rtx_SUBREG (HImode, t0, 2);
1792 1805
1793 rtx insn = emit_insn (gen_rotlsi3 (t0, operands[2], GEN_INT (16))); 1806 rtx_insn *insn = emit_insn (gen_rotlsi3 (t0, operands[2], GEN_INT (16)));
1794 emit_insn (gen_umulhisi3 (t1, op1_hi, op2_hi)); 1807 emit_insn (gen_umulhisi3 (t1, op1_hi, op2_hi));
1795 emit_insn (gen_umulhisi3 (t2, op1_hi, t0_hi)); 1808 emit_insn (gen_umulhisi3 (t2, op1_hi, t0_hi));
1796 emit_insn (gen_mpyhhu_si (t3, operands[1], t0)); 1809 emit_insn (gen_mpyhhu_si (t3, operands[1], t0));
1797 emit_insn (gen_mpyhhu_si (t4, operands[1], operands[2])); 1810 emit_insn (gen_mpyhhu_si (t4, operands[1], operands[2]));
1798 emit_insn (gen_ashlsi3 (t5, t2, GEN_INT (16))); 1811 emit_insn (gen_ashlsi3 (t5, t2, GEN_INT (16)));
2230 operands[3] = gen_reg_rtx (<MODE>mode); 2243 operands[3] = gen_reg_rtx (<MODE>mode);
2231 operands[4] = gen_reg_rtx (<MODE>mode); 2244 operands[4] = gen_reg_rtx (<MODE>mode);
2232 operands[5] = spu_const(<MODE>mode, 31); 2245 operands[5] = spu_const(<MODE>mode, 31);
2233 }) 2246 })
2234 2247
2248 (define_expand "clrsb<mode>2"
2249 [(set (match_dup 2)
2250 (gt:VSI (match_operand:VSI 1 "spu_reg_operand" "") (match_dup 5)))
2251 (set (match_dup 3) (not:VSI (xor:VSI (match_dup 1) (match_dup 2))))
2252 (set (match_dup 4) (clz:VSI (match_dup 3)))
2253 (set (match_operand:VSI 0 "spu_reg_operand")
2254 (plus:VSI (match_dup 4) (match_dup 5)))]
2255 ""
2256 {
2257 operands[2] = gen_reg_rtx (<MODE>mode);
2258 operands[3] = gen_reg_rtx (<MODE>mode);
2259 operands[4] = gen_reg_rtx (<MODE>mode);
2260 operands[5] = spu_const(<MODE>mode, -1);
2261 })
2262
2235 (define_expand "ffs<mode>2" 2263 (define_expand "ffs<mode>2"
2236 [(set (match_dup 2) 2264 [(set (match_dup 2)
2237 (neg:VSI (match_operand:VSI 1 "spu_reg_operand" ""))) 2265 (neg:VSI (match_operand:VSI 1 "spu_reg_operand" "")))
2238 (set (match_dup 3) (and:VSI (match_dup 1) 2266 (set (match_dup 3) (and:VSI (match_dup 1)
2239 (match_dup 2))) 2267 (match_dup 2)))
2830 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") 2858 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "")
2831 (match_operand:SI 1 "const_int_operand" "") 2859 (match_operand:SI 1 "const_int_operand" "")
2832 (match_operand:SI 2 "const_int_operand" "")) 2860 (match_operand:SI 2 "const_int_operand" ""))
2833 (match_operand 3 "nonmemory_operand" ""))] 2861 (match_operand 3 "nonmemory_operand" ""))]
2834 "" 2862 ""
2835 { spu_expand_insv(operands); DONE; }) 2863 {
2864 if (INTVAL (operands[1]) + INTVAL (operands[2])
2865 > GET_MODE_BITSIZE (GET_MODE (operands[0])))
2866 FAIL;
2867 spu_expand_insv(operands);
2868 DONE;
2869 })
2836 2870
2837 ;; Simplify a number of patterns that get generated by extv, extzv, 2871 ;; Simplify a number of patterns that get generated by extv, extzv,
2838 ;; insv, and loads. 2872 ;; insv, and loads.
2839 (define_insn_and_split "trunc_shr_ti<mode>" 2873 (define_insn_and_split "trunc_shr_ti<mode>"
2840 [(set (match_operand:QHSI 0 "spu_reg_operand" "=r") 2874 [(set (match_operand:QHSI 0 "spu_reg_operand" "=r")
3853 "bi%b1%b0z\t%1,$lr" 3887 "bi%b1%b0z\t%1,$lr"
3854 [(set_attr "type" "br")]) 3888 [(set_attr "type" "br")])
3855 3889
3856 3890
3857 ;; vector conditional compare patterns 3891 ;; vector conditional compare patterns
3858 (define_expand "vcond<mode>" 3892 (define_expand "vcond<mode><mode>"
3859 [(set (match_operand:VCMP 0 "spu_reg_operand" "=r") 3893 [(set (match_operand:VCMP 0 "spu_reg_operand" "=r")
3860 (if_then_else:VCMP 3894 (if_then_else:VCMP
3861 (match_operator 3 "comparison_operator" 3895 (match_operator 3 "comparison_operator"
3862 [(match_operand:VCMP 4 "spu_reg_operand" "r") 3896 [(match_operand:VCMP 4 "spu_reg_operand" "r")
3863 (match_operand:VCMP 5 "spu_reg_operand" "r")]) 3897 (match_operand:VCMP 5 "spu_reg_operand" "r")])
3870 DONE; 3904 DONE;
3871 else 3905 else
3872 FAIL; 3906 FAIL;
3873 }) 3907 })
3874 3908
3875 (define_expand "vcondu<mode>" 3909 (define_expand "vcondu<mode><mode>"
3876 [(set (match_operand:VCMPU 0 "spu_reg_operand" "=r") 3910 [(set (match_operand:VCMPU 0 "spu_reg_operand" "=r")
3877 (if_then_else:VCMPU 3911 (if_then_else:VCMPU
3878 (match_operator 3 "comparison_operator" 3912 (match_operator 3 "comparison_operator"
3879 [(match_operand:VCMPU 4 "spu_reg_operand" "r") 3913 [(match_operand:VCMPU 4 "spu_reg_operand" "r")
3880 (match_operand:VCMPU 5 "spu_reg_operand" "r")]) 3914 (match_operand:VCMPU 5 "spu_reg_operand" "r")])
3987 (define_expand "extend_compare" 4021 (define_expand "extend_compare"
3988 [(set (match_operand 0 "spu_reg_operand" "=r") 4022 [(set (match_operand 0 "spu_reg_operand" "=r")
3989 (unspec [(match_operand 1 "spu_reg_operand" "r")] UNSPEC_EXTEND_CMP))] 4023 (unspec [(match_operand 1 "spu_reg_operand" "r")] UNSPEC_EXTEND_CMP))]
3990 "" 4024 ""
3991 { 4025 {
3992 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 4026 emit_insn (gen_rtx_SET (operands[0],
3993 gen_rtx_UNSPEC (GET_MODE (operands[0]), 4027 gen_rtx_UNSPEC (GET_MODE (operands[0]),
3994 gen_rtvec (1, operands[1]), 4028 gen_rtvec (1, operands[1]),
3995 UNSPEC_EXTEND_CMP))); 4029 UNSPEC_EXTEND_CMP)));
3996 DONE; 4030 DONE;
3997 }) 4031 })
3998 4032
3999 (define_insn "extend_compare<mode>" 4033 (define_insn "extend_compare<mode>"
4000 [(set (match_operand:ALL 0 "spu_reg_operand" "=r") 4034 [(set (match_operand:ALL 0 "spu_reg_operand" "=r")
4001 (unspec:ALL [(match_operand 1 "spu_reg_operand" "r")] UNSPEC_EXTEND_CMP))] 4035 (unspec:ALL [(match_operand 1 "spu_reg_operand" "r")] UNSPEC_EXTEND_CMP))]
4002 "operands" 4036 "operands != NULL"
4003 "fsm\t%0,%1" 4037 "fsm\t%0,%1"
4004 [(set_attr "type" "shuf")]) 4038 [(set_attr "type" "shuf")])
4005 4039
4006 4040
4007 ;; case 4041 ;; case
4188 (define_expand "prologue" 4222 (define_expand "prologue"
4189 [(const_int 1)] 4223 [(const_int 1)]
4190 "" 4224 ""
4191 { spu_expand_prologue (); DONE; }) 4225 { spu_expand_prologue (); DONE; })
4192 4226
4193 ;; "blockage" is only emited in epilogue. This is what it took to 4227 ;; "blockage" is only emitted in epilogue. This is what it took to
4194 ;; make "basic block reordering" work with the insns sequence 4228 ;; make "basic block reordering" work with the insns sequence
4195 ;; generated by the spu_expand_epilogue (taken from mips.md) 4229 ;; generated by the spu_expand_epilogue (taken from mips.md)
4196 4230
4197 (define_insn "blockage" 4231 (define_insn "blockage"
4198 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)] 4232 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4199 "" 4233 ""
4200 "" 4234 ""
4201 [(set_attr "type" "convert") 4235 [(set_attr "type" "convert")
4202 (set_attr "length" "0")]) 4236 (set_attr "length" "0")])
4203 4237
4291 4325
4292 4326
4293 ;; vector patterns 4327 ;; vector patterns
4294 4328
4295 ;; Vector initialization 4329 ;; Vector initialization
4296 (define_expand "vec_init<mode>" 4330 (define_expand "vec_init<mode><inner_l>"
4297 [(match_operand:V 0 "register_operand" "") 4331 [(match_operand:V 0 "register_operand" "")
4298 (match_operand 1 "" "")] 4332 (match_operand 1 "" "")]
4299 "" 4333 ""
4300 { 4334 {
4301 spu_expand_vector_init (operands[0], operands[1]); 4335 spu_expand_vector_init (operands[0], operands[1]);
4320 operands[4] = stack_pointer_rtx; 4354 operands[4] = stack_pointer_rtx;
4321 operands[5] = offset; 4355 operands[5] = offset;
4322 operands[6] = GEN_INT (size); 4356 operands[6] = GEN_INT (size);
4323 }) 4357 })
4324 4358
4325 (define_expand "vec_extract<mode>" 4359 (define_expand "vec_extract<mode><inner_l>"
4326 [(set (match_operand:<inner> 0 "spu_reg_operand" "=r") 4360 [(set (match_operand:<inner> 0 "spu_reg_operand" "=r")
4327 (vec_select:<inner> (match_operand:V 1 "spu_reg_operand" "r") 4361 (vec_select:<inner> (match_operand:V 1 "spu_reg_operand" "r")
4328 (parallel [(match_operand 2 "const_int_operand" "i")])))] 4362 (parallel [(match_operand 2 "const_int_operand" "i")])))]
4329 "" 4363 ""
4330 { 4364 {
4370 (define_insn "_shufb" 4404 (define_insn "_shufb"
4371 [(set (match_operand 0 "spu_reg_operand" "=r") 4405 [(set (match_operand 0 "spu_reg_operand" "=r")
4372 (unspec [(match_operand 1 "spu_reg_operand" "r") 4406 (unspec [(match_operand 1 "spu_reg_operand" "r")
4373 (match_operand 2 "spu_reg_operand" "r") 4407 (match_operand 2 "spu_reg_operand" "r")
4374 (match_operand:TI 3 "spu_reg_operand" "r")] UNSPEC_SHUFB))] 4408 (match_operand:TI 3 "spu_reg_operand" "r")] UNSPEC_SHUFB))]
4375 "operands" 4409 "operands != NULL"
4376 "shufb\t%0,%1,%2,%3" 4410 "shufb\t%0,%1,%2,%3"
4377 [(set_attr "type" "shuf")]) 4411 [(set_attr "type" "shuf")])
4378 4412
4413 ; The semantics of vec_permv16qi are nearly identical to those of the SPU
4414 ; shufb instruction, except that we need to reduce the selector modulo 32.
4415 (define_expand "vec_permv16qi"
4416 [(set (match_dup 4) (and:V16QI (match_operand:V16QI 3 "spu_reg_operand" "")
4417 (match_dup 6)))
4418 (set (match_operand:V16QI 0 "spu_reg_operand" "")
4419 (unspec:V16QI
4420 [(match_operand:V16QI 1 "spu_reg_operand" "")
4421 (match_operand:V16QI 2 "spu_reg_operand" "")
4422 (match_dup 5)]
4423 UNSPEC_SHUFB))]
4424 ""
4425 {
4426 operands[4] = gen_reg_rtx (V16QImode);
4427 operands[5] = gen_lowpart (TImode, operands[4]);
4428 operands[6] = spu_const (V16QImode, 31);
4429 })
4430
4379 (define_insn "nop" 4431 (define_insn "nop"
4380 [(unspec_volatile [(const_int 0)] UNSPEC_NOP)] 4432 [(unspec_volatile [(const_int 0)] UNSPECV_NOP)]
4381 "" 4433 ""
4382 "nop" 4434 "nop"
4383 [(set_attr "type" "nop")]) 4435 [(set_attr "type" "nop")])
4384 4436
4385 (define_insn "nopn" 4437 (define_insn "nopn"
4386 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "K")] UNSPEC_NOP)] 4438 [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "K")] UNSPECV_NOP)]
4387 "" 4439 ""
4388 "nop\t%0" 4440 "nop\t%0"
4389 [(set_attr "type" "nop")]) 4441 [(set_attr "type" "nop")])
4390 4442
4391 (define_insn "lnop" 4443 (define_insn "lnop"
4392 [(unspec_volatile [(const_int 0)] UNSPEC_LNOP)] 4444 [(unspec_volatile [(const_int 0)] UNSPECV_LNOP)]
4393 "" 4445 ""
4394 "lnop" 4446 "lnop"
4395 [(set_attr "type" "lnop")]) 4447 [(set_attr "type" "lnop")])
4396 4448
4397 ;; The operand is so we know why we generated this hbrp. 4449 ;; The operand is so we know why we generated this hbrp.
4422 hbrr\t%0,%1 4474 hbrr\t%0,%1
4423 hbra\t%0,%1" 4475 hbra\t%0,%1"
4424 [(set_attr "type" "hbr")]) 4476 [(set_attr "type" "hbr")])
4425 4477
4426 (define_insn "sync" 4478 (define_insn "sync"
4427 [(unspec_volatile [(const_int 0)] UNSPEC_SYNC) 4479 [(unspec_volatile [(const_int 0)] UNSPECV_SYNC)
4428 (clobber (mem:BLK (scratch)))] 4480 (clobber (mem:BLK (scratch)))]
4429 "" 4481 ""
4430 "sync" 4482 "sync"
4431 [(set_attr "type" "br")]) 4483 [(set_attr "type" "br")])
4432 4484
4433 (define_insn "syncc" 4485 (define_insn "syncc"
4434 [(unspec_volatile [(const_int 1)] UNSPEC_SYNC) 4486 [(unspec_volatile [(const_int 1)] UNSPECV_SYNC)
4435 (clobber (mem:BLK (scratch)))] 4487 (clobber (mem:BLK (scratch)))]
4436 "" 4488 ""
4437 "syncc" 4489 "syncc"
4438 [(set_attr "type" "br")]) 4490 [(set_attr "type" "br")])
4439 4491
4440 (define_insn "dsync" 4492 (define_insn "dsync"
4441 [(unspec_volatile [(const_int 2)] UNSPEC_SYNC) 4493 [(unspec_volatile [(const_int 2)] UNSPECV_SYNC)
4442 (clobber (mem:BLK (scratch)))] 4494 (clobber (mem:BLK (scratch)))]
4443 "" 4495 ""
4444 "dsync" 4496 "dsync"
4445 [(set_attr "type" "br")]) 4497 [(set_attr "type" "br")])
4446 4498
4448 4500
4449 ;; Define the subtract-one-and-jump insns so loop.c 4501 ;; Define the subtract-one-and-jump insns so loop.c
4450 ;; knows what to generate. 4502 ;; knows what to generate.
4451 (define_expand "doloop_end" 4503 (define_expand "doloop_end"
4452 [(use (match_operand 0 "" "")) ; loop pseudo 4504 [(use (match_operand 0 "" "")) ; loop pseudo
4453 (use (match_operand 1 "" "")) ; iterations; zero if unknown 4505 (use (match_operand 1 "" ""))] ; label
4454 (use (match_operand 2 "" "")) ; max iterations
4455 (use (match_operand 3 "" "")) ; loop level
4456 (use (match_operand 4 "" ""))] ; label
4457 "" 4506 ""
4458 " 4507 "
4459 { 4508 {
4460 /* Currently SMS relies on the do-loop pattern to recognize loops 4509 /* Currently SMS relies on the do-loop pattern to recognize loops
4461 where (1) the control part comprises of all insns defining and/or 4510 where (1) the control part comprises of all insns defining and/or
4467 { 4516 {
4468 rtx s0; 4517 rtx s0;
4469 rtx bcomp; 4518 rtx bcomp;
4470 rtx loc_ref; 4519 rtx loc_ref;
4471 4520
4472 /* Only use this on innermost loops. */
4473 if (INTVAL (operands[3]) > 1)
4474 FAIL;
4475 if (GET_MODE (operands[0]) != SImode) 4521 if (GET_MODE (operands[0]) != SImode)
4476 FAIL; 4522 FAIL;
4477 4523
4478 s0 = operands [0]; 4524 s0 = operands [0];
4479 emit_move_insn (s0, gen_rtx_PLUS (SImode, s0, GEN_INT (-1))); 4525 emit_move_insn (s0, gen_rtx_PLUS (SImode, s0, GEN_INT (-1)));
4480 bcomp = gen_rtx_NE(SImode, s0, const0_rtx); 4526 bcomp = gen_rtx_NE(SImode, s0, const0_rtx);
4481 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [4]); 4527 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [1]);
4482 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, 4528 emit_jump_insn (gen_rtx_SET (pc_rtx,
4483 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp, 4529 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
4484 loc_ref, pc_rtx))); 4530 loc_ref, pc_rtx)));
4485 4531
4486 DONE; 4532 DONE;
4487 }else 4533 }else
4572 emit_insn (gen_cgt_v2df (mask, operands[1], operands[2])); 4618 emit_insn (gen_cgt_v2df (mask, operands[1], operands[2]));
4573 emit_insn (gen_selb (operands[0], operands[1], operands[2], 4619 emit_insn (gen_selb (operands[0], operands[1], operands[2],
4574 spu_gen_subreg (V4SImode, mask))); 4620 spu_gen_subreg (V4SImode, mask)));
4575 DONE; 4621 DONE;
4576 }") 4622 }")
4623
4624 (define_insn "vec_widen_smult_odd_v8hi"
4625 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r,r")
4626 (mult:V4SI
4627 (sign_extend:V4SI
4628 (vec_select:V4HI
4629 (match_operand:V8HI 1 "spu_reg_operand" "r,r")
4630 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
4631 (sign_extend:V4SI
4632 (vec_select:V4HI
4633 (match_operand:V8HI 2 "spu_arith_operand" "r,B")
4634 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))))]
4635 ""
4636 "@
4637 mpy\t%0,%1,%2
4638 mpyi\t%0,%1,%2"
4639 [(set_attr "type" "fp7")])
4640
4641 (define_insn "vec_widen_umult_odd_v8hi"
4642 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r,r")
4643 (mult:V4SI
4644 (zero_extend:V4SI
4645 (vec_select:V4HI
4646 (match_operand:V8HI 1 "spu_reg_operand" "r,r")
4647 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))
4648 (zero_extend:V4SI
4649 (vec_select:V4HI
4650 (match_operand:V8HI 2 "spu_arith_operand" "r,B")
4651 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)])))))]
4652 ""
4653 "@
4654 mpyu\t%0,%1,%2
4655 mpyui\t%0,%1,%2"
4656 [(set_attr "type" "fp7")])
4657
4658 (define_insn "vec_widen_smult_even_v8hi"
4659 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
4660 (mult:V4SI
4661 (sign_extend:V4SI
4662 (vec_select:V4HI
4663 (match_operand:V8HI 1 "spu_reg_operand" "r")
4664 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
4665 (sign_extend:V4SI
4666 (vec_select:V4HI
4667 (match_operand:V8HI 2 "spu_reg_operand" "r")
4668 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))))]
4669 ""
4670 "mpyhh\t%0,%1,%2"
4671 [(set_attr "type" "fp7")])
4672
4673 (define_insn "vec_widen_umult_even_v8hi"
4674 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
4675 (mult:V4SI
4676 (zero_extend:V4SI
4677 (vec_select:V4HI
4678 (match_operand:V8HI 1 "spu_reg_operand" "r")
4679 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))
4680 (zero_extend:V4SI
4681 (vec_select:V4HI
4682 (match_operand:V8HI 2 "spu_reg_operand" "r")
4683 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)])))))]
4684 ""
4685 "mpyhhu\t%0,%1,%2"
4686 [(set_attr "type" "fp7")])
4577 4687
4578 (define_expand "vec_widen_umult_hi_v8hi" 4688 (define_expand "vec_widen_umult_hi_v8hi"
4579 [(set (match_operand:V4SI 0 "register_operand" "=r") 4689 [(set (match_operand:V4SI 0 "register_operand" "=r")
4580 (mult:V4SI 4690 (mult:V4SI
4581 (zero_extend:V4SI 4691 (zero_extend:V4SI
4595 unsigned char arr[16] = { 4705 unsigned char arr[16] = {
4596 0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13, 4706 0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
4597 0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17}; 4707 0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17};
4598 4708
4599 emit_move_insn (mask, array_to_constant (TImode, arr)); 4709 emit_move_insn (mask, array_to_constant (TImode, arr));
4600 emit_insn (gen_spu_mpyhhu (ve, operands[1], operands[2])); 4710 emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2]));
4601 emit_insn (gen_spu_mpyu (vo, operands[1], operands[2])); 4711 emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2]));
4602 emit_insn (gen_shufb (operands[0], ve, vo, mask)); 4712 emit_insn (gen_shufb (operands[0], ve, vo, mask));
4603 DONE; 4713 DONE;
4604 }") 4714 }")
4605 4715
4606 (define_expand "vec_widen_umult_lo_v8hi" 4716 (define_expand "vec_widen_umult_lo_v8hi"
4623 unsigned char arr[16] = { 4733 unsigned char arr[16] = {
4624 0x08, 0x09, 0x0A, 0x0B, 0x18, 0x19, 0x1A, 0x1B, 4734 0x08, 0x09, 0x0A, 0x0B, 0x18, 0x19, 0x1A, 0x1B,
4625 0x0C, 0x0D, 0x0E, 0x0F, 0x1C, 0x1D, 0x1E, 0x1F}; 4735 0x0C, 0x0D, 0x0E, 0x0F, 0x1C, 0x1D, 0x1E, 0x1F};
4626 4736
4627 emit_move_insn (mask, array_to_constant (TImode, arr)); 4737 emit_move_insn (mask, array_to_constant (TImode, arr));
4628 emit_insn (gen_spu_mpyhhu (ve, operands[1], operands[2])); 4738 emit_insn (gen_vec_widen_umult_even_v8hi (ve, operands[1], operands[2]));
4629 emit_insn (gen_spu_mpyu (vo, operands[1], operands[2])); 4739 emit_insn (gen_vec_widen_umult_odd_v8hi (vo, operands[1], operands[2]));
4630 emit_insn (gen_shufb (operands[0], ve, vo, mask)); 4740 emit_insn (gen_shufb (operands[0], ve, vo, mask));
4631 DONE; 4741 DONE;
4632 }") 4742 }")
4633 4743
4634 (define_expand "vec_widen_smult_hi_v8hi" 4744 (define_expand "vec_widen_smult_hi_v8hi"
4651 unsigned char arr[16] = { 4761 unsigned char arr[16] = {
4652 0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13, 4762 0x00, 0x01, 0x02, 0x03, 0x10, 0x11, 0x12, 0x13,
4653 0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17}; 4763 0x04, 0x05, 0x06, 0x07, 0x14, 0x15, 0x16, 0x17};
4654 4764
4655 emit_move_insn (mask, array_to_constant (TImode, arr)); 4765 emit_move_insn (mask, array_to_constant (TImode, arr));
4656 emit_insn (gen_spu_mpyhh (ve, operands[1], operands[2])); 4766 emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2]));
4657 emit_insn (gen_spu_mpy (vo, operands[1], operands[2])); 4767 emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2]));
4658 emit_insn (gen_shufb (operands[0], ve, vo, mask)); 4768 emit_insn (gen_shufb (operands[0], ve, vo, mask));
4659 DONE; 4769 DONE;
4660 }") 4770 }")
4661 4771
4662 (define_expand "vec_widen_smult_lo_v8hi" 4772 (define_expand "vec_widen_smult_lo_v8hi"
4679 unsigned char arr[16] = { 4789 unsigned char arr[16] = {
4680 0x08, 0x09, 0x0A, 0x0B, 0x18, 0x19, 0x1A, 0x1B, 4790 0x08, 0x09, 0x0A, 0x0B, 0x18, 0x19, 0x1A, 0x1B,
4681 0x0C, 0x0D, 0x0E, 0x0F, 0x1C, 0x1D, 0x1E, 0x1F}; 4791 0x0C, 0x0D, 0x0E, 0x0F, 0x1C, 0x1D, 0x1E, 0x1F};
4682 4792
4683 emit_move_insn (mask, array_to_constant (TImode, arr)); 4793 emit_move_insn (mask, array_to_constant (TImode, arr));
4684 emit_insn (gen_spu_mpyhh (ve, operands[1], operands[2])); 4794 emit_insn (gen_vec_widen_smult_even_v8hi (ve, operands[1], operands[2]));
4685 emit_insn (gen_spu_mpy (vo, operands[1], operands[2])); 4795 emit_insn (gen_vec_widen_smult_odd_v8hi (vo, operands[1], operands[2]));
4686 emit_insn (gen_shufb (operands[0], ve, vo, mask)); 4796 emit_insn (gen_shufb (operands[0], ve, vo, mask));
4687 DONE; 4797 DONE;
4688 }") 4798 }")
4689 4799
4690 (define_expand "vec_realign_load_<mode>" 4800 (define_expand "vec_realign_load_<mode>"
4908 5018
4909 DONE; 5019 DONE;
4910 }) 5020 })
4911 5021
4912 5022
4913 (define_expand "vec_extract_evenv4si"
4914 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
4915 (vec_concat:V4SI
4916 (vec_select:V2SI
4917 (match_operand:V4SI 1 "spu_reg_operand" "r")
4918 (parallel [(const_int 0)(const_int 2)]))
4919 (vec_select:V2SI
4920 (match_operand:V4SI 2 "spu_reg_operand" "r")
4921 (parallel [(const_int 0)(const_int 2)]))))]
4922
4923 ""
4924 "
4925 {
4926 rtx mask = gen_reg_rtx (TImode);
4927 unsigned char arr[16] = {
4928 0x00, 0x01, 0x02, 0x03,
4929 0x08, 0x09, 0x0A, 0x0B,
4930 0x10, 0x11, 0x12, 0x13,
4931 0x18, 0x19, 0x1A, 0x1B};
4932
4933 emit_move_insn (mask, array_to_constant (TImode, arr));
4934 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
4935 DONE;
4936 }")
4937
4938
4939 (define_expand "vec_extract_evenv4sf"
4940 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
4941 (vec_concat:V4SF
4942 (vec_select:V2SF
4943 (match_operand:V4SF 1 "spu_reg_operand" "r")
4944 (parallel [(const_int 0)(const_int 2)]))
4945 (vec_select:V2SF
4946 (match_operand:V4SF 2 "spu_reg_operand" "r")
4947 (parallel [(const_int 0)(const_int 2)]))))]
4948
4949 ""
4950 "
4951 {
4952 rtx mask = gen_reg_rtx (TImode);
4953 unsigned char arr[16] = {
4954 0x00, 0x01, 0x02, 0x03,
4955 0x08, 0x09, 0x0A, 0x0B,
4956 0x10, 0x11, 0x12, 0x13,
4957 0x18, 0x19, 0x1A, 0x1B};
4958
4959 emit_move_insn (mask, array_to_constant (TImode, arr));
4960 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
4961 DONE;
4962 }")
4963
4964 (define_expand "vec_extract_evenv8hi"
4965 [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
4966 (vec_concat:V8HI
4967 (vec_select:V4HI
4968 (match_operand:V8HI 1 "spu_reg_operand" "r")
4969 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))
4970 (vec_select:V4HI
4971 (match_operand:V8HI 2 "spu_reg_operand" "r")
4972 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))))]
4973
4974 ""
4975 "
4976 {
4977 rtx mask = gen_reg_rtx (TImode);
4978 unsigned char arr[16] = {
4979 0x00, 0x01, 0x04, 0x05,
4980 0x08, 0x09, 0x0C, 0x0D,
4981 0x10, 0x11, 0x14, 0x15,
4982 0x18, 0x19, 0x1C, 0x1D};
4983
4984 emit_move_insn (mask, array_to_constant (TImode, arr));
4985 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
4986 DONE;
4987 }")
4988
4989 (define_expand "vec_extract_evenv16qi"
4990 [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
4991 (vec_concat:V16QI
4992 (vec_select:V8QI
4993 (match_operand:V16QI 1 "spu_reg_operand" "r")
4994 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)
4995 (const_int 8)(const_int 10)(const_int 12)(const_int 14)]))
4996 (vec_select:V8QI
4997 (match_operand:V16QI 2 "spu_reg_operand" "r")
4998 (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)
4999 (const_int 8)(const_int 10)(const_int 12)(const_int 14)]))))]
5000
5001 ""
5002 "
5003 {
5004 rtx mask = gen_reg_rtx (TImode);
5005 unsigned char arr[16] = {
5006 0x00, 0x02, 0x04, 0x06,
5007 0x08, 0x0A, 0x0C, 0x0E,
5008 0x10, 0x12, 0x14, 0x16,
5009 0x18, 0x1A, 0x1C, 0x1E};
5010
5011 emit_move_insn (mask, array_to_constant (TImode, arr));
5012 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5013 DONE;
5014 }")
5015
5016 (define_expand "vec_extract_oddv4si"
5017 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
5018 (vec_concat:V4SI
5019 (vec_select:V2SI
5020 (match_operand:V4SI 1 "spu_reg_operand" "r")
5021 (parallel [(const_int 1)(const_int 3)]))
5022 (vec_select:V2SI
5023 (match_operand:V4SI 2 "spu_reg_operand" "r")
5024 (parallel [(const_int 1)(const_int 3)]))))]
5025
5026 ""
5027 "
5028 {
5029 rtx mask = gen_reg_rtx (TImode);
5030 unsigned char arr[16] = {
5031 0x04, 0x05, 0x06, 0x07,
5032 0x0C, 0x0D, 0x0E, 0x0F,
5033 0x14, 0x15, 0x16, 0x17,
5034 0x1C, 0x1D, 0x1E, 0x1F};
5035
5036 emit_move_insn (mask, array_to_constant (TImode, arr));
5037 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5038 DONE;
5039 }")
5040
5041 (define_expand "vec_extract_oddv4sf"
5042 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
5043 (vec_concat:V4SF
5044 (vec_select:V2SF
5045 (match_operand:V4SF 1 "spu_reg_operand" "r")
5046 (parallel [(const_int 1)(const_int 3)]))
5047 (vec_select:V2SF
5048 (match_operand:V4SF 2 "spu_reg_operand" "r")
5049 (parallel [(const_int 1)(const_int 3)]))))]
5050
5051 ""
5052 "
5053 {
5054 rtx mask = gen_reg_rtx (TImode);
5055 unsigned char arr[16] = {
5056 0x04, 0x05, 0x06, 0x07,
5057 0x0C, 0x0D, 0x0E, 0x0F,
5058 0x14, 0x15, 0x16, 0x17,
5059 0x1C, 0x1D, 0x1E, 0x1F};
5060
5061 emit_move_insn (mask, array_to_constant (TImode, arr));
5062 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5063 DONE;
5064 }")
5065
5066 (define_expand "vec_extract_oddv8hi"
5067 [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
5068 (vec_concat:V8HI
5069 (vec_select:V4HI
5070 (match_operand:V8HI 1 "spu_reg_operand" "r")
5071 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))
5072 (vec_select:V4HI
5073 (match_operand:V8HI 2 "spu_reg_operand" "r")
5074 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))]
5075
5076 ""
5077 "
5078 {
5079 rtx mask = gen_reg_rtx (TImode);
5080 unsigned char arr[16] = {
5081 0x02, 0x03, 0x06, 0x07,
5082 0x0A, 0x0B, 0x0E, 0x0F,
5083 0x12, 0x13, 0x16, 0x17,
5084 0x1A, 0x1B, 0x1E, 0x1F};
5085
5086 emit_move_insn (mask, array_to_constant (TImode, arr));
5087 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5088 DONE;
5089 }")
5090
5091 (define_expand "vec_extract_oddv16qi"
5092 [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
5093 (vec_concat:V16QI
5094 (vec_select:V8QI
5095 (match_operand:V16QI 1 "spu_reg_operand" "r")
5096 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)
5097 (const_int 9)(const_int 11)(const_int 13)(const_int 15)]))
5098 (vec_select:V8QI
5099 (match_operand:V16QI 2 "spu_reg_operand" "r")
5100 (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)
5101 (const_int 9)(const_int 11)(const_int 13)(const_int 15)]))))]
5102
5103 ""
5104 "
5105 {
5106 rtx mask = gen_reg_rtx (TImode);
5107 unsigned char arr[16] = {
5108 0x01, 0x03, 0x05, 0x07,
5109 0x09, 0x0B, 0x0D, 0x0F,
5110 0x11, 0x13, 0x15, 0x17,
5111 0x19, 0x1B, 0x1D, 0x1F};
5112
5113 emit_move_insn (mask, array_to_constant (TImode, arr));
5114 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5115 DONE;
5116 }")
5117
5118 (define_expand "vec_interleave_highv4sf"
5119 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
5120 (vec_select:V4SF
5121 (vec_concat:V4SF
5122 (vec_select:V2SF
5123 (match_operand:V4SF 1 "spu_reg_operand" "r")
5124 (parallel [(const_int 0)(const_int 1)]))
5125 (vec_select:V2SF
5126 (match_operand:V4SF 2 "spu_reg_operand" "r")
5127 (parallel [(const_int 0)(const_int 1)])))
5128 (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
5129
5130 ""
5131 "
5132 {
5133 rtx mask = gen_reg_rtx (TImode);
5134 unsigned char arr[16] = {
5135 0x00, 0x01, 0x02, 0x03,
5136 0x10, 0x11, 0x12, 0x13,
5137 0x04, 0x05, 0x06, 0x07,
5138 0x14, 0x15, 0x16, 0x17};
5139
5140 emit_move_insn (mask, array_to_constant (TImode, arr));
5141 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5142 DONE;
5143 }")
5144
5145 (define_expand "vec_interleave_lowv4sf"
5146 [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
5147 (vec_select:V4SF
5148 (vec_concat:V4SF
5149 (vec_select:V2SF
5150 (match_operand:V4SF 1 "spu_reg_operand" "r")
5151 (parallel [(const_int 2)(const_int 3)]))
5152 (vec_select:V2SF
5153 (match_operand:V4SF 2 "spu_reg_operand" "r")
5154 (parallel [(const_int 2)(const_int 3)])))
5155 (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
5156
5157 ""
5158 "
5159 {
5160 rtx mask = gen_reg_rtx (TImode);
5161 unsigned char arr[16] = {
5162 0x08, 0x09, 0x0A, 0x0B,
5163 0x18, 0x19, 0x1A, 0x1B,
5164 0x0C, 0x0D, 0x0E, 0x0F,
5165 0x1C, 0x1D, 0x1E, 0x1F};
5166
5167 emit_move_insn (mask, array_to_constant (TImode, arr));
5168 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5169 DONE;
5170 }")
5171
5172 (define_expand "vec_interleave_highv4si"
5173 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
5174 (vec_select:V4SI
5175 (vec_concat:V4SI
5176 (vec_select:V2SI
5177 (match_operand:V4SI 1 "spu_reg_operand" "r")
5178 (parallel [(const_int 0)(const_int 1)]))
5179 (vec_select:V2SI
5180 (match_operand:V4SI 2 "spu_reg_operand" "r")
5181 (parallel [(const_int 0)(const_int 1)])))
5182 (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
5183
5184 ""
5185 "
5186 {
5187 rtx mask = gen_reg_rtx (TImode);
5188 unsigned char arr[16] = {
5189 0x00, 0x01, 0x02, 0x03,
5190 0x10, 0x11, 0x12, 0x13,
5191 0x04, 0x05, 0x06, 0x07,
5192 0x14, 0x15, 0x16, 0x17};
5193
5194 emit_move_insn (mask, array_to_constant (TImode, arr));
5195 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5196 DONE;
5197 }")
5198
5199 (define_expand "vec_interleave_lowv4si"
5200 [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
5201 (vec_select:V4SI
5202 (vec_concat:V4SI
5203 (vec_select:V2SI
5204 (match_operand:V4SI 1 "spu_reg_operand" "r")
5205 (parallel [(const_int 2)(const_int 3)]))
5206 (vec_select:V2SI
5207 (match_operand:V4SI 2 "spu_reg_operand" "r")
5208 (parallel [(const_int 2)(const_int 3)])))
5209 (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
5210
5211 ""
5212 "
5213 {
5214 rtx mask = gen_reg_rtx (TImode);
5215 unsigned char arr[16] = {
5216 0x08, 0x09, 0x0A, 0x0B,
5217 0x18, 0x19, 0x1A, 0x1B,
5218 0x0C, 0x0D, 0x0E, 0x0F,
5219 0x1C, 0x1D, 0x1E, 0x1F};
5220
5221 emit_move_insn (mask, array_to_constant (TImode, arr));
5222 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5223 DONE;
5224 }")
5225
5226 (define_expand "vec_interleave_highv8hi"
5227 [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
5228 (vec_select:V8HI
5229 (vec_concat:V8HI
5230 (vec_select:V4HI
5231 (match_operand:V8HI 1 "spu_reg_operand" "r")
5232 (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)]))
5233 (vec_select:V4HI
5234 (match_operand:V8HI 2 "spu_reg_operand" "r")
5235 (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)])))
5236 (parallel [(const_int 0)(const_int 4)(const_int 1)(const_int 5)
5237 (const_int 2)(const_int 6)(const_int 3)(const_int 7)])))]
5238
5239 ""
5240 "
5241 {
5242 rtx mask = gen_reg_rtx (TImode);
5243 unsigned char arr[16] = {
5244 0x00, 0x01, 0x10, 0x11,
5245 0x02, 0x03, 0x12, 0x13,
5246 0x04, 0x05, 0x14, 0x15,
5247 0x06, 0x07, 0x16, 0x17};
5248
5249 emit_move_insn (mask, array_to_constant (TImode, arr));
5250 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5251 DONE;
5252 }")
5253
5254 (define_expand "vec_interleave_lowv8hi"
5255 [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
5256 (vec_select:V8HI
5257 (vec_concat:V8HI
5258 (vec_select:V4HI
5259 (match_operand:V8HI 1 "spu_reg_operand" "r")
5260 (parallel [(const_int 4)(const_int 5)(const_int 6)(const_int 7)]))
5261 (vec_select:V4HI
5262 (match_operand:V8HI 2 "spu_reg_operand" "r")
5263 (parallel [(const_int 4)(const_int 5)(const_int 6)(const_int 7)])))
5264 (parallel [(const_int 0)(const_int 4)(const_int 1)(const_int 5)
5265 (const_int 2)(const_int 6)(const_int 3)(const_int 7)])))]
5266
5267 ""
5268 "
5269 {
5270 rtx mask = gen_reg_rtx (TImode);
5271 unsigned char arr[16] = {
5272 0x08, 0x09, 0x18, 0x19,
5273 0x0A, 0x0B, 0x1A, 0x1B,
5274 0x0C, 0x0D, 0x1C, 0x1D,
5275 0x0E, 0x0F, 0x1E, 0x1F};
5276
5277 emit_move_insn (mask, array_to_constant (TImode, arr));
5278 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5279 DONE;
5280 }")
5281
5282 (define_expand "vec_interleave_highv16qi"
5283 [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
5284 (vec_select:V16QI
5285 (vec_concat:V16QI
5286 (vec_select:V8QI
5287 (match_operand:V16QI 1 "spu_reg_operand" "r")
5288 (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)
5289 (const_int 4)(const_int 5)(const_int 6)(const_int 7)]))
5290 (vec_select:V8QI
5291 (match_operand:V16QI 2 "spu_reg_operand" "r")
5292 (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)
5293 (const_int 4)(const_int 5)(const_int 6)(const_int 7)])))
5294 (parallel [(const_int 0)(const_int 8)(const_int 1)(const_int 9)
5295 (const_int 2)(const_int 10)(const_int 3)(const_int 11)
5296 (const_int 4)(const_int 12)(const_int 5)(const_int 13)
5297 (const_int 6)(const_int 14)(const_int 7)(const_int 15)])))]
5298
5299 ""
5300 "
5301 {
5302 rtx mask = gen_reg_rtx (TImode);
5303 unsigned char arr[16] = {
5304 0x00, 0x10, 0x01, 0x11,
5305 0x02, 0x12, 0x03, 0x13,
5306 0x04, 0x14, 0x05, 0x15,
5307 0x06, 0x16, 0x07, 0x17};
5308
5309 emit_move_insn (mask, array_to_constant (TImode, arr));
5310 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5311 DONE;
5312 }")
5313
5314 (define_expand "vec_interleave_lowv16qi"
5315 [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
5316 (vec_select:V16QI
5317 (vec_concat:V16QI
5318 (vec_select:V8QI
5319 (match_operand:V16QI 1 "spu_reg_operand" "r")
5320 (parallel [(const_int 8)(const_int 9)(const_int 10)(const_int 11)
5321 (const_int 12)(const_int 13)(const_int 14)(const_int 15)]))
5322 (vec_select:V8QI
5323 (match_operand:V16QI 2 "spu_reg_operand" "r")
5324 (parallel [(const_int 8)(const_int 9)(const_int 10)(const_int 11)
5325 (const_int 12)(const_int 13)(const_int 14)(const_int 15)])))
5326 (parallel [(const_int 0)(const_int 8)(const_int 1)(const_int 9)
5327 (const_int 2)(const_int 10)(const_int 3)(const_int 11)
5328 (const_int 4)(const_int 12)(const_int 5)(const_int 13)
5329 (const_int 6)(const_int 14)(const_int 7)(const_int 15)])))]
5330
5331 ""
5332 "
5333 {
5334 rtx mask = gen_reg_rtx (TImode);
5335 unsigned char arr[16] = {
5336 0x08, 0x18, 0x09, 0x19,
5337 0x0A, 0x1A, 0x0B, 0x1B,
5338 0x0C, 0x1C, 0x0D, 0x1D,
5339 0x0E, 0x1E, 0x0F, 0x1F};
5340
5341 emit_move_insn (mask, array_to_constant (TImode, arr));
5342 emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
5343 DONE;
5344 }")
5345
5346 (define_expand "vec_pack_trunc_v8hi" 5023 (define_expand "vec_pack_trunc_v8hi"
5347 [(set (match_operand:V16QI 0 "spu_reg_operand" "=r") 5024 [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
5348 (vec_concat:V16QI 5025 (vec_concat:V16QI
5349 (truncate:V8QI (match_operand:V8HI 1 "spu_reg_operand" "r")) 5026 (truncate:V8QI (match_operand:V8HI 1 "spu_reg_operand" "r"))
5350 (truncate:V8QI (match_operand:V8HI 2 "spu_reg_operand" "r"))))] 5027 (truncate:V8QI (match_operand:V8HI 2 "spu_reg_operand" "r"))))]
5408 5085
5409 bcomp = gen_rtx_NE (SImode, compare_result, const0_rtx); 5086 bcomp = gen_rtx_NE (SImode, compare_result, const0_rtx);
5410 5087
5411 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[2]); 5088 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[2]);
5412 5089
5413 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, 5090 emit_jump_insn (gen_rtx_SET (pc_rtx,
5414 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp, 5091 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
5415 loc_ref, pc_rtx))); 5092 loc_ref, pc_rtx)));
5416 5093
5417 DONE; 5094 DONE;
5418 }) 5095 })
5419 5096
5420 (define_insn "stack_protect_test_si" 5097 (define_insn "stack_protect_test_si"
5427 "lq%p1\t%0,%1\;lq%p2\t%3,%2\;ceq\t%0,%0,%3\;xor\t%3,%3,%3" 5104 "lq%p1\t%0,%1\;lq%p2\t%3,%2\;ceq\t%0,%0,%3\;xor\t%3,%3,%3"
5428 [(set_attr "length" "16") 5105 [(set_attr "length" "16")
5429 (set_attr "type" "multi1")] 5106 (set_attr "type" "multi1")]
5430 ) 5107 )
5431 5108
5109 ; Atomic operations
5110 ;
5111 ; SPU execution is always single-threaded, so there is no need for real
5112 ; atomic operations. We provide the atomic primitives anyway so that
5113 ; code expecting the builtins to be present (like libgfortran) will work.
5114
5115 ;; Types that we should provide atomic instructions for.
5116 (define_mode_iterator AINT [QI HI SI DI TI])
5117
5118 (define_code_iterator ATOMIC [plus minus ior xor and mult])
5119 (define_code_attr atomic_name
5120 [(plus "add") (minus "sub")
5121 (ior "or") (xor "xor") (and "and") (mult "nand")])
5122 (define_code_attr atomic_pred
5123 [(plus "spu_arith_operand") (minus "spu_reg_operand")
5124 (ior "spu_logical_operand") (xor "spu_logical_operand")
5125 (and "spu_logical_operand") (mult "spu_logical_operand")])
5126
5127 (define_expand "atomic_load<mode>"
5128 [(set (match_operand:AINT 0 "spu_reg_operand" "") ;; output
5129 (match_operand:AINT 1 "memory_operand" "")) ;; memory
5130 (use (match_operand:SI 2 "const_int_operand" ""))] ;; model
5131 ""
5132 {
5133 if (MEM_ADDR_SPACE (operands[1]))
5134 FAIL;
5135
5136 emit_move_insn (operands[0], operands[1]);
5137 DONE;
5138 })
5139
5140 (define_expand "atomic_store<mode>"
5141 [(set (match_operand:AINT 0 "memory_operand" "") ;; memory
5142 (match_operand:AINT 1 "spu_reg_operand" "")) ;; input
5143 (use (match_operand:SI 2 "const_int_operand" ""))] ;; model
5144 ""
5145 {
5146 if (MEM_ADDR_SPACE (operands[0]))
5147 FAIL;
5148
5149 emit_move_insn (operands[0], operands[1]);
5150 DONE;
5151 })
5152
5153 (define_expand "atomic_compare_and_swap<mode>"
5154 [(match_operand:SI 0 "spu_reg_operand" "") ;; bool out
5155 (match_operand:AINT 1 "spu_reg_operand" "") ;; val out
5156 (match_operand:AINT 2 "memory_operand" "") ;; memory
5157 (match_operand:AINT 3 "spu_nonmem_operand" "") ;; expected
5158 (match_operand:AINT 4 "spu_nonmem_operand" "") ;; desired
5159 (match_operand:SI 5 "const_int_operand" "") ;; is_weak
5160 (match_operand:SI 6 "const_int_operand" "") ;; model succ
5161 (match_operand:SI 7 "const_int_operand" "")] ;; model fail
5162 ""
5163 {
5164 rtx boolval, retval, label;
5165
5166 if (MEM_ADDR_SPACE (operands[2]))
5167 FAIL;
5168
5169 boolval = gen_reg_rtx (SImode);
5170 retval = gen_reg_rtx (<MODE>mode);
5171 label = gen_label_rtx ();
5172
5173 emit_move_insn (retval, operands[2]);
5174 emit_move_insn (boolval, const0_rtx);
5175
5176 emit_cmp_and_jump_insns (retval, operands[3], NE, NULL_RTX,
5177 <MODE>mode, 1, label);
5178
5179 emit_move_insn (operands[2], operands[4]);
5180 emit_move_insn (boolval, const1_rtx);
5181
5182 emit_label (label);
5183
5184 emit_move_insn (operands[0], boolval);
5185 emit_move_insn (operands[1], retval);
5186 DONE;
5187 })
5188
5189 (define_expand "atomic_exchange<mode>"
5190 [(match_operand:AINT 0 "spu_reg_operand" "") ;; output
5191 (match_operand:AINT 1 "memory_operand" "") ;; memory
5192 (match_operand:AINT 2 "spu_nonmem_operand" "") ;; input
5193 (match_operand:SI 3 "const_int_operand" "")] ;; model
5194 ""
5195 {
5196 rtx retval;
5197
5198 if (MEM_ADDR_SPACE (operands[1]))
5199 FAIL;
5200
5201 retval = gen_reg_rtx (<MODE>mode);
5202
5203 emit_move_insn (retval, operands[1]);
5204 emit_move_insn (operands[1], operands[2]);
5205 emit_move_insn (operands[0], retval);
5206 DONE;
5207 })
5208
5209 (define_expand "atomic_<atomic_name><mode>"
5210 [(ATOMIC:AINT
5211 (match_operand:AINT 0 "memory_operand" "") ;; memory
5212 (match_operand:AINT 1 "<atomic_pred>" "")) ;; operand
5213 (match_operand:SI 2 "const_int_operand" "")] ;; model
5214 ""
5215 {
5216 if (MEM_ADDR_SPACE (operands[0]))
5217 FAIL;
5218
5219 spu_expand_atomic_op (<CODE>, operands[0], operands[1],
5220 NULL_RTX, NULL_RTX);
5221 DONE;
5222 })
5223
5224 (define_expand "atomic_fetch_<atomic_name><mode>"
5225 [(match_operand:AINT 0 "spu_reg_operand" "") ;; output
5226 (ATOMIC:AINT
5227 (match_operand:AINT 1 "memory_operand" "") ;; memory
5228 (match_operand:AINT 2 "<atomic_pred>" "")) ;; operand
5229 (match_operand:SI 3 "const_int_operand" "")] ;; model
5230 ""
5231 {
5232 if (MEM_ADDR_SPACE (operands[1]))
5233 FAIL;
5234
5235 spu_expand_atomic_op (<CODE>, operands[1], operands[2],
5236 operands[0], NULL_RTX);
5237 DONE;
5238 })
5239
5240 (define_expand "atomic_<atomic_name>_fetch<mode>"
5241 [(match_operand:AINT 0 "spu_reg_operand" "") ;; output
5242 (ATOMIC:AINT
5243 (match_operand:AINT 1 "memory_operand" "") ;; memory
5244 (match_operand:AINT 2 "<atomic_pred>" "")) ;; operand
5245 (match_operand:SI 3 "const_int_operand" "")] ;; model
5246 ""
5247 {
5248 if (MEM_ADDR_SPACE (operands[1]))
5249 FAIL;
5250
5251 spu_expand_atomic_op (<CODE>, operands[1], operands[2],
5252 NULL_RTX, operands[0]);
5253 DONE;
5254 })
5255