CbC/CbC_gcc: gcc/doc/rtl.texi comparison

comparison gcc/doc/rtl.texi @ 111:04ced10e8804

gcc 7

author	kono
date	Fri, 27 Oct 2017 22:46:09 +0900
parents	f6334be47118
children	84e7813d76e9

comparison

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-:561a7518be6b
+:04ced10e8804
-@c Copyright (C) 1988, 1989, 1992, 1994, 1997, 1998, 1999, 2000, 2001, 2002,
+@c Copyright (C) 1988-2017 Free Software Foundation, Inc.
-@c 2003, 2004, 2005, 2006, 2007, 2008, 2010
-@c Free Software Foundation, Inc.
 @c This is part of the GCC manual.
 @c For copying conditions, see the file gcc.texi.
 @node RTL
 @chapter RTL Representation
 An RTX code for something that matches in insns, such as
 @code{MATCH_DUP}.  These only occur in machine descriptions.
 @item RTX_AUTOINC
 An RTX code for an auto-increment addressing mode, such as
-@code{POST_INC}.
+@code{POST_INC}.  @samp{XEXP (@var{x}, 0)} gives the auto-modified
+register.
 @item RTX_EXTRA
 All other RTX codes.  This category includes the remaining codes used
 only in machine descriptions (@code{DEFINE_*}, etc.).  It also includes
 all the codes describing side effects (@code{SET}, @code{USE},
 @code{COMPONENT_REF}, in which case this is some field reference,
 and @code{TREE_OPERAND (@var{x}, 0)} contains the declaration,
 or another @code{COMPONENT_REF}, or null if there is no compile-time
 object associated with the reference.
+@findex MEM_OFFSET_KNOWN_P
+@item MEM_OFFSET_KNOWN_P (@var{x})
+True if the offset of the memory reference from @code{MEM_EXPR} is known.
+@samp{MEM_OFFSET (@var{x})} provides the offset if so.
 @findex MEM_OFFSET
 @item MEM_OFFSET (@var{x})
-The offset from the start of @code{MEM_EXPR} as a @code{CONST_INT} rtx.
+The offset from the start of @code{MEM_EXPR}.  The value is only valid if
+@samp{MEM_OFFSET_KNOWN_P (@var{x})} is true.
+@findex MEM_SIZE_KNOWN_P
+@item MEM_SIZE_KNOWN_P (@var{x})
+True if the size of the memory reference is known.
+@samp{MEM_SIZE (@var{x})} provides its size if so.
 @findex MEM_SIZE
 @item MEM_SIZE (@var{x})
-The size in bytes of the memory reference as a @code{CONST_INT} rtx.
+The size in bytes of the memory reference.
 This is mostly relevant for @code{BLKmode} references as otherwise
-the size is implied by the mode.
+the size is implied by the mode.  The value is only valid if
+@samp{MEM_SIZE_KNOWN_P (@var{x})} is true.
 @findex MEM_ALIGN
 @item MEM_ALIGN (@var{x})
 The known alignment in bits of the memory reference.
 @findex INSN_DELETED_P
 @cindex @code{insn} and @samp{/v}
 @cindex @code{call_insn} and @samp{/v}
 @cindex @code{jump_insn} and @samp{/v}
 @cindex @code{code_label} and @samp{/v}
+@cindex @code{jump_table_data} and @samp{/v}
 @cindex @code{barrier} and @samp{/v}
 @cindex @code{note} and @samp{/v}
-@cindex @code{volatil}, in @code{insn}, @code{call_insn}, @code{jump_insn}, @code{code_label}, @code{barrier}, and @code{note}
+@cindex @code{volatil}, in @code{insn}, @code{call_insn}, @code{jump_insn}, @code{code_label}, @code{jump_table_data}, @code{barrier}, and @code{note}
 @item INSN_DELETED_P (@var{x})
 In an @code{insn}, @code{call_insn}, @code{jump_insn}, @code{code_label},
-@code{barrier}, or @code{note},
+@code{jump_table_data}, @code{barrier}, or @code{note},
 nonzero if the insn has been deleted.  Stored in the
 @code{volatil} field and printed as @samp{/v}.
 @findex INSN_FROM_TARGET_P
 @cindex @code{insn} and @samp{/s}
 @item LABEL_REF_NONLOCAL_P (@var{x})
 In @code{label_ref} and @code{reg_label} expressions, nonzero if this is
 a reference to a non-local label.
 Stored in the @code{volatil} field and printed as @samp{/v}.
-@findex MEM_IN_STRUCT_P
-@cindex @code{mem} and @samp{/s}
-@cindex @code{in_struct}, in @code{mem}
-@item MEM_IN_STRUCT_P (@var{x})
-In @code{mem} expressions, nonzero for reference to an entire structure,
-union or array, or to a component of one.  Zero for references to a
-scalar variable or through a pointer to a scalar.  If both this flag and
-@code{MEM_SCALAR_P} are clear, then we don't know whether this @code{mem}
-is in a structure or not.  Both flags should never be simultaneously set.
-Stored in the @code{in_struct} field and printed as @samp{/s}.
 @findex MEM_KEEP_ALIAS_SET_P
 @cindex @code{mem} and @samp{/j}
 @cindex @code{jump}, in @code{mem}
 @item MEM_KEEP_ALIAS_SET_P (@var{x})
 In @code{mem} expressions, 1 if we should keep the alias set for this
 mem unchanged when we access a component.  Set to 1, for example, when we
 are already in a non-addressable component of an aggregate.
 Stored in the @code{jump} field and printed as @samp{/j}.
-@findex MEM_SCALAR_P
-@cindex @code{mem} and @samp{/i}
-@cindex @code{return_val}, in @code{mem}
-@item MEM_SCALAR_P (@var{x})
-In @code{mem} expressions, nonzero for reference to a scalar known not
-to be a member of a structure, union, or array.  Zero for such
-references and for indirections through pointers, even pointers pointing
-to scalar types.  If both this flag and @code{MEM_IN_STRUCT_P} are clear,
-then we don't know whether this @code{mem} is in a structure or not.
-Both flags should never be simultaneously set.
-Stored in the @code{return_val} field and printed as @samp{/i}.
 @findex MEM_VOLATILE_P
 @cindex @code{mem} and @samp{/v}
 @cindex @code{asm_input} and @samp{/v}
 @cindex @code{asm_operands} and @samp{/v}
 Read-only in this context means never modified during the lifetime of the
 program, not necessarily in ROM or in write-disabled pages.  A common
 example of the later is a shared library's global offset table.  This
 table is initialized by the runtime loader, so the memory is technically
-writable, but after control is transfered from the runtime loader to the
+writable, but after control is transferred from the runtime loader to the
 application, this memory will never be subsequently modified.
 Stored in the @code{unchanging} field and printed as @samp{/u}.
 @findex SCHED_GROUP_P
 @cindex @code{insn} and @samp{/s}
 @cindex @code{call_insn} and @samp{/s}
 @cindex @code{jump_insn} and @samp{/s}
-@cindex @code{in_struct}, in @code{insn}, @code{jump_insn} and @code{call_insn}
+@cindex @code{jump_table_data} and @samp{/s}
+@cindex @code{in_struct}, in @code{insn}, @code{call_insn}, @code{jump_insn} and @code{jump_table_data}
 @item SCHED_GROUP_P (@var{x})
-During instruction scheduling, in an @code{insn}, @code{call_insn} or
+During instruction scheduling, in an @code{insn}, @code{call_insn},
-@code{jump_insn}, indicates that the
+@code{jump_insn} or @code{jump_table_data}, indicates that the
 previous insn must be scheduled together with this insn.  This is used to
 ensure that certain groups of instructions will not be split up by the
 instruction scheduling pass, for example, @code{use} insns before
 a @code{call_insn} may not be separated from the @code{call_insn}.
 Stored in the @code{in_struct} field and printed as @samp{/s}.
 In an RTL dump, this flag is represented as @samp{/f}.
 @findex in_struct
 @cindex @samp{/s} in RTL dump
 @item in_struct
-In @code{mem} expressions, it is 1 if the memory datum referred to is
-all or part of a structure or array; 0 if it is (or might be) a scalar
-variable.  A reference through a C pointer has 0 because the pointer
-might point to a scalar variable.  This information allows the compiler
-to determine something about possible cases of aliasing.
 In @code{reg} expressions, it is 1 if the register has its entire life
 contained within the test expression of some loop.
 In @code{subreg} expressions, 1 means that the @code{subreg} is accessing
 an object that has had its mode promoted from a wider mode.
 the value to be returned by the current function.  On
 machines that pass parameters in registers, the same register number
 may be used for parameters as well, but this flag is not set on such
 uses.
-In @code{mem} expressions, 1 means the memory reference is to a scalar
-known not to be a member of a structure, union, or array.
 In @code{symbol_ref} expressions, 1 means the referenced symbol is weak.
 In @code{call} expressions, 1 means the call is pure.
 In an RTL dump, this flag is represented as @samp{/i}.
 @node Machine Modes
 @section Machine Modes
 @cindex machine modes
-@findex enum machine_mode
+@findex machine_mode
 A machine mode describes a size of data object and the representation used
 for it.  In the C code, machine modes are represented by an enumeration
-type, @code{enum machine_mode}, defined in @file{machmode.def}.  Each RTL
+type, @code{machine_mode}, defined in @file{machmode.def}.  Each RTL
 expression has room for a machine mode and so do certain kinds of tree
 expressions (declarations and types, to be precise).
 In debugging dumps and machine descriptions, the machine mode of an RTL
 expression is written after the expression code with a colon to separate
 ``Tetra Integer'' (?) mode represents a sixteen-byte integer.
 @findex OImode
 @item OImode
 ``Octa Integer'' (?) mode represents a thirty-two-byte integer.
+@findex XImode
+@item XImode
+``Hexadeca Integer'' (?) mode represents a sixty-four-byte integer.
 @findex QFmode
 @item QFmode
 ``Quarter-Floating'' mode represents a quarter-precision (single byte)
 floating point number.
 @item CQImode, CHImode, CSImode, CDImode, CTImode, COImode
 These modes stand for a complex number represented as a pair of integer
 values.  The integer values are in @code{QImode}, @code{HImode},
 @code{SImode}, @code{DImode}, @code{TImode}, and @code{OImode},
 respectively.
+@findex BND32mode
+@findex BND64mode
+@item BND32mode BND64mode
+These modes stand for bounds for pointer of 32 and 64 bit size respectively.
+Mode size is double pointer mode size.
 @end table
 The machine description defines @code{Pmode} as a C macro which expands
 into the machine mode used for addresses.  Normally this is the mode
 whose size is @code{BITS_PER_WORD}, @code{SImode} on 32-bit machines.
 (These are not currently implemented).
 @findex MODE_CC
 @item MODE_CC
 Modes representing condition code values.  These are @code{CCmode} plus
 any @code{CC_MODE} modes listed in the @file{@var{machine}-modes.def}.
 @xref{Jump Patterns},
 also see @ref{Condition Code}.
+@findex MODE_POINTER_BOUNDS
+@item MODE_POINTER_BOUNDS
+Pointer bounds modes.  Used to represent values of pointer bounds type.
+Operations in these modes may be executed as NOPs depending on hardware
+features and environment setup.
 @findex MODE_RANDOM
 @item MODE_RANDOM
 This is a catchall mode class for modes which don't fit into the above
 classes.  Currently @code{VOIDmode} and @code{BLKmode} are in
 @findex GET_CLASS_NARROWEST_MODE
 @item GET_CLASS_NARROWEST_MODE (@var{c})
 Returns the narrowest mode in mode class @var{c}.
 @end table
+The following 3 variables are defined on every target.   They can be
+used to allocate buffers that are guaranteed to be large enough to
+hold any value that can be represented on the target.   The first two
+can be overridden by defining them in the target's mode.def file,
+however, the value must be a constant that can determined very early
+in the compilation process.   The third symbol cannot be overridden.
+@table @code
+@findex BITS_PER_UNIT
+@item BITS_PER_UNIT
+The number of bits in an addressable storage unit (byte).  If you do
+not define this, the default is 8.
+@findex MAX_BITSIZE_MODE_ANY_INT
+@item MAX_BITSIZE_MODE_ANY_INT
+The maximum bitsize of any mode that is used in integer math.  This
+should be overridden by the target if it uses large integers as
+containers for larger vectors but otherwise never uses the contents to
+compute integer values.
+@findex MAX_BITSIZE_MODE_ANY_MODE
+@item MAX_BITSIZE_MODE_ANY_MODE
+The bitsize of the largest mode on the target.
+@end table
 @findex byte_mode
 @findex word_mode
 The global variables @code{byte_mode} and @code{word_mode} contain modes
 whose classes are @code{MODE_INT} and whose bitsizes are either
 @code{BITS_PER_UNIT} or @code{BITS_PER_WORD}, respectively.  On 32-bit
 @item (const_int @var{i})
 This type of expression represents the integer value @var{i}.  @var{i}
 is customarily accessed with the macro @code{INTVAL} as in
 @code{INTVAL (@var{exp})}, which is equivalent to @code{XWINT (@var{exp}, 0)}.
-Constants generated for modes with fewer bits than @code{HOST_WIDE_INT}
+Constants generated for modes with fewer bits than in
-must be sign extended to full width (e.g., with @code{gen_int_mode}).
+@code{HOST_WIDE_INT} must be sign extended to full width (e.g., with
+@code{gen_int_mode}).  For constants for modes with more bits than in
+@code{HOST_WIDE_INT} the implied high order bits of that constant are
+copies of the top bit.  Note however that values are neither
+inherently signed nor inherently unsigned; where necessary, signedness
+is determined by the rtl operation instead.
 @findex const0_rtx
 @findex const1_rtx
 @findex const2_rtx
 @findex constm1_rtx
 @code{STORE_FLAG_VALUE} is @minus{}1, @code{const_true_rtx} and
 @code{constm1_rtx} will point to the same object.
 @findex const_double
 @item (const_double:@var{m} @var{i0} @var{i1} @dots{})
-Represents either a floating-point constant of mode @var{m} or an
+This represents either a floating-point constant of mode @var{m} or
-integer constant too large to fit into @code{HOST_BITS_PER_WIDE_INT}
+(on older ports that do not define
-bits but small enough to fit within twice that number of bits (GCC
+@code{TARGET_SUPPORTS_WIDE_INT}) an integer constant too large to fit
-does not provide a mechanism to represent even larger constants).  In
+into @code{HOST_BITS_PER_WIDE_INT} bits but small enough to fit within
-the latter case, @var{m} will be @code{VOIDmode}.
+twice that number of bits.  In the latter case, @var{m} will be
+@code{VOIDmode}.  For integral values constants for modes with more
+bits than twice the number in @code{HOST_WIDE_INT} the implied high
+order bits of that constant are copies of the top bit of
+@code{CONST_DOUBLE_HIGH}.  Note however that integral values are
+neither inherently signed nor inherently unsigned; where necessary,
+signedness is determined by the rtl operation instead.
+On more modern ports, @code{CONST_DOUBLE} only represents floating
+point values.  New ports define @code{TARGET_SUPPORTS_WIDE_INT} to
+make this designation.
 @findex CONST_DOUBLE_LOW
 If @var{m} is @code{VOIDmode}, the bits of the value are stored in
 @var{i0} and @var{i1}.  @var{i0} is customarily accessed with the macro
 @code{CONST_DOUBLE_LOW} and @var{i1} with @code{CONST_DOUBLE_HIGH}.
 @code{REAL_VALUE_TYPE} (@pxref{Floating Point}).  The integers
 represent a floating point number, but not precisely in the target
 machine's or host machine's floating point format.  To convert them to
 the precise bit pattern used by the target machine, use the macro
 @code{REAL_VALUE_TO_TARGET_DOUBLE} and friends (@pxref{Data Output}).
+@findex CONST_WIDE_INT
+@item (const_wide_int:@var{m} @var{nunits} @var{elt0} @dots{})
+This contains an array of @code{HOST_WIDE_INT}s that is large enough
+to hold any constant that can be represented on the target.  This form
+of rtl is only used on targets that define
+@code{TARGET_SUPPORTS_WIDE_INT} to be nonzero and then
+@code{CONST_DOUBLE}s are only used to hold floating-point values.  If
+the target leaves @code{TARGET_SUPPORTS_WIDE_INT} defined as 0,
+@code{CONST_WIDE_INT}s are not used and @code{CONST_DOUBLE}s are as
+they were before.
+The values are stored in a compressed format.  The higher-order
+0s or -1s are not represented if they are just the logical sign
+extension of the number that is represented.
+@findex CONST_WIDE_INT_VEC
+@item CONST_WIDE_INT_VEC (@var{code})
+Returns the entire array of @code{HOST_WIDE_INT}s that are used to
+store the value.  This macro should be rarely used.
+@findex CONST_WIDE_INT_NUNITS
+@item CONST_WIDE_INT_NUNITS (@var{code})
+The number of @code{HOST_WIDE_INT}s used to represent the number.
+Note that this generally is smaller than the number of
+@code{HOST_WIDE_INT}s implied by the mode size.
+@findex CONST_WIDE_INT_ELT
+@item CONST_WIDE_INT_NUNITS (@var{code},@var{i})
+Returns the @code{i}th element of the array.   Element 0 is contains
+the low order bits of the constant.
 @findex const_fixed
 @item (const_fixed:@var{m} @dots{})
 Represents a fixed-point constant of mode @var{m}.
 The operand is a data structure of type @code{struct fixed_value} and
 @item VIRTUAL_STACK_VARS_REGNUM
 If @code{FRAME_GROWS_DOWNWARD} is defined to a nonzero value, this points
 to immediately above the first variable on the stack.  Otherwise, it points
 to the first variable on the stack.
-@cindex @code{STARTING_FRAME_OFFSET} and virtual registers
+@cindex @code{TARGET_STARTING_FRAME_OFFSET} and virtual registers
 @cindex @code{FRAME_POINTER_REGNUM} and virtual registers
 @code{VIRTUAL_STACK_VARS_REGNUM} is replaced with the sum of the
 register given by @code{FRAME_POINTER_REGNUM} and the value
-@code{STARTING_FRAME_OFFSET}.
+@code{TARGET_STARTING_FRAME_OFFSET}.
 @findex VIRTUAL_STACK_DYNAMIC_REGNUM
 @item VIRTUAL_STACK_DYNAMIC_REGNUM
 This points to the location of dynamically allocated memory on the stack
 immediately after the stack pointer has been adjusted by the amount of
 mode other than its natural one, or to refer to one register of
 a multi-part @code{reg} that actually refers to several registers.
 Each pseudo register has a natural mode.  If it is necessary to
 operate on it in a different mode, the register must be
 enclosed in a @code{subreg}.
 There are currently three supported types for the first operand of a
 @code{subreg}:
 @itemize
 @item pseudo registers
 When @var{m1} is strictly wider than @var{m2}, the @code{subreg}
 expression is called @dfn{paradoxical}.  The canonical test for this
 class of @code{subreg} is:
 @smallexample
-GET_MODE_SIZE (@var{m1}) > GET_MODE_SIZE (@var{m2})
+paradoxical_subreg_p (@var{m1}, @var{m2})
 @end smallexample
 Paradoxical @code{subreg}s can be used as both lvalues and rvalues.
 When used as an lvalue, the low-order bits of the source value
 are stored in @var{reg} and the high-order bits are discarded.
 When used as an rvalue, the low-order bits of the @code{subreg} are
 taken from @var{reg} while the high-order bits may or may not be
 defined.
-The high-order bits of rvalues are in the following circumstances:
+The high-order bits of rvalues are defined in the following circumstances:
 @itemize
 @item @code{subreg}s of @code{mem}
 When @var{m2} is smaller than a word, the macro @code{LOAD_EXTEND_OP},
 can control how the high-order bits are defined.
 would set the lower two bytes of @var{z} to @var{y} and set the upper
 two bytes to an unknown value assuming @code{SUBREG_PROMOTED_VAR_P} is
 false.
 @item Normal subregs
 When @var{m1} is at least as narrow as @var{m2} the @code{subreg}
 expression is called @dfn{normal}.
 Normal @code{subreg}s restrict consideration to certain bits of
 @var{reg}.  There are two cases.  If @var{m1} is smaller than a word,
 floating point values as if they had the same endianness as integer
 values.  This works because they handle them solely as a collection of
 integer values, with no particular numerical value.  Only real.c and
 the runtime libraries care about @code{FLOAT_WORDS_BIG_ENDIAN}.
 Thus,
 @smallexample
 (subreg:HI (reg:SI @var{x}) 2)
 @end smallexample
 @end smallexample
 does not guarantee that @samp{(subreg:HI (reg:PSI 0) 0)} has the
 value @samp{(reg:HI 4)}.
-@cindex @code{CANNOT_CHANGE_MODE_CLASS} and subreg semantics
+@cindex @code{TARGET_CAN_CHANGE_MODE_CLASS} and subreg semantics
 The rules above apply to both pseudo @var{reg}s and hard @var{reg}s.
 If the semantics are not correct for particular combinations of
 @var{m1}, @var{m2} and hard @var{reg}, the target-specific code
 must ensure that those combinations are never used.  For example:
 @smallexample
-CANNOT_CHANGE_MODE_CLASS (@var{m2}, @var{m1}, @var{class})
+TARGET_CAN_CHANGE_MODE_CLASS (@var{m2}, @var{m1}, @var{class})
 @end smallexample
-must be true for every class @var{class} that includes @var{reg}.
+must be false for every class @var{class} that includes @var{reg}.
 @findex SUBREG_REG
 @findex SUBREG_BYTE
 The first operand of a @code{subreg} expression is customarily accessed
 with the @code{SUBREG_REG} macro and the second operand is customarily
 @item (compare:@var{m} @var{x} @var{y})
 Represents the result of subtracting @var{y} from @var{x} for purposes
 of comparison.  The result is computed without overflow, as if with
 infinite precision.
-Of course, machines can't really subtract with infinite precision.
+Of course, machines cannot really subtract with infinite precision.
 However, they can pretend to do so when only the sign of the result will
 be used, which is the case when the result is stored in the condition
 code.  And that is the @emph{only} way this kind of expression may
 validly be used: as a value to be stored in the condition codes, either
 @code{(cc0)} or a register.  @xref{Comparisons}.
 @code{zero_extend} instead of @code{sign_extend}.
 @findex fma
 @item (fma:@var{m} @var{x} @var{y} @var{z})
 Represents the @code{fma}, @code{fmaf}, and @code{fmal} builtin
-functions that do a combined multiply of @var{x} and @var{y} and then
+functions, which compute @samp{@var{x} * @var{y} + @var{z}}
-adding to@var{z} without doing an intermediate rounding step.
+without doing an intermediate rounding step.
 @findex div
 @findex ss_div
 @cindex division
 @cindex signed division
 @findex ffs
 @item (ffs:@var{m} @var{x})
 Represents one plus the index of the least significant 1-bit in
 @var{x}, represented as an integer of mode @var{m}.  (The value is
-zero if @var{x} is zero.)  The mode of @var{x} need not be @var{m};
+zero if @var{x} is zero.)  The mode of @var{x} must be @var{m}
-depending on the target machine, various mode combinations may be
+or @code{VOIDmode}.
-valid.
+@findex clrsb
+@item (clrsb:@var{m} @var{x})
+Represents the number of redundant leading sign bits in @var{x},
+represented as an integer of mode @var{m}, starting at the most
+significant bit position.  This is one less than the number of leading
+sign bits (either 0 or 1), with no special cases.  The mode of @var{x}
+must be @var{m} or @code{VOIDmode}.
 @findex clz
 @item (clz:@var{m} @var{x})
 Represents the number of leading 0-bits in @var{x}, represented as an
 integer of mode @var{m}, starting at the most significant bit position.
 If @var{x} is zero, the value is determined by
 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}).  Note that this is one of
 the few expressions that is not invariant under widening.  The mode of
-@var{x} will usually be an integer mode.
+@var{x} must be @var{m} or @code{VOIDmode}.
 @findex ctz
 @item (ctz:@var{m} @var{x})
 Represents the number of trailing 0-bits in @var{x}, represented as an
 integer of mode @var{m}, starting at the least significant bit position.
 If @var{x} is zero, the value is determined by
 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}).  Except for this case,
 @code{ctz(x)} is equivalent to @code{ffs(@var{x}) - 1}.  The mode of
-@var{x} will usually be an integer mode.
+@var{x} must be @var{m} or @code{VOIDmode}.
 @findex popcount
 @item (popcount:@var{m} @var{x})
 Represents the number of 1-bits in @var{x}, represented as an integer of
-mode @var{m}.  The mode of @var{x} will usually be an integer mode.
+mode @var{m}.  The mode of @var{x} must be @var{m} or @code{VOIDmode}.
 @findex parity
 @item (parity:@var{m} @var{x})
 Represents the number of 1-bits modulo 2 in @var{x}, represented as an
-integer of mode @var{m}.  The mode of @var{x} will usually be an integer
+integer of mode @var{m}.  The mode of @var{x} must be @var{m} or
-mode.
+@code{VOIDmode}.
 @findex bswap
 @item (bswap:@var{m} @var{x})
 Represents the value @var{x} with the order of bytes reversed, carried out
 in mode @var{m}, which must be a fixed-point machine mode.
+The mode of @var{x} must be @var{m} or @code{VOIDmode}.
 @end table
 @node Comparisons
 @section Comparison Operations
 @cindex RTL comparison operations
 @findex vec_select
 @item (vec_select:@var{m} @var{vec1} @var{selection})
 This describes an operation that selects parts of a vector.  @var{vec1} is
 the source vector, and @var{selection} is a @code{parallel} that contains a
 @code{const_int} for each of the subparts of the result vector, giving the
 number of the source subpart that should be stored into it.
 The result mode @var{m} is either the submode for a single element of
 @var{vec1} (if only one subpart is selected), or another vector mode
 with that element submode (if multiple subparts are selected).
 @findex vec_concat
-@item (vec_concat:@var{m} @var{vec1} @var{vec2})
+@item (vec_concat:@var{m} @var{x1} @var{x2})
 Describes a vector concat operation.  The result is a concatenation of the
-vectors @var{vec1} and @var{vec2}; its length is the sum of the lengths of
+vectors or scalars @var{x1} and @var{x2}; its length is the sum of the
-the two inputs.
+lengths of the two inputs.
 @findex vec_duplicate
-@item (vec_duplicate:@var{m} @var{vec})
+@item (vec_duplicate:@var{m} @var{x})
-This operation converts a small vector into a larger one by duplicating the
+This operation converts a scalar into a vector or a small vector into a
-input values.  The output vector mode must have the same submodes as the
+larger one by duplicating the input values.  The output vector mode must have
-input vector mode, and the number of output parts must be an integer multiple
+the same submodes as the input vector mode or the scalar modes, and the
-of the number of input parts.
+number of output parts must be an integer multiple of the number of input
+parts.
 @end table
 @node Conversions
 @section Conversions
 placed in @code{pc} to return to the caller.
 Note that an insn pattern of @code{(return)} is logically equivalent to
 @code{(set (pc) (return))}, but the latter form is never used.
+@findex simple_return
+@item (simple_return)
+Like @code{(return)}, but truly represents only a function return, while
+@code{(return)} may represent an insn that also performs other functions
+of the function epilogue.  Like @code{(return)}, this may also occur in
+conditional jumps.
 @findex call
 @item (call @var{function} @var{nargs})
 Represents a function call.  @var{function} is a @code{mem} expression
 whose address is the address of the function to be called.
 @var{nargs} is an expression which can be used for two purposes: on
 @item (parallel [@var{x0} @var{x1} @dots{}])
 Represents several side effects performed in parallel.  The square
 brackets stand for a vector; the operand of @code{parallel} is a
 vector of expressions.  @var{x0}, @var{x1} and so on are individual
 side effect expressions---expressions of code @code{set}, @code{call},
-@code{return}, @code{clobber} or @code{use}.
+@code{return}, @code{simple_return}, @code{clobber} or @code{use}.
 ``In parallel'' means that first all the values used in the individual
 side-effects are computed, and second all the actual side-effects are
 performed.  For example,
 Peephole optimization, which takes place together with final assembly
 code output, can produce insns whose patterns consist of a @code{parallel}
 whose elements are the operands needed to output the resulting
 assembler code---often @code{reg}, @code{mem} or constant expressions.
 This would not be well-formed RTL at any other stage in compilation,
-but it is ok then because no further optimization remains to be done.
+but it is OK then because no further optimization remains to be done.
 However, the definition of the macro @code{NOTICE_UPDATE_CC}, if
 any, must deal with such insns if you define any peephole optimizations.
 @findex cond_exec
 @item (cond_exec [@var{cond} @var{expr}])
 must not have side-effects, but the @var{expr} may very well have
 side-effects.
 @findex sequence
 @item (sequence [@var{insns} @dots{}])
-Represents a sequence of insns.  Each of the @var{insns} that appears
+Represents a sequence of insns.  If a @code{sequence} appears in the
-in the vector is suitable for appearing in the chain of insns, so it
+chain of insns, then each of the @var{insns} that appears in the sequence
-must be an @code{insn}, @code{jump_insn}, @code{call_insn},
+must be suitable for appearing in the chain of insns, i.e. must satisfy
-@code{code_label}, @code{barrier} or @code{note}.
+the @code{INSN_P} predicate.
-A @code{sequence} RTX is never placed in an actual insn during RTL
-generation.  It represents the sequence of insns that result from a
-@code{define_expand} @emph{before} those insns are passed to
-@code{emit_insn} to insert them in the chain of insns.  When actually
-inserted, the individual sub-insns are separated out and the
-@code{sequence} is forgotten.
 After delay-slot scheduling is completed, an insn and all the insns that
 reside in its delay slots are grouped together into a @code{sequence}.
 The insn requiring the delay slot is the first insn in the vector;
 subsequent insns are to be placed in the delay slot.
 the effect of the insns in the delay slots.  In such a case,
 @code{INSN_FROM_TARGET_P} indicates that the insn is from the target of
 the branch and should be executed only if the branch is taken; otherwise
 the insn should be executed only if the branch is not taken.
 @xref{Delay Slots}.
+Some back ends also use @code{sequence} objects for purposes other than
+delay-slot groups.  This is not supported in the common parts of the
+compiler, which treat such sequences as delay-slot groups.
+DWARF2 Call Frame Address (CFA) adjustments are sometimes also expressed
+using @code{sequence} objects as the value of a @code{RTX_FRAME_RELATED_P}
+note.  This only happens if the CFA adjustments cannot be easily derived
+from the pattern of the instruction to which the note is attached.  In
+such cases, the value of the note is used instead of best-guesing the
+semantics of the instruction.  The back end can attach notes containing
+a @code{sequence} of @code{set} patterns that express the effect of the
+parent instruction.
 @end table
 These expression codes appear in place of a side effect, as the body of
 an insn, though strictly speaking they do not always describe side
 effects as such:
 as @code{REG_LABEL_TARGET} notes.  The exception is @code{addr_vec}
 and @code{addr_diff_vec}, where @code{JUMP_LABEL} is @code{NULL_RTX}
 and the only way to find the labels is to scan the entire body of the
 insn.
-Return insns count as jumps, but since they do not refer to any
+Return insns count as jumps, but their @code{JUMP_LABEL} is @code{RETURN}
-labels, their @code{JUMP_LABEL} is @code{NULL_RTX}.
+or @code{SIMPLE_RETURN}.
 @findex call_insn
 @item call_insn
 The expression code @code{call_insn} is used for instructions that may do
 function calls.  It is important to distinguish these instructions because
 @findex CALL_INSN_FUNCTION_USAGE
 @code{call_insn} insns have the same extra fields as @code{insn} insns,
 accessed in the same way and in addition contain a field
 @code{CALL_INSN_FUNCTION_USAGE}, which contains a list (chain of
-@code{expr_list} expressions) containing @code{use} and @code{clobber}
+@code{expr_list} expressions) containing @code{use}, @code{clobber} and
-expressions that denote hard registers and @code{MEM}s used or
+sometimes @code{set} expressions that denote hard registers and
-clobbered by the called function.
+@code{mem}s used or clobbered by the called function.
-A @code{MEM} generally points to a stack slots in which arguments passed
+A @code{mem} generally points to a stack slot in which arguments passed
 to the libcall by reference (@pxref{Register Arguments,
 TARGET_PASS_BY_REFERENCE}) are stored.  If the argument is
 caller-copied (@pxref{Register Arguments, TARGET_CALLEE_COPIES}),
-the stack slot will be mentioned in @code{CLOBBER} and @code{USE}
+the stack slot will be mentioned in @code{clobber} and @code{use}
-entries; if it's callee-copied, only a @code{USE} will appear, and the
+entries; if it's callee-copied, only a @code{use} will appear, and the
-@code{MEM} may point to addresses that are not stack slots.
+@code{mem} may point to addresses that are not stack slots.
-@code{CLOBBER}ed registers in this list augment registers specified in
+Registers occurring inside a @code{clobber} in this list augment
-@code{CALL_USED_REGISTERS} (@pxref{Register Basics}).
+registers specified in @code{CALL_USED_REGISTERS} (@pxref{Register
+Basics}).
+If the list contains a @code{set} involving two registers, it indicates
+that the function returns one of its arguments.  Such a @code{set} may
+look like a no-op if the same register holds the argument and the return
+value.
 @findex code_label
 @findex CODE_LABEL_NUMBER
 @item code_label
 A @code{code_label} insn represents a label that a jump insn can jump
 them, is the function @code{output_alternate_entry_point}, in
 @file{final.c}.
 To set the kind of a label, use the @code{SET_LABEL_KIND} macro.
+@findex jump_table_data
+@item jump_table_data
+A @code{jump_table_data} insn is a placeholder for the jump-table data
+of a @code{casesi} or @code{tablejump} insn.  They are placed after
+a @code{tablejump_p} insn.  A @code{jump_table_data} insn is not part o
+a basic blockm but it is associated with the basic block that ends with
+the @code{tablejump_p} insn.  The @code{PATTERN} of a @code{jump_table_data}
+is always either an @code{addr_vec} or an @code{addr_diff_vec}, and a
+@code{jump_table_data} insn is always preceded by a @code{code_label}.
+The @code{tablejump_p} insn refers to that @code{code_label} via its
+@code{JUMP_LABEL}.
 @findex barrier
 @item barrier
 Barriers are placed in the instruction stream when control cannot flow
 past them.  They are placed after unconditional jump instructions to
 indicate that the jumps are unconditional and after calls to
 @findex NOTE_INSN_EH_REGION_BEG
 @findex NOTE_INSN_EH_REGION_END
 @item NOTE_INSN_EH_REGION_BEG
 @itemx NOTE_INSN_EH_REGION_END
 These types of notes indicate the position of the beginning and end of a
-level of scoping for exception handling.  @code{NOTE_BLOCK_NUMBER}
+level of scoping for exception handling.  @code{NOTE_EH_HANDLER}
-identifies which @code{CODE_LABEL} or @code{note} of type
+identifies which region is associated with these notes.
-@code{NOTE_INSN_DELETED_LABEL} is associated with the given region.
-@findex NOTE_INSN_LOOP_BEG
-@findex NOTE_INSN_LOOP_END
-@item NOTE_INSN_LOOP_BEG
-@itemx NOTE_INSN_LOOP_END
-These types of notes indicate the position of the beginning and end
-of a @code{while} or @code{for} loop.  They enable the loop optimizer
-to find loops quickly.
-@findex NOTE_INSN_LOOP_CONT
-@item NOTE_INSN_LOOP_CONT
-Appears at the place in a loop that @code{continue} statements jump to.
-@findex NOTE_INSN_LOOP_VTOP
-@item NOTE_INSN_LOOP_VTOP
-This note indicates the place in a loop where the exit test begins for
-those loops in which the exit test has been duplicated.  This position
-becomes another virtual start of the loop when considering loop
-invariants.
 @findex NOTE_INSN_FUNCTION_BEG
 @item NOTE_INSN_FUNCTION_BEG
 Appears at the start of the function body, after the function
 prologue.
 and @code{call_insn} insns:
 @table @code
 @findex PATTERN
 @item PATTERN (@var{i})
-An expression for the side effect performed by this insn.  This must be
+An expression for the side effect performed by this insn.  This must
-one of the following codes: @code{set}, @code{call}, @code{use},
+be one of the following codes: @code{set}, @code{call}, @code{use},
-@code{clobber}, @code{return}, @code{asm_input}, @code{asm_output},
+@code{clobber}, @code{return}, @code{simple_return}, @code{asm_input},
-@code{addr_vec}, @code{addr_diff_vec}, @code{trap_if}, @code{unspec},
+@code{asm_output}, @code{addr_vec}, @code{addr_diff_vec},
-@code{unspec_volatile}, @code{parallel}, @code{cond_exec}, or @code{sequence}.  If it is a @code{parallel},
+@code{trap_if}, @code{unspec}, @code{unspec_volatile},
-each element of the @code{parallel} must be one these codes, except that
+@code{parallel}, @code{cond_exec}, or @code{sequence}.  If it is a
-@code{parallel} expressions cannot be nested and @code{addr_vec} and
+@code{parallel}, each element of the @code{parallel} must be one these
-@code{addr_diff_vec} are not permitted inside a @code{parallel} expression.
+codes, except that @code{parallel} expressions cannot be nested and
+@code{addr_vec} and @code{addr_diff_vec} are not permitted inside a
+@code{parallel} expression.
 @findex INSN_CODE
 @item INSN_CODE (@var{i})
 An integer that says which pattern in the machine description matches
 this insn, or @minus{}1 if the matching has not yet been attempted.
 @item LOG_LINKS (@var{i})
 A list (chain of @code{insn_list} expressions) giving information about
 dependencies between instructions within a basic block.  Neither a jump
 nor a label may come between the related insns.  These are only used by
 the schedulers and by combine.  This is a deprecated data structure.
 Def-use and use-def chains are now preferred.
 @findex REG_NOTES
 @item REG_NOTES (@var{i})
-A list (chain of @code{expr_list} and @code{insn_list} expressions)
+A list (chain of @code{expr_list}, @code{insn_list} and @code{int_list}
-giving miscellaneous information about the insn.  It is often
+expressions) giving miscellaneous information about the insn.  It is often
 information pertaining to the registers used in this insn.
 @end table
 The @code{LOG_LINKS} field of an insn is a chain of @code{insn_list}
 expressions.  Each of these has two operands: the first is an insn,
 which can be used for instruction combination.  For each insn, the flow
 analysis pass adds a link to insns which store into registers values
 that are used for the first time in this insn.
 The @code{REG_NOTES} field of an insn is a chain similar to the
-@code{LOG_LINKS} field but it includes @code{expr_list} expressions in
+@code{LOG_LINKS} field but it includes @code{expr_list} and @code{int_list}
-addition to @code{insn_list} expressions.  There are several kinds of
+expressions in addition to @code{insn_list} expressions.  There are several
-register notes, which are distinguished by the machine mode, which in a
+kinds of register notes, which are distinguished by the machine mode, which
-register note is really understood as being an @code{enum reg_note}.
+in a register note is really understood as being an @code{enum reg_note}.
 The first operand @var{op} of the note is data whose meaning depends on
 the kind of note.
 @findex REG_NOTE_KIND
 @findex PUT_REG_NOTE_KIND
 instruction should not be ``collapsed'' into a simpler branching
 construct.  It is used when the optimization to partition basic blocks
 into hot and cold sections is turned on.
 @findex REG_SETJMP
 @item REG_SETJMP
 Appears attached to each @code{CALL_INSN} to @code{setjmp} or a
 related function.
 @end table
 The following notes describe attributes of outputs of an insn:
 This note is only valid on an insn that sets only one register and
 indicates that that register will be equal to @var{op} at run time; the
 scope of this equivalence differs between the two types of notes.  The
 value which the insn explicitly copies into the register may look
 different from @var{op}, but they will be equal at run time.  If the
-output of the single @code{set} is a @code{strict_low_part} expression,
+output of the single @code{set} is a @code{strict_low_part} or
-the note refers to the register that is contained in @code{SUBREG_REG}
+@code{zero_extract} expression, the note refers to the register that
-of the @code{subreg} expression.
+is contained in its first operand.
 For @code{REG_EQUIV}, the register is equivalent to @var{op} throughout
 the entire function, and could validly be replaced in all its
 occurrences by @var{op}.  (``Validly'' here refers to the data flow of
 the program; simple replacement may make some insns invalid.)  For
 This indicates an anti dependence (a write after read dependence).
 @end table
 These notes describe information gathered from gcov profile data.  They
-are stored in the @code{REG_NOTES} field of an insn as an
+are stored in the @code{REG_NOTES} field of an insn.
-@code{expr_list}.
 @table @code
 @findex REG_BR_PROB
 @item REG_BR_PROB
 This is used to specify the ratio of branches to non-branches of a
-branch insn according to the profile data.  The value is stored as a
+branch insn according to the profile data.  The note is represented
-value between 0 and REG_BR_PROB_BASE; larger values indicate a higher
+as an @code{int_list} expression whose integer value is an encoding
-probability that the branch will be taken.
+of @code{profile_probability} type.  @code{profile_probability} provide
+member function @code{from_reg_br_prob_note} and @code{to_reg_br_prob_note}
+to extract and store the probability into the RTL encoding.
 @findex REG_BR_PRED
 @item REG_BR_PRED
 These notes are found in JUMP insns after delayed branch scheduling
 has taken place.  They indicate both the direction and the likelihood
 @findex REG_FRAME_RELATED_EXPR
 @item REG_FRAME_RELATED_EXPR
 This is used on an RTX_FRAME_RELATED_P insn wherein the attached expression
 is used in place of the actual insn pattern.  This is done in cases where
 the pattern is either complex or misleading.
+@end table
+The note @code{REG_CALL_NOCF_CHECK} is used in conjunction with the
+@option{-fcf-protection=branch} option.  The note is set if a
+@code{nocf_check} attribute is specified for a function type or a
+pointer to function type.  The note is stored in the @code{REG_NOTES}
+field of an insn.
+@table @code
+@findex REG_CALL_NOCF_CHECK
+@item REG_CALL_NOCF_CHECK
+Users have control through the @code{nocf_check} attribute to identify
+which calls to a function should be skipped from control-flow instrumentation
+when the option @option{-fcf-protection=branch} is specified.  The compiler
+puts a @code{REG_CALL_NOCF_CHECK} note on each @code{CALL_INSN} instruction
+that has a function type marked with a @code{nocf_check} attribute.
 @end table
 For convenience, the machine mode in an @code{insn_list} or
 @code{expr_list} is printed using these symbolic codes in debugging dumps.

Mercurial > hg > CbC > CbC_gcc

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