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comparison gcc/ira.h @ 111:04ced10e8804

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gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
parents f6334be47118
children 84e7813d76e9
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68:561a7518be6b 111:04ced10e8804
1 /* Communication between the Integrated Register Allocator (IRA) and 1 /* Communication between the Integrated Register Allocator (IRA) and
2 the rest of the compiler. 2 the rest of the compiler.
3 Copyright (C) 2006, 2007, 2008, 2009, 2010 3 Copyright (C) 2006-2017 Free Software Foundation, Inc.
4 Free Software Foundation, Inc.
5 Contributed by Vladimir Makarov <vmakarov@redhat.com>. 4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 5
7 This file is part of GCC. 6 This file is part of GCC.
8 7
9 GCC is free software; you can redistribute it and/or modify it under 8 GCC is free software; you can redistribute it and/or modify it under
18 17
19 You should have received a copy of the GNU General Public License 18 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see 19 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */ 20 <http://www.gnu.org/licenses/>. */
22 21
23 /* Function specific hard registers can not be used for the register 22 #ifndef GCC_IRA_H
24 allocation. */ 23 #define GCC_IRA_H
25 extern HARD_REG_SET ira_no_alloc_regs; 24
25 #include "emit-rtl.h"
26
27 /* True when we use LRA instead of reload pass for the current
28 function. */
29 extern bool ira_use_lra_p;
26 30
27 /* True if we have allocno conflicts. It is false for non-optimized 31 /* True if we have allocno conflicts. It is false for non-optimized
28 mode or when the conflict table is too big. */ 32 mode or when the conflict table is too big. */
29 extern bool ira_conflicts_p; 33 extern bool ira_conflicts_p;
30 34
31 struct target_ira { 35 struct target_ira
32 /* Number of given class hard registers available for the register 36 {
33 allocation for given classes. */ 37 /* Map: hard register number -> allocno class it belongs to. If the
34 int x_ira_available_class_regs[N_REG_CLASSES];
35
36 /* Map: hard register number -> cover class it belongs to. If the
37 corresponding class is NO_REGS, the hard register is not available 38 corresponding class is NO_REGS, the hard register is not available
38 for allocation. */ 39 for allocation. */
39 enum reg_class x_ira_hard_regno_cover_class[FIRST_PSEUDO_REGISTER]; 40 enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER];
40 41
41 /* Number of cover classes. Cover classes is non-intersected register 42 /* Number of allocno classes. Allocno classes are register classes
42 classes containing all hard-registers available for the 43 which can be used for allocations of allocnos. */
43 allocation. */ 44 int x_ira_allocno_classes_num;
44 int x_ira_reg_class_cover_size; 45
45 46 /* The array containing allocno classes. Only first
46 /* The array containing cover classes (see also comments for macro 47 IRA_ALLOCNO_CLASSES_NUM elements are used for this. */
47 IRA_COVER_CLASSES;. Only first IRA_REG_CLASS_COVER_SIZE elements are 48 enum reg_class x_ira_allocno_classes[N_REG_CLASSES];
48 used for this. */ 49
49 enum reg_class x_ira_reg_class_cover[N_REG_CLASSES]; 50 /* Map of all register classes to corresponding allocno classes
50 51 containing the given class. If given class is not a subset of an
51 /* Map of all register classes to corresponding cover class containing 52 allocno class, we translate it into the cheapest allocno class. */
52 the given class. If given class is not a subset of a cover class, 53 enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES];
53 we translate it into the cheapest cover class. */ 54
54 enum reg_class x_ira_class_translate[N_REG_CLASSES]; 55 /* Number of pressure classes. Pressure classes are register
55 56 classes for which we calculate register pressure. */
56 /* Map: register class x machine mode -> number of hard registers of 57 int x_ira_pressure_classes_num;
57 given class needed to store value of given mode. If the number for 58
58 some hard-registers of the register class is different, the size 59 /* The array containing pressure classes. Only first
59 will be negative. */ 60 IRA_PRESSURE_CLASSES_NUM elements are used for this. */
60 int x_ira_reg_class_nregs[N_REG_CLASSES][MAX_MACHINE_MODE]; 61 enum reg_class x_ira_pressure_classes[N_REG_CLASSES];
62
63 /* Map of all register classes to corresponding pressure classes
64 containing the given class. If given class is not a subset of an
65 pressure class, we translate it into the cheapest pressure
66 class. */
67 enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
68
69 /* Biggest pressure register class containing stack registers.
70 NO_REGS if there are no stack registers. */
71 enum reg_class x_ira_stack_reg_pressure_class;
72
73 /* Maps: register class x machine mode -> maximal/minimal number of
74 hard registers of given class needed to store value of given
75 mode. */
76 unsigned char x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
77 unsigned char x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
61 78
62 /* Array analogous to target hook TARGET_MEMORY_MOVE_COST. */ 79 /* Array analogous to target hook TARGET_MEMORY_MOVE_COST. */
63 short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2]; 80 short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
64 81
65 /* Array of number of hard registers of given class which are 82 /* Array of number of hard registers of given class which are
68 short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER]; 85 short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
69 86
70 /* The number of elements of the above array for given register 87 /* The number of elements of the above array for given register
71 class. */ 88 class. */
72 int x_ira_class_hard_regs_num[N_REG_CLASSES]; 89 int x_ira_class_hard_regs_num[N_REG_CLASSES];
90
91 /* Register class subset relation: TRUE if the first class is a subset
92 of the second one considering only hard registers available for the
93 allocation. */
94 int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
95
96 /* The biggest class inside of intersection of the two classes (that
97 is calculated taking only hard registers available for allocation
98 into account. If the both classes contain no hard registers
99 available for allocation, the value is calculated with taking all
100 hard-registers including fixed ones into account. */
101 enum reg_class x_ira_reg_class_subset[N_REG_CLASSES][N_REG_CLASSES];
102
103 /* True if the two classes (that is calculated taking only hard
104 registers available for allocation into account; are
105 intersected. */
106 bool x_ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES];
107
108 /* If class CL has a single allocatable register of mode M,
109 index [CL][M] gives the number of that register, otherwise it is -1. */
110 short x_ira_class_singleton[N_REG_CLASSES][MAX_MACHINE_MODE];
111
112 /* Function specific hard registers can not be used for the register
113 allocation. */
114 HARD_REG_SET x_ira_no_alloc_regs;
115
116 /* Array whose values are hard regset of hard registers available for
117 the allocation of given register class whose targetm.hard_regno_mode_ok
118 values for given mode are false. */
119 HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
73 }; 120 };
74 121
75 extern struct target_ira default_target_ira; 122 extern struct target_ira default_target_ira;
76 #if SWITCHABLE_TARGET 123 #if SWITCHABLE_TARGET
77 extern struct target_ira *this_target_ira; 124 extern struct target_ira *this_target_ira;
78 #else 125 #else
79 #define this_target_ira (&default_target_ira) 126 #define this_target_ira (&default_target_ira)
80 #endif 127 #endif
81 128
82 #define ira_available_class_regs \ 129 #define ira_hard_regno_allocno_class \
83 (this_target_ira->x_ira_available_class_regs) 130 (this_target_ira->x_ira_hard_regno_allocno_class)
84 #define ira_hard_regno_cover_class \ 131 #define ira_allocno_classes_num \
85 (this_target_ira->x_ira_hard_regno_cover_class) 132 (this_target_ira->x_ira_allocno_classes_num)
86 #define ira_reg_class_cover_size \ 133 #define ira_allocno_classes \
87 (this_target_ira->x_ira_reg_class_cover_size) 134 (this_target_ira->x_ira_allocno_classes)
88 #define ira_reg_class_cover \ 135 #define ira_allocno_class_translate \
89 (this_target_ira->x_ira_reg_class_cover) 136 (this_target_ira->x_ira_allocno_class_translate)
90 #define ira_class_translate \ 137 #define ira_pressure_classes_num \
91 (this_target_ira->x_ira_class_translate) 138 (this_target_ira->x_ira_pressure_classes_num)
92 #define ira_reg_class_nregs \ 139 #define ira_pressure_classes \
93 (this_target_ira->x_ira_reg_class_nregs) 140 (this_target_ira->x_ira_pressure_classes)
141 #define ira_pressure_class_translate \
142 (this_target_ira->x_ira_pressure_class_translate)
143 #define ira_stack_reg_pressure_class \
144 (this_target_ira->x_ira_stack_reg_pressure_class)
145 #define ira_reg_class_max_nregs \
146 (this_target_ira->x_ira_reg_class_max_nregs)
147 #define ira_reg_class_min_nregs \
148 (this_target_ira->x_ira_reg_class_min_nregs)
94 #define ira_memory_move_cost \ 149 #define ira_memory_move_cost \
95 (this_target_ira->x_ira_memory_move_cost) 150 (this_target_ira->x_ira_memory_move_cost)
96 #define ira_class_hard_regs \ 151 #define ira_class_hard_regs \
97 (this_target_ira->x_ira_class_hard_regs) 152 (this_target_ira->x_ira_class_hard_regs)
98 #define ira_class_hard_regs_num \ 153 #define ira_class_hard_regs_num \
99 (this_target_ira->x_ira_class_hard_regs_num) 154 (this_target_ira->x_ira_class_hard_regs_num)
155 #define ira_class_subset_p \
156 (this_target_ira->x_ira_class_subset_p)
157 #define ira_reg_class_subset \
158 (this_target_ira->x_ira_reg_class_subset)
159 #define ira_reg_classes_intersect_p \
160 (this_target_ira->x_ira_reg_classes_intersect_p)
161 #define ira_class_singleton \
162 (this_target_ira->x_ira_class_singleton)
163 #define ira_no_alloc_regs \
164 (this_target_ira->x_ira_no_alloc_regs)
165 #define ira_prohibited_class_mode_regs \
166 (this_target_ira->x_ira_prohibited_class_mode_regs)
167
168 /* Major structure describing equivalence info for a pseudo. */
169 struct ira_reg_equiv_s
170 {
171 /* True if we can use this equivalence. */
172 bool defined_p;
173 /* True if the usage of the equivalence is profitable. */
174 bool profitable_p;
175 /* Equiv. memory, constant, invariant, and initializing insns of
176 given pseudo-register or NULL_RTX. */
177 rtx memory;
178 rtx constant;
179 rtx invariant;
180 /* Always NULL_RTX if defined_p is false. */
181 rtx_insn_list *init_insns;
182 };
183
184 /* The length of the following array. */
185 extern int ira_reg_equiv_len;
186
187 /* Info about equiv. info for each register. */
188 extern struct ira_reg_equiv_s *ira_reg_equiv;
100 189
101 extern void ira_init_once (void); 190 extern void ira_init_once (void);
102 extern void ira_init (void); 191 extern void ira_init (void);
103 extern void ira_finish_once (void);
104 extern void ira_setup_eliminable_regset (void); 192 extern void ira_setup_eliminable_regset (void);
105 extern rtx ira_eliminate_regs (rtx, enum machine_mode); 193 extern rtx ira_eliminate_regs (rtx, machine_mode);
106 extern void ira_set_pseudo_classes (FILE *); 194 extern void ira_set_pseudo_classes (bool, FILE *);
107 extern void ira_implicitly_set_insn_hard_regs (HARD_REG_SET *); 195 extern void ira_expand_reg_equiv (void);
108 196 extern void ira_update_equiv_info_by_shuffle_insn (int, int, rtx_insn *);
109 extern void ira_sort_regnos_for_alter_reg (int *, int, unsigned int *); 197
198 extern void ira_sort_regnos_for_alter_reg (int *, int, machine_mode *);
110 extern void ira_mark_allocation_change (int); 199 extern void ira_mark_allocation_change (int);
111 extern void ira_mark_memory_move_deletion (int, int); 200 extern void ira_mark_memory_move_deletion (int, int);
112 extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *, 201 extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *,
113 HARD_REG_SET *, bitmap); 202 HARD_REG_SET *, bitmap);
114 extern rtx ira_reuse_stack_slot (int, unsigned int, unsigned int); 203 extern rtx ira_reuse_stack_slot (int, unsigned int, unsigned int);
115 extern void ira_mark_new_stack_slot (rtx, int, unsigned int); 204 extern void ira_mark_new_stack_slot (rtx, int, unsigned int);
116 extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx); 205 extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx_insn *);
117 extern bool ira_bad_reload_regno (int, rtx, rtx); 206 extern bool ira_bad_reload_regno (int, rtx, rtx);
118 207
119 extern void ira_adjust_equiv_reg_cost (unsigned, int); 208 extern void ira_adjust_equiv_reg_cost (unsigned, int);
209
210 /* ira-costs.c */
211 extern void ira_costs_c_finalize (void);
212
213 /* Spilling static chain pseudo may result in generation of wrong
214 non-local goto code using frame-pointer to address saved stack
215 pointer value after restoring old frame pointer value. The
216 function returns TRUE if REGNO is such a static chain pseudo. */
217 static inline bool
218 non_spilled_static_chain_regno_p (int regno)
219 {
220 return (cfun->static_chain_decl && crtl->has_nonlocal_goto
221 && REG_EXPR (regno_reg_rtx[regno]) == cfun->static_chain_decl);
222 }
223
224 #endif /* GCC_IRA_H */