comparison gcc/testsuite/gcc.dg/pr27861-1.c @ 111:04ced10e8804

gcc 7
author kono
date Fri, 27 Oct 2017 22:46:09 +0900
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68:561a7518be6b 111:04ced10e8804
1 /* PR target/27861 */
2 /* The following code used to cause an ICE during RTL expansion, as
3 expand shift was stripping the SUBREG of a rotate shift count, and
4 later producing a VAR_DECL tree whose DECL_RTL's mode didn't match
5 the VAR_DECL's type's mode. */
6 /* { dg-do compile } */
7 /* { dg-options "-O2" } */
8
9 typedef struct sim_state *SIM_DESC;
10 typedef enum
11 {
12 SIM_OPEN_STANDALONE, SIM_OPEN_DEBUG
13 }
14 SIM_RC;
15 typedef unsigned int unsigned32 __attribute__ ((__mode__ (__SI__)));
16 typedef unsigned int unsigned64 __attribute__ ((__mode__ (__DI__)));
17 typedef unsigned32 unsigned_address;
18 typedef unsigned_address address_word;
19 static __inline__ unsigned64
20 __attribute__ ((__unused__)) ROTR64 (unsigned64 val, int shift)
21 {
22 unsigned64 result;
23 result = (((val) >> (shift)) | ((val) << ((64) - (shift))));
24 return result;
25 }
26 typedef struct _sim_cpu sim_cpu;
27 enum
28 {
29 TRACE_MEMORY_IDX, TRACE_MODEL_IDX, TRACE_ALU_IDX, TRACE_CORE_IDX,
30 };
31 typedef struct _trace_data
32 {
33 char trace_flags[32];
34 }
35 TRACE_DATA;
36 typedef enum
37 {
38 nr_watchpoint_types,
39 }
40 watchpoint_type;
41 typedef struct _sim_watchpoints
42 {
43 TRACE_DATA trace_data;
44 }
45 sim_cpu_base;
46 struct _sim_cpu
47 {
48 sim_cpu_base base;
49 };
50 struct sim_state
51 {
52 sim_cpu cpu[1];
53 };
54 typedef address_word instruction_address;
55 void trace_result_word1 ();
56 int
57 do_dror (SIM_DESC sd, instruction_address cia, int MY_INDEX, unsigned64 x,
58 unsigned64 y)
59 {
60 unsigned64 result;
61 result = ROTR64 (x, y);
62 {
63 if ((((-1) & (1 << (TRACE_ALU_IDX))) != 0
64 && (((&(((&(sd)->cpu[0])))->base.trace_data))->
65 trace_flags)[TRACE_ALU_IDX] != 0))
66 trace_result_word1 (sd, ((&(sd)->cpu[0])), TRACE_ALU_IDX, (result));
67 }
68 }
69