CbC/CbC_gcc: gcc/combine.c comparison

comparison gcc/combine.c @ 145:1830386684a0

gcc-9.2.0

author	anatofuz
date	Thu, 13 Feb 2020 11:34:05 +0900
parents	84e7813d76e9
children

comparison

equal deleted inserted replaced

-:84e7813d76e9
+:1830386684a0
 /* Optimize by combining instructions for GNU compiler.
-Copyright (C) 1987-2018 Free Software Foundation, Inc.
+Copyright (C) 1987-2020 Free Software Foundation, Inc.
 This file is part of GCC.
 GCC is free software; you can redistribute it and/or modify it under
 the terms of the GNU General Public License as published by the Free
 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
 #include "explow.h"
 #include "insn-attr.h"
 #include "rtlhooks-def.h"
 #include "expr.h"
-#include "params.h"
 #include "tree-pass.h"
 #include "valtrack.h"
 #include "rtl-iter.h"
 #include "print-rtl.h"
+#include "function-abi.h"
 /* Number of attempts to combine instructions in this function.  */
 static int combine_attempts;
 targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
 *code = (enum rtx_code)code_int;
 }
 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
-PATTERN can not be split.  Otherwise, it returns an insn sequence.
+PATTERN cannot be split.  Otherwise, it returns an insn sequence.
 This is a wrapper around split_insns which ensures that the
 reg_stat vector is made larger if the splitter creates a new
 register.  */
 static rtx_insn *
 case CONST:
 case LABEL_REF:
 case SYMBOL_REF:
 CASE_CONST_ANY:
 case CLOBBER:
-case CLOBBER_HIGH:
 return 0;
 case SET:
 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 	 of a REG that occupies all of the REG, the insn uses DEST if
 return true;
 }
-/* Delete any insns that copy a register to itself.  */
+/* Delete any insns that copy a register to itself.
+Return true if the CFG was changed.  */
-static void
+static bool
 delete_noop_moves (void)
 {
 rtx_insn *insn, *next;
 basic_block bb;
+bool edges_deleted = false;
 FOR_EACH_BB_FN (bb, cfun)
 {
 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 	{
 	  next = NEXT_INSN (insn);
 	  if (INSN_P (insn) && noop_move_p (insn))
 	    {
 	      if (dump_file)
 		fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
-	      delete_insn_and_edges (insn);
+	      edges_deleted |= delete_insn_and_edges (insn);
 	    }
 	}
 }
+return edges_deleted;
 }
 /* Return false if we do not want to (or cannot) combine DEF.  */
 static bool
 }
 /* Main entry point for combiner.  F is the first insn of the function.
 NREGS is the first unused pseudo-reg number.
-Return nonzero if the combiner has turned an indirect jump
+Return nonzero if the CFG was changed (e.g. if the combiner has
-instruction into a direct jump.  */
+turned an indirect jump instruction into a direct jump).  */
 static int
 combine_instructions (rtx_insn *f, unsigned int nregs)
 {
 rtx_insn *insn, *next;
 rtx_insn *prev;
 rtx links;
 subst_low_luid = DF_INSN_LUID (insn);
 subst_insn = insn;
-	    note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
+	    note_stores (insn, set_nonzero_bits_and_sign_copies, insn);
-		         insn);
 	    record_dead_and_set_regs (insn);
 	    if (AUTO_INC_DEC)
 	      for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
 		if (REG_NOTE_KIND (links) == REG_INC)
 		  set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
 						    insn);
 	    /* Record the current insn_cost of this instruction.  */
-	    if (NONJUMP_INSN_P (insn))
+	    INSN_COST (insn) = insn_cost (insn, optimize_this_for_speed_p);
-	      INSN_COST (insn) = insn_cost (insn, optimize_this_for_speed_p);
 	    if (dump_file)
 	      {
 		fprintf (dump_file, "insn_cost %d for ", INSN_COST (insn));
 		dump_insn_slim (dump_file, insn);
 	      }
 /* Now scan all the insns in forward order.  */
 label_tick = label_tick_ebb_start = 1;
 init_reg_last ();
 setup_incoming_promotions (first);
 last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
-int max_combine = PARAM_VALUE (PARAM_MAX_COMBINE_INSNS);
+int max_combine = param_max_combine_insns;
 FOR_EACH_BB_FN (this_basic_block, cfun)
 {
 rtx_insn *last_combined_insn = NULL;
 }
 default_rtl_profile ();
 clear_bb_flags ();
 new_direct_jump_p |= purge_all_dead_edges ();
-delete_noop_moves ();
+new_direct_jump_p |= delete_noop_moves ();
 /* Clean up.  */
 obstack_free (&insn_link_obstack, NULL);
 free (uid_log_links);
 free (uid_insn_cost);
 /* Determine, if possible, whether all call sites of the current
 function lie within the current compilation unit.  (This does
 	 take into account the exporting of a function via taking its
 	 address, and so forth.)  */
-strictly_local = cgraph_node::local_info (current_function_decl)->local;
+strictly_local
+	= cgraph_node::local_info_node (current_function_decl)->local;
 /* The mode and signedness of the argument before any promotions happen
 (equal to the mode of the pseudo holding it at that stage).  */
 mode1 = TYPE_MODE (TREE_TYPE (arg));
 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
 }
 /* Don't call nonzero_bits if it cannot change anything.  */
 if (rsp->nonzero_bits != HOST_WIDE_INT_M1U)
 {
-bits = nonzero_bits (src, nonzero_bits_mode);
+machine_mode mode = GET_MODE (x);
+if (GET_MODE_CLASS (mode) == MODE_INT
+	  && HWI_COMPUTABLE_MODE_P (mode))
+	mode = nonzero_bits_mode;
+bits = nonzero_bits (src, mode);
 if (reg_equal && bits)
-	bits &= nonzero_bits (reg_equal, nonzero_bits_mode);
+	bits &= nonzero_bits (reg_equal, mode);
 rsp->nonzero_bits |= bits;
 }
 /* Don't call num_sign_bit_copies if it cannot change anything.  */
 if (rsp->sign_bit_copies != 1)
 	{
 	  rsp->nonzero_bits = GET_MODE_MASK (mode);
 	  rsp->sign_bit_copies = 1;
 	  return;
 	}
-/* Should not happen as we only using pseduo registers.  */
-gcc_assert (GET_CODE (set) != CLOBBER_HIGH);
 /* If this register is being initialized using itself, and the
 	 register is uninitialized in this basic block, and there are
 	 no LOG_LINKS which set the register, then part of the
 	 register is uninitialized.  In that case we can't assume
 		}
 	      break;
 	      /* We can ignore CLOBBERs.  */
 	    case CLOBBER:
-	    case CLOBBER_HIGH:
 	      break;
 	    case SET:
 	      /* Ignore SETs whose result isn't used but not those that
 		 have side-effects.  */
 volatile insn might affect machine state.  */
 is_volatile_p = volatile_refs_p (PATTERN (insn))
 ? volatile_refs_p
 : volatile_insn_p;
 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
 return 0;
 /* If INSN contains an autoincrement or autodecrement, make sure that
 register is not used between there and I3, and not already used in
 I3 either.  Neither must it be used in PRED or SUCC, if they exist.
-Also insist that I3 not be a jump; if it were one
+Also insist that I3 not be a jump if using LRA; if it were one
-and the incremented register were spilled, we would lose.  */
+and the incremented register were spilled, we would lose.
+Reload handles this correctly.  */
 if (AUTO_INC_DEC)
 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
 if (REG_NOTE_KIND (link) == REG_INC
-	  && (JUMP_P (i3)
+	  && ((JUMP_P (i3) && targetm.lra_p ())
 	      || reg_used_between_p (XEXP (link, 0), insn, i3)
 	      || (pred != NULL_RTX
 		  && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
 	      || (pred2 != NULL_RTX
 		  && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
 src = SUBREG_REG (src);
 if (GET_CODE (dest) == SUBREG)
 dest = SUBREG_REG (dest);
 if (REG_P (src) && REG_P (dest)
 && ((HARD_REGISTER_P (src)
-	   && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)))
+	   && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
+#ifdef LEAF_REGISTERS
+	   && ! LEAF_REGISTERS [REGNO (src)])
+#else
+	   )
+#endif
 	  || (HARD_REGISTER_P (dest)
 	      && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
 	      && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
 return 1;
 info.regno = regno;
 info.nregs = nregs;
 info.mask = mask;
 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
 if (INSN_P (p))
-note_stores (PATTERN (p), likely_spilled_retval_1, &info);
+note_stores (p, likely_spilled_retval_1, &info);
 mask = info.mask;
 /* Check if any of the (probably) live return value registers is
 likely spilled.  */
 nregs --;
 {
 case CLOBBER:
 	if (XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
 	  return false;
 	break;
-case CLOBBER_HIGH:
-	break;
 default:
 	return false;
 }
 return true;
 }
 {
 if (INSN_P (x))
 x = PATTERN (x);
 return (GET_CODE (x) == SET && general_operand (SET_SRC (x), VOIDmode));
+}
+/* Callback function to count autoincs.  */
+static int
+count_auto_inc (rtx, rtx, rtx, rtx, rtx, void *arg)
+{
+(*((int *) arg))++;
+return 0;
 }
 /* Try to combine the insns I0, I1 and I2 into I3.
 Here I0, I1 and I2 appear earlier than I3.
 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
 int have_mult = 0;
 int swap_i2i3 = 0;
 int split_i2i3 = 0;
 int changed_i3_dest = 0;
 bool i2_was_move = false, i3_was_move = false;
+int n_auto_inc = 0;
 int maxreg;
 rtx_insn *temp_insn;
 rtx temp_expr;
 struct insn_link *link;
 	 that usually (see can_combine_p), so do not here either.  */
 bool ok = true;
 for (i = 0; ok && i < XVECLEN (p2, 0); i++)
 	{
 	  if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
-	       || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER
+	       || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
-	       || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER_HIGH)
 	      && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
 					  SET_DEST (XVECEXP (p2, 0, i))))
 	    ok = false;
 	  else if (GET_CODE (XVECEXP (p2, 0, i)) == SET
 		   && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS)
 }
 /* Verify that I2 and maybe I1 and I0 can be combined into I3.  */
 if (!can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src))
 {
-if (dump_file)
+if (dump_file && (dump_flags & TDF_DETAILS))
 	fprintf (dump_file, "Can't combine i2 into i3\n");
 undo_all ();
 return 0;
 }
 if (i1 && !can_combine_p (i1, i3, i0, NULL, i2, NULL, &i1dest, &i1src))
 {
-if (dump_file)
+if (dump_file && (dump_flags & TDF_DETAILS))
 	fprintf (dump_file, "Can't combine i1 into i3\n");
 undo_all ();
 return 0;
 }
 if (i0 && !can_combine_p (i0, i3, NULL, NULL, i1, i2, &i0dest, &i0src))
 {
-if (dump_file)
+if (dump_file && (dump_flags & TDF_DETAILS))
 	fprintf (dump_file, "Can't combine i0 into i3\n");
 undo_all ();
 return 0;
 }
 	  || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
 {
 undo_all ();
 return 0;
 }
+/* Count how many auto_inc expressions there were in the original insns;
+we need to have the same number in the resulting patterns.  */
+if (i0)
+for_each_inc_dec (PATTERN (i0), count_auto_inc, &n_auto_inc);
+if (i1)
+for_each_inc_dec (PATTERN (i1), count_auto_inc, &n_auto_inc);
+for_each_inc_dec (PATTERN (i2), count_auto_inc, &n_auto_inc);
+for_each_inc_dec (PATTERN (i3), count_auto_inc, &n_auto_inc);
 /* If the set in I2 needs to be kept around, we must make a copy of
 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
 PATTERN (I2), we are only substituting for the original I1DEST, not into
 an already-substituted copy.  This also prevents making self-referential
 /* If we already got a failure, don't try to do more.  Otherwise, try to
 substitute I1 if we have it.  */
 if (i1 && GET_CODE (newpat) != CLOBBER)
 {
-/* Check that an autoincrement side-effect on I1 has not been lost.
+/* Before we can do this substitution, we must redo the test done
-	 This happens if I1DEST is mentioned in I2 and dies there, and
+	 above (see detailed comments there) that ensures I1DEST isn't
-	 has disappeared from the new pattern.  */
+	 mentioned in any SETs in NEWPAT that are field assignments.  */
-if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
+if (!combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
-	   && i1_feeds_i2_n
+			     0, 0, 0))
-	   && dead_or_set_p (i2, i1dest)
-	   && !reg_overlap_mentioned_p (i1dest, newpat))
-	   /* Before we can do this substitution, we must redo the test done
-	      above (see detailed comments there) that ensures I1DEST isn't
-	      mentioned in any SETs in NEWPAT that are field assignments.  */
-	  || !combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
-				0, 0, 0))
 	{
 	  undo_all ();
 	  return 0;
 	}
 /* Likewise for I0 if we have it.  */
 if (i0 && GET_CODE (newpat) != CLOBBER)
 {
-if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
+if (!combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
-	   && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
+			     0, 0, 0))
-	       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
-	   && !reg_overlap_mentioned_p (i0dest, newpat))
-	  || !combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
-				0, 0, 0))
 	{
 	  undo_all ();
 	  return 0;
 	}
 n_occurrences = 0;
 subst_low_luid = DF_INSN_LUID (i0);
 newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
 substed_i0 = 1;
+}
+if (n_auto_inc)
+{
+int new_n_auto_inc = 0;
+for_each_inc_dec (newpat, count_auto_inc, &new_n_auto_inc);
+if (n_auto_inc != new_n_auto_inc)
+	{
+	  if (dump_file && (dump_flags & TDF_DETAILS))
+	    fprintf (dump_file, "Number of auto_inc expressions changed\n");
+	  undo_all ();
+	  return 0;
+	}
 }
 /* Fail if an autoincrement side-effect has been duplicated.  Be careful
 to count all the ways that I2SRC and I1SRC can be used.  */
 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
 /* Update reg_stat[].nonzero_bits et al for any changes that may have
 been made to this insn.  The order is important, because newi2pat
 can affect nonzero_bits of newpat.  */
 if (newi2pat)
-note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
+note_pattern_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
-note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
+note_pattern_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
 }
 if (undobuf.other_insn != NULL_RTX)
 {
 if (dump_file)
 				 XEXP (x, 0)));
 	  return &XEXP (XEXP (x, 0), 0);
 	}
 /* If we have a PLUS whose second operand is a constant and the
-	 address is not valid, perhaps will can split it up using
+	 address is not valid, perhaps we can split it up using
 	 the machine-specific way to split large constants.  We use
 	 the first pseudo-reg (one of the virtual regs) as a placeholder;
 	 it will not remain in the result.  */
 if (GET_CODE (XEXP (x, 0)) == PLUS
 	  && CONST_INT_P (XEXP (XEXP (x, 0), 1))
 	  rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)),
 					       subst_insn);
 	  /* This should have produced two insns, each of which sets our
 	     placeholder.  If the source of the second is a valid address,
-	     we can make put both sources together and make a split point
+	     we can put both sources together and make a split point
 	     in the middle.  */
 	  if (seq
 	      && NEXT_INSN (seq) != NULL_RTX
 	      && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
 		  SUBST (XEXP (x, 0), src2);
 		  return split;
 		}
 	    }
+	  /* If that didn't work and we have a nested plus, like:
+	     ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
+	     is valid address, try to split (REG1 * CONST1).  */
+	  if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
+	      && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
+	      && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
+	      && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
+		    && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
+							 0), 0)))))
+	    {
+	      rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 0);
+	      XEXP (XEXP (XEXP (x, 0), 0), 0) = reg;
+	      if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
+					       MEM_ADDR_SPACE (x)))
+		{
+		  XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
+		  return &XEXP (XEXP (XEXP (x, 0), 0), 0);
+		}
+	      XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
+	    }
+	  else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
+		   && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
+		   && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
+		   && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
+			 && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
+							      0), 1)))))
+	    {
+	      rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 1);
+	      XEXP (XEXP (XEXP (x, 0), 0), 1) = reg;
+	      if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
+					       MEM_ADDR_SPACE (x)))
+		{
+		  XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
+		  return &XEXP (XEXP (XEXP (x, 0), 0), 1);
+		}
+	      XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
+	    }
 	  /* If that didn't work, perhaps the first operand is complex and
 	     needs to be computed separately, so make a split point there.
 	     This will occur on machines that just support REG + CONST
 	     and have a constant moved through some previous computation.  */
+	  if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
-	  else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
+	      && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
-		   && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
+		    && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
-			 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
 	    return &XEXP (XEXP (x, 0), 0);
 	}
 /* If we have a PLUS whose first operand is complex, try computing it
 separately by making a split there.  */
 		  if (! x)
 		    x = gen_rtx_CLOBBER (mode, const0_rtx);
 		}
 	      else if (CONST_SCALAR_INT_P (new_rtx)
 		       && (GET_CODE (x) == ZERO_EXTEND
+			   || GET_CODE (x) == SIGN_EXTEND
 			   || GET_CODE (x) == FLOAT
 			   || GET_CODE (x) == UNSIGNED_FLOAT))
 		{
 		  x = simplify_unary_operation (GET_CODE (x), GET_MODE (x),
 						new_rtx,
 		x = simplify_gen_unary (NEG, mode,
 					simplify_gen_relational (reversed,
 								 mode, VOIDmode,
 								 cond, cop1),
 					mode);
-	      else
-		return gen_rtx_IF_THEN_ELSE (mode,
-					     simplify_gen_relational (cond_code,
-								      mode,
-								      VOIDmode,
-								      cond,
-								      cop1),
-					     true_rtx, false_rtx);
 	      code = GET_CODE (x);
 	      op0_mode = VOIDmode;
 	    }
 	}
 	    && (GET_MODE_PRECISION (int_mode)
 		< GET_MODE_PRECISION (int_op0_mode))
 	    && known_eq (subreg_lowpart_offset (int_mode, int_op0_mode),
 			 SUBREG_BYTE (x))
 	    && HWI_COMPUTABLE_MODE_P (int_op0_mode)
-	    && (nonzero_bits (SUBREG_REG (x), int_op0_mode)
+	    && ((nonzero_bits (SUBREG_REG (x), int_op0_mode)
-		& GET_MODE_MASK (int_mode)) == 0)
+		 & GET_MODE_MASK (int_mode)) == 0)
+	    && !side_effects_p (SUBREG_REG (x)))
 	  return CONST0_RTX (int_mode);
 }
 /* Don't change the mode of the MEM if that would change the meaning
 	 of the address.  */
 	  || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
 	      && !OBJECT_P (false_rtx))
 	  || reg_mentioned_p (true_rtx, false_rtx)
 	  || rtx_equal_p (false_rtx, XEXP (cond, 0))))
 {
-true_code = reversed_comparison_code (cond, NULL);
 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
 SUBST (XEXP (x, 1), false_rtx);
 SUBST (XEXP (x, 2), true_rtx);
 std::swap (true_rtx, false_rtx);
 		  % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
 		     : BITS_PER_UNIT)) == 0
 	      /* We can't do this if we are widening INNER_MODE (it
 		 may not be aligned, for one thing).  */
 	      && !paradoxical_subreg_p (tmode, inner_mode)
+	      && known_le (pos + len, GET_MODE_PRECISION (is_mode))
 	      && (inner_mode == tmode
 		  || (! mode_dependent_address_p (XEXP (inner, 0),
 						  MEM_ADDR_SPACE (inner))
 		      && ! MEM_VOLATILE_P (inner))))))
 {
 and their respective operands.
 For memory, assume that the desired extraction_mode and pos_mode
 are the same as for a register operation, since at present we don't
 have named patterns for aligned memory structures.  */
-struct extraction_insn insn;
+class extraction_insn insn;
 unsigned int inner_size;
 if (GET_MODE_BITSIZE (inner_mode).is_constant (&inner_size)
 && get_best_reg_extraction_insn (&insn, pattern, inner_size, mode))
 {
 wanted_inner_reg_mode = insn.struct_mode.require ();
 /* Never narrow an object, since that might not be safe.  */
 if (mode != VOIDmode
 && partial_subreg_p (extraction_mode, mode))
 extraction_mode = mode;
+/* Punt if len is too large for extraction_mode.  */
+if (maybe_gt (len, GET_MODE_PRECISION (extraction_mode)))
+return NULL_RTX;
 if (!MEM_P (inner))
 wanted_inner_mode = wanted_inner_reg_mode;
 else
 {
 case MINUS:
 /* If X is (minus C Y) where C's least set bit is larger than any bit
 	 in the mask, then we may replace with (neg Y).  */
 if (poly_int_rtx_p (XEXP (x, 0), &const_op0)
-	  && (unsigned HOST_WIDE_INT) known_alignment (const_op0) > mask)
+	  && known_alignment (poly_uint64 (const_op0)) > mask)
 	{
 	  x = simplify_gen_unary (NEG, xmode, XEXP (x, 1), xmode);
 	  return force_to_mode (x, mode, mask, next_select);
 	}
 return x;
 }
 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
 We don't care about bits outside of those defined in MODE.
+We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
 a shift, AND, or zero_extract, we can do better.  */
 static rtx
 return adjust_address_nv (x, omode, offset);
 }
 /* If X is a comparison operator, rewrite it in a new mode.  This
 probably won't match, but may allow further simplifications.  */
-else if (COMPARISON_P (x))
+else if (COMPARISON_P (x)
+	   && SCALAR_INT_MODE_P (imode)
+	   && SCALAR_INT_MODE_P (omode))
 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
 /* If we couldn't simplify X any other way, just enclose it in a
 SUBREG.  Normally, this SUBREG won't match, but some patterns may
 include an explicit SUBREG or we may simplify it further in combine.  */
 	  /* If we are doing a < 0 or >= 0 comparison, it means we are testing
 	     a particular bit.  Convert it to an AND of a constant of that
 	     bit.  This will be converted into a ZERO_EXTRACT.  */
 	  if (const_op == 0 && sign_bit_comparison_p
 	      && CONST_INT_P (XEXP (op0, 1))
-	      && mode_width <= HOST_BITS_PER_WIDE_INT)
+	      && mode_width <= HOST_BITS_PER_WIDE_INT
+	      && UINTVAL (XEXP (op0, 1)) < mode_width)
 	    {
 	      op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
 					    (HOST_WIDE_INT_1U
 					     << (mode_width - 1
 						 - INTVAL (XEXP (op0, 1)))));
 	    tem = XEXP (tem, 0);
 	  else if (count_occurrences (value, reg, 1) >= 2)
 	    {
 	      /* If there are two or more occurrences of REG in VALUE,
 		 prevent the value from growing too much.  */
-	      if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
+	      if (count_rtxs (tem) > param_max_last_value_rtl)
 		tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
 	    }
 	  value = replace_rtx (copy_rtx (value), reg, tem);
 	}
 	       && known_le (GET_MODE_PRECISION (GET_MODE (dest)),
 			    BITS_PER_WORD)
 	       && subreg_lowpart_p (SET_DEST (setter)))
 	record_value_for_reg (dest, record_dead_insn,
 			      WORD_REGISTER_OPERATIONS
+			      && word_register_operation_p (SET_SRC (setter))
 			      && paradoxical_subreg_p (SET_DEST (setter))
 			      ? SET_SRC (setter)
 			      : gen_lowpart (GET_MODE (dest),
 					     SET_SRC (setter)));
-else if (GET_CODE (setter) == CLOBBER_HIGH)
-	{
-	  reg_stat_type *rsp = &reg_stat[REGNO (dest)];
-	  if (rsp->last_set_value
-	      && reg_is_clobbered_by_clobber_high
-		   (REGNO (dest), GET_MODE (rsp->last_set_value),
-		    XEXP (setter, 0)))
-	    record_value_for_reg (dest, NULL, NULL_RTX);
-	}
 else
 	record_value_for_reg (dest, record_dead_insn, NULL_RTX);
 }
 else if (MEM_P (dest)
 	   /* Ignore pushes, they clobber nothing.  */
 	record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
 }
 if (CALL_P (insn))
 {
+HARD_REG_SET callee_clobbers
+	= insn_callee_abi (insn).full_and_partial_reg_clobbers ();
 hard_reg_set_iterator hrsi;
-EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
+EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers, 0, i, hrsi)
 	{
 	  reg_stat_type *rsp;
+	  /* ??? We could try to preserve some information from the last
+	     set of register I if the call doesn't actually clobber
+	     (reg:last_set_mode I), which might be true for ABIs with
+	     partial clobbers.  However, it would be difficult to
+	     update last_set_nonzero_bits and last_sign_bit_copies
+	     to account for the part of I that actually was clobbered.
+	     It wouldn't help much anyway, since we rarely see this
+	     situation before RA.  */
 	  rsp = &reg_stat[i];
 	  rsp->last_set_invalid = 1;
 	  rsp->last_set = insn;
 	  rsp->last_set_value = 0;
 	  rsp->last_set_mode = VOIDmode;
 /* We can't combine into a call pattern.  Remember, though, that
 	 the return value register is set at this LUID.  We could
 	 still replace a register with the return value from the
 	 wrong subroutine call!  */
-note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
+note_stores (insn, record_dead_and_set_regs_1, NULL_RTX);
 }
 else
-note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
+note_stores (insn, record_dead_and_set_regs_1, insn);
 }
 /* If a SUBREG has the promoted bit set, it is in fact a property of the
 register present in the SUBREG, so for each such SUBREG go back and
 adjust nonzero and sign bit information of the registers that are
 unsigned int regno, endregno;
 if (!REG_P (dest))
 return;
-if (GET_CODE (x) == CLOBBER_HIGH
-&& !reg_is_clobbered_by_clobber_high (reg_dead_reg, XEXP (x, 0)))
-return;
 regno = REGNO (dest);
 endregno = END_REGNO (dest);
 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
 }
 if (INSN_P (insn))
 {
 	  if (find_regno_note (insn, REG_UNUSED, reg_dead_regno))
 	    return 1;
-	  note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
+	  note_stores (insn, reg_dead_at_p_1, NULL);
 	  if (reg_dead_flag)
 	    return reg_dead_flag == 1 ? 1 : 0;
 	  if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
 	    return 1;
 continue;
 	  rtx set = single_set (insn);
 	  if (!set)
 	    continue;
+	  rtx dest = SET_DEST (set);
+	  if (!(REG_P (dest) && !HARD_REGISTER_P (dest)))
+	      continue;
 	  rtx src = SET_SRC (set);
-	  rtx dest = SET_DEST (set);
-	  if (GET_CODE (src) == SUBREG)
-	    src = SUBREG_REG (src);
 	  if (!(REG_P (src) && HARD_REGISTER_P (src)))
 	    continue;
 	  if (TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)))
 	    continue;
 	  rtx new_reg = gen_reg_rtx (GET_MODE (dest));
-	  rtx_insn *insn1 = gen_move_insn (new_reg, src);
+	  rtx_insn *new_insn = gen_move_insn (new_reg, src);
-	  rtx_insn *insn2 = gen_move_insn (dest, new_reg);
+	  SET_SRC (set) = new_reg;
-	  emit_insn_after (insn1, insn);
+	  emit_insn_before (new_insn, insn);
-	  emit_insn_after (insn2, insn1);
+	  df_insn_rescan (insn);
-	  delete_insn (insn);
-	  insn = insn2;
 	}
 }
 }
 /* Try combining insns through substitution.  */

Mercurial > hg > CbC > CbC_gcc

comparison gcc/combine.c @ 145:1830386684a0