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gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
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131:84e7813d76e9 145:1830386684a0
1 /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu. 1 /* Definitions of target machine for GNU compiler, Synopsys DesignWare ARC cpu.
2 Copyright (C) 1994-2018 Free Software Foundation, Inc. 2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 3
4 This file is part of GCC. 4 This file is part of GCC.
5 5
6 GCC is free software; you can redistribute it and/or modify 6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by 7 it under the terms of the GNU General Public License as published by
95 #define SUBTARGET_CPP_SPEC "" 95 #define SUBTARGET_CPP_SPEC ""
96 #endif 96 #endif
97 97
98 #undef ASM_SPEC 98 #undef ASM_SPEC
99 #define ASM_SPEC "%{mbig-endian|EB:-EB} %{EL} " \ 99 #define ASM_SPEC "%{mbig-endian|EB:-EB} %{EL} " \
100 "%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} %{mfpu=fpuda*:-mfpuda}" 100 "%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} " \
101 "%{mfpu=fpuda*:-mfpuda} %{mcode-density}"
101 102
102 #define OPTION_DEFAULT_SPECS \ 103 #define OPTION_DEFAULT_SPECS \
103 {"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}}}}}" } 104 {"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}}}}}" }
104 105
105 #ifndef DRIVER_ENDIAN_SELF_SPECS 106 #ifndef DRIVER_ENDIAN_SELF_SPECS
283 /* Set this nonzero if move instructions will actually fail to work 284 /* Set this nonzero if move instructions will actually fail to work
284 when given unaligned data. */ 285 when given unaligned data. */
285 /* On the ARC the lower address bits are masked to 0 as necessary. The chip 286 /* On the ARC the lower address bits are masked to 0 as necessary. The chip
286 won't croak when given an unaligned address, but the insn will still fail 287 won't croak when given an unaligned address, but the insn will still fail
287 to produce the correct result. */ 288 to produce the correct result. */
288 #define STRICT_ALIGNMENT (!unaligned_access && !TARGET_HS) 289 #define STRICT_ALIGNMENT (!unaligned_access)
289 290
290 /* Layout of source language data types. */ 291 /* Layout of source language data types. */
291 292
292 #define SHORT_TYPE_SIZE 16 293 #define SHORT_TYPE_SIZE 16
293 #define INT_TYPE_SIZE 32 294 #define INT_TYPE_SIZE 32
310 #define WCHAR_TYPE "int" 311 #define WCHAR_TYPE "int"
311 312
312 #undef WCHAR_TYPE_SIZE 313 #undef WCHAR_TYPE_SIZE
313 #define WCHAR_TYPE_SIZE 32 314 #define WCHAR_TYPE_SIZE 32
314 315
315 #define PROGRAM_COUNTER_REGNO 63
316
317 /* Standard register usage. */ 316 /* Standard register usage. */
318 317
319 /* Number of actual hardware registers. 318 /* Number of actual hardware registers.
320 The hardware registers are assigned numbers for the compiler 319 The hardware registers are assigned numbers for the compiler
321 from 0 to just below FIRST_PSEUDO_REGISTER. 320 from 0 to just below FIRST_PSEUDO_REGISTER.
325 Registers 61, 62, and 63 are not really registers and we needn't treat 324 Registers 61, 62, and 63 are not really registers and we needn't treat
326 them as such. We still need a register for the condition code and 325 them as such. We still need a register for the condition code and
327 argument pointer. */ 326 argument pointer. */
328 327
329 /* r63 is pc, r64-r127 = simd vregs, r128-r143 = simd dma config regs 328 /* r63 is pc, r64-r127 = simd vregs, r128-r143 = simd dma config regs
330 r144, r145 = lp_start, lp_end 329 r144, r145 = ARG_POINTER, FRAME_POINTER
331 and therefore the pseudo registers start from r146. */ 330 and therefore the pseudo registers start from r146. */
332 #define FIRST_PSEUDO_REGISTER 146 331 #define FIRST_PSEUDO_REGISTER 146
333 332
334 /* 1 for registers that have pervasive standard uses 333 /* 1 for registers that have pervasive standard uses
335 and are not available for the register allocator. 334 and are not available for the register allocator.
361 30 - ilink2 360 30 - ilink2
362 31 - return address register 361 31 - return address register
363 362
364 By default, the extension registers are not available. */ 363 By default, the extension registers are not available. */
365 /* Present implementations only have VR0-VR23 only. */ 364 /* Present implementations only have VR0-VR23 only. */
366 /* ??? FIXME: r27 and r31 should not be fixed registers. */
367 #define FIXED_REGISTERS \ 365 #define FIXED_REGISTERS \
368 { 0, 0, 0, 0, 0, 0, 0, 0, \ 366 { 0, 0, 0, 0, 0, 0, 0, 0, \
369 0, 0, 0, 0, 0, 0, 0, 0, \ 367 0, 0, 0, 0, 0, 0, 0, 0, \
370 0, 0, 0, 0, 0, 0, 0, 0, \ 368 0, 0, 0, 0, 0, 0, 0, 0, \
371 0, 0, 1, 1, 1, 1, 1, 1, \ 369 0, 0, 1, 0, 1, 1, 1, 1, \
372 \ 370 \
373 1, 1, 1, 1, 1, 1, 1, 1, \ 371 1, 1, 1, 1, 1, 1, 1, 1, \
374 0, 0, 0, 0, 1, 1, 1, 1, \ 372 0, 0, 0, 0, 1, 1, 1, 1, \
375 1, 1, 1, 1, 1, 1, 1, 1, \ 373 1, 1, 1, 1, 1, 1, 1, 1, \
376 1, 1, 1, 1, 0, 1, 1, 1, \ 374 1, 1, 1, 1, 1, 1, 1, 1, \
377 \ 375 \
378 0, 0, 0, 0, 0, 0, 0, 0, \ 376 0, 0, 0, 0, 0, 0, 0, 0, \
379 0, 0, 0, 0, 0, 0, 0, 0, \ 377 0, 0, 0, 0, 0, 0, 0, 0, \
380 0, 0, 0, 0, 0, 0, 0, 0, \ 378 0, 0, 0, 0, 0, 0, 0, 0, \
381 1, 1, 1, 1, 1, 1, 1, 1, \ 379 1, 1, 1, 1, 1, 1, 1, 1, \
398 #define CALL_USED_REGISTERS \ 396 #define CALL_USED_REGISTERS \
399 { \ 397 { \
400 1, 1, 1, 1, 1, 1, 1, 1, \ 398 1, 1, 1, 1, 1, 1, 1, 1, \
401 1, 1, 1, 1, 1, 0, 0, 0, \ 399 1, 1, 1, 1, 1, 0, 0, 0, \
402 0, 0, 0, 0, 0, 0, 0, 0, \ 400 0, 0, 0, 0, 0, 0, 0, 0, \
403 0, 0, 1, 1, 1, 1, 1, 1, \ 401 0, 0, 1, 0, 1, 1, 1, 1, \
404 \ 402 \
405 1, 1, 1, 1, 1, 1, 1, 1, \ 403 1, 1, 1, 1, 1, 1, 1, 1, \
406 1, 1, 1, 1, 1, 1, 1, 1, \ 404 1, 1, 1, 1, 1, 1, 1, 1, \
407 1, 1, 1, 1, 1, 1, 1, 1, \ 405 1, 1, 1, 1, 1, 1, 1, 1, \
408 1, 1, 1, 1, 1, 1, 1, 1, \ 406 1, 1, 1, 1, 1, 1, 1, 1, \
422 1, 1} 420 1, 1}
423 421
424 /* If defined, an initializer for a vector of integers, containing the 422 /* If defined, an initializer for a vector of integers, containing the
425 numbers of hard registers in the order in which GCC should 423 numbers of hard registers in the order in which GCC should
426 prefer to use them (from most preferred to least). */ 424 prefer to use them (from most preferred to least). */
427 #define REG_ALLOC_ORDER \ 425 #define REG_ALLOC_ORDER \
428 { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1, \ 426 { \
429 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, \ 427 /* General registers. */ \
428 2, 3, 12, 13, 14, 15, 1, 0, 4, 5, 6, 7, 8, 9, 10, 11, \
429 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 30, \
430 /* Extension core registers. */ \
430 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 431 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
431 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, \ 432 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
432 27, 28, 29, 30, 31, 63} 433 /* VR regs. */ \
434 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
435 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
436 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
437 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, \
438 124, 125, 126, 127, \
439 /* DMA registers. */ \
440 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, \
441 142, 143, \
442 /* Register not used for general use. */ \
443 62, FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \
444 SP_REG, ILINK1_REG, RETURN_ADDR_REGNUM, LP_COUNT, CC_REG, PCL_REG \
445 }
446
447 /* Use different register alloc ordering for Thumb. */
448 #define ADJUST_REG_ALLOC_ORDER arc_adjust_reg_alloc_order ()
449
450 /* Tell IRA to use the order we define rather than messing it up with its
451 own cost calculations. */
452 #define HONOR_REG_ALLOC_ORDER 1
433 453
434 /* Internal macros to classify a register number as to whether it's a 454 /* Internal macros to classify a register number as to whether it's a
435 general purpose register for compact insns (r0-r3,r12-r15), or 455 general purpose register for compact insns (r0-r3,r12-r15), or
436 stack pointer (r28). */ 456 stack pointer (r28). */
437 457
468 488
469 enum reg_class 489 enum reg_class
470 { 490 {
471 NO_REGS, 491 NO_REGS,
472 R0_REGS, /* 'x' */ 492 R0_REGS, /* 'x' */
473 GP_REG, /* 'Rgp' */ 493 R0R1_CD_REGS, /* 'Rsd' */
474 FP_REG, /* 'f' */ 494 R0R3_CD_REGS, /* 'Rcd' */
475 SP_REGS, /* 'b' */
476 LPCOUNT_REG, /* 'l' */
477 LINK_REGS, /* 'k' */
478 DOUBLE_REGS, /* D0, D1 */
479 SIMD_VR_REGS, /* VR00-VR63 */
480 SIMD_DMA_CONFIG_REGS, /* DI0-DI7,DO0-DO7 */
481 ARCOMPACT16_REGS, /* 'q' */ 495 ARCOMPACT16_REGS, /* 'q' */
482 AC16_BASE_REGS, /* 'e' */
483 SIBCALL_REGS, /* "Rsc" */ 496 SIBCALL_REGS, /* "Rsc" */
497 AC16_H_REGS, /* 'h' */
498 DOUBLE_REGS, /* 'D' */
484 GENERAL_REGS, /* 'r' */ 499 GENERAL_REGS, /* 'r' */
485 MPY_WRITABLE_CORE_REGS, /* 'W' */ 500 SIMD_VR_REGS, /* 'v' */
486 WRITABLE_CORE_REGS, /* 'w' */ 501 SIMD_DMA_CONFIG_REGS, /* 'd' */
487 CHEAP_CORE_REGS, /* 'c' */
488 ALL_CORE_REGS, /* 'Rac' */
489 R0R3_CD_REGS, /* 'Rcd' */
490 R0R1_CD_REGS, /* 'Rsd' */
491 AC16_H_REGS, /* 'h' */
492 ALL_REGS, 502 ALL_REGS,
493 LIM_REG_CLASSES 503 LIM_REG_CLASSES
494 }; 504 };
495 505
496 #define N_REG_CLASSES (int) LIM_REG_CLASSES 506 #define N_REG_CLASSES (int) LIM_REG_CLASSES
497 507
498 /* Give names of register classes as strings for dump file. */ 508 /* Give names of register classes as strings for dump file. */
499 #define REG_CLASS_NAMES \ 509 #define REG_CLASS_NAMES \
500 { \ 510 { \
501 "NO_REGS", \ 511 "NO_REGS", \
502 "R0_REGS", \ 512 "R0_REGS", \
503 "GP_REG", \ 513 "R0R1_CD_REGS", \
504 "FP_REG", \ 514 "R0R3_CD_REGS", \
505 "SP_REGS", \ 515 "ARCOMPACT16_REGS", \
506 "LPCOUNT_REG", \ 516 "SIBCALL_REGS", \
507 "LINK_REGS", \ 517 "AC16_H_REGS", \
508 "DOUBLE_REGS", \ 518 "DOUBLE_REGS", \
509 "SIMD_VR_REGS", \ 519 "GENERAL_REGS", \
520 "SIMD_VR_REGS", \
510 "SIMD_DMA_CONFIG_REGS", \ 521 "SIMD_DMA_CONFIG_REGS", \
511 "ARCOMPACT16_REGS", \ 522 "ALL_REGS" \
512 "AC16_BASE_REGS", \
513 "SIBCALL_REGS", \
514 "GENERAL_REGS", \
515 "MPY_WRITABLE_CORE_REGS", \
516 "WRITABLE_CORE_REGS", \
517 "CHEAP_CORE_REGS", \
518 "R0R3_CD_REGS", \
519 "R0R1_CD_REGS", \
520 "AC16_H_REGS", \
521 "ALL_CORE_REGS", \
522 "ALL_REGS" \
523 } 523 }
524 524
525 /* Define which registers fit in which classes. 525 /* Define which registers fit in which classes.
526 This is an initializer for a vector of HARD_REG_SET 526 This is an initializer for a vector of HARD_REG_SET
527 of length N_REG_CLASSES. */ 527 of length N_REG_CLASSES. */
528 528
529 #define REG_CLASS_CONTENTS \ 529 #define REG_CLASS_CONTENTS \
530 { \ 530 { \
531 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* No Registers */ \ 531 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* NO_REGS. */\
532 {0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'x', r0 register , r0 */ \ 532 {0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'x'. */ \
533 {0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rgp', Global Pointer, r26 */ \ 533 {0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsd'. */ \
534 {0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'f', Frame Pointer, r27 */ \ 534 {0x0000000f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rcd'. */ \
535 {0x10000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'b', Stack Pointer, r28 */ \ 535 {0x0000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'q'. */ \
536 {0x00000000, 0x10000000, 0x00000000, 0x00000000, 0x00000000}, /* 'l', LPCOUNT Register, r60 */ \ 536 {0x00001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsc'. */ \
537 {0xe0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'k', LINK Registers, r29-r31 */ \ 537 {0x9fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'h'. */ \
538 {0x00000000, 0x00000f00, 0x00000000, 0x00000000, 0x00000000}, /* 'D', D1, D2 Registers */ \ 538 {0x00000000, 0x00000f00, 0x00000000, 0x00000000, 0x00000000}, /* 'D'. */ \
539 {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000}, /* 'V', VR00-VR63 Registers */ \ 539 {0xffffffff, 0x8fffffff, 0x00000000, 0x00000000, 0x00030000}, /* 'r'. */ \
540 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffff}, /* 'V', DI0-7,DO0-7 Registers */ \ 540 {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000}, /* 'v'. */ \
541 {0x0000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'q', r0-r3, r12-r15 */ \ 541 {0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000ffff}, /* 'd'. */ \
542 {0x1000f00f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'e', r0-r3, r12-r15, sp */ \ 542 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff} /* ALL_REGS. */\
543 {0x1c001fff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* "Rsc", r0-r12 */ \
544 {0x9fffffff, 0x80000000, 0x00000000, 0x00000000, 0x00000000}, /* 'r', r0-r28, blink, ap and pcl */ \
545 {0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'W', r0-r31 */ \
546 /* Include ap / pcl in WRITABLE_CORE_REGS for sake of symmetry. As these \
547 registers are fixed, it does not affect the literal meaning of the \
548 constraints, but it makes it a superset of GENERAL_REGS, thus \
549 enabling some operations that would otherwise not be possible. */ \
550 {0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'w', r0-r31, r60 */ \
551 {0xffffffff, 0x9fffffff, 0x00000000, 0x00000000, 0x00000000}, /* 'c', r0-r60, ap, pcl */ \
552 {0xffffffff, 0x9fffffff, 0x00000000, 0x00000000, 0x00000000}, /* 'Rac', r0-r60, ap, pcl */ \
553 {0x0000000f, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rcd', r0-r3 */ \
554 {0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'Rsd', r0-r1 */ \
555 {0x9fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, /* 'h', r0-28, r30 */ \
556 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff} /* All Registers */ \
557 } 543 }
558 544
559 /* Local macros to mark the first and last regs of different classes. */ 545 /* Local macros to mark the first and last regs of different classes. */
560 #define ARC_FIRST_SIMD_VR_REG 64 546 #define ARC_FIRST_SIMD_VR_REG 64
561 #define ARC_LAST_SIMD_VR_REG 127 547 #define ARC_LAST_SIMD_VR_REG 127
588 #define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS) 574 #define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS)
589 575
590 /* The class value for valid base registers. A base register is one used in 576 /* The class value for valid base registers. A base register is one used in
591 an address which is the register value plus a displacement. */ 577 an address which is the register value plus a displacement. */
592 578
593 #define BASE_REG_CLASS (TARGET_MIXED_CODE ? AC16_BASE_REGS : GENERAL_REGS) 579 #define BASE_REG_CLASS GENERAL_REGS
594 580
595 /* These assume that REGNO is a hard or pseudo reg number. 581 /* These assume that REGNO is a hard or pseudo reg number.
596 They give nonzero only if REGNO is a hard reg of the suitable class 582 They give nonzero only if REGNO is a hard reg of the suitable class
597 or a pseudo reg currently allocated to a suitable hard reg. 583 or a pseudo reg currently allocated to a suitable hard reg.
598 Since they use reg_renumber, they are safe only once reg_renumber 584 Since they use reg_renumber, they are safe only once reg_renumber
599 has been allocated, which happens in local-alloc.c. */ 585 has been allocated, which happens in local-alloc.c. */
600 #define REGNO_OK_FOR_BASE_P(REGNO) \ 586 #define REGNO_OK_FOR_BASE_P(REGNO) \
601 ((REGNO) < 29 || ((REGNO) == ARG_POINTER_REGNUM) || ((REGNO) == 63) \ 587 ((REGNO) < 29 \
588 || ((REGNO) == ARG_POINTER_REGNUM) \
589 || ((REGNO) == FRAME_POINTER_REGNUM) \
590 || ((REGNO) == PCL_REG) \
602 || ((unsigned) reg_renumber[REGNO] < 29) \ 591 || ((unsigned) reg_renumber[REGNO] < 29) \
603 || ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \ 592 || ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \
604 || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)) \ 593 || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)) \
605 || ((REGNO) == 30 && fixed_regs[REGNO] == 0)) 594 || (fixed_regs[REGNO] == 0 && (REGNO) == R30_REG))
606 595
607 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) 596 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
608 597
609 /* Given an rtx X being reloaded into a reg required to be 598 /* Given an rtx X being reloaded into a reg required to be
610 in class CLASS, return the class of reg to actually use. 599 in class CLASS, return the class of reg to actually use.
686 675
687 /* Register to use for pushing function arguments. */ 676 /* Register to use for pushing function arguments. */
688 #define STACK_POINTER_REGNUM 28 677 #define STACK_POINTER_REGNUM 28
689 678
690 /* Base register for access to local variables of the function. */ 679 /* Base register for access to local variables of the function. */
691 #define FRAME_POINTER_REGNUM 27 680 #define FRAME_POINTER_REGNUM 145
681 #define HARD_FRAME_POINTER_REGNUM 27
692 682
693 /* Base register for access to arguments of the function. This register 683 /* Base register for access to arguments of the function. This register
694 will be eliminated into either fp or sp. */ 684 will be eliminated into either fp or sp. */
695 #define ARG_POINTER_REGNUM 62 685 #define ARG_POINTER_REGNUM 144
696 686
697 #define RETURN_ADDR_REGNUM 31 687 #define RETURN_ADDR_REGNUM 31
698 688
699 /* TODO - check usage of STATIC_CHAIN_REGNUM with a testcase */ 689 /* TODO - check usage of STATIC_CHAIN_REGNUM with a testcase */
700 /* Register in which static-chain is passed to a function. This must 690 /* Register in which static-chain is passed to a function. This must
800 register can often be eliminated in favor of the stack pointer register. 790 register can often be eliminated in favor of the stack pointer register.
801 */ 791 */
802 792
803 #define ELIMINABLE_REGS \ 793 #define ELIMINABLE_REGS \
804 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 794 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
805 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 795 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
806 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} 796 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
797 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
807 798
808 /* Define the offset between two registers, one to be eliminated, and the other 799 /* Define the offset between two registers, one to be eliminated, and the other
809 its replacement, at the start of a routine. */ 800 its replacement, at the start of a routine. */
810 extern int arc_initial_elimination_offset(int from, int to); 801 extern int arc_initial_elimination_offset(int from, int to);
811 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 802 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
812 (OFFSET) = arc_initial_elimination_offset ((FROM), (TO)) 803 (OFFSET) = arc_initial_elimination_offset ((FROM), (TO))
813 804
814 /* Output assembler code to FILE to increment profiler label # LABELNO 805 /* All the work done in PROFILE_HOOK, but still required. */
815 for profiling a function entry. */ 806 #undef FUNCTION_PROFILER
816 #define FUNCTION_PROFILER(FILE, LABELNO) \ 807 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
817 do { \
818 if (flag_pic) \
819 fprintf (FILE, "\tbl\t__mcount@plt\n"); \
820 else \
821 fprintf (FILE, "\tbl\t__mcount\n"); \
822 } while (0)
823 808
824 #define NO_PROFILE_COUNTERS 1 809 #define NO_PROFILE_COUNTERS 1
825 810
826 /* Trampolines. */ 811 /* Trampolines. */
827 812
938 /* Return non-zero if SELECT_CC_MODE will never return MODE for a 923 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
939 floating point inequality comparison. */ 924 floating point inequality comparison. */
940 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ 925 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/
941 926
942 /* Costs. */ 927 /* Costs. */
943
944 /* Compute extra cost of moving data between one register class
945 and another. */
946 #define REGISTER_MOVE_COST(MODE, CLASS, TO_CLASS) \
947 arc_register_move_cost ((MODE), (CLASS), (TO_CLASS))
948
949 /* Compute the cost of moving data between registers and memory. */
950 /* Memory is 3 times as expensive as registers.
951 ??? Is that the right way to look at it? */
952 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \
953 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12)
954 928
955 /* The cost of a branch insn. */ 929 /* The cost of a branch insn. */
956 /* ??? What's the right value here? Branches are certainly more 930 /* ??? What's the right value here? Branches are certainly more
957 expensive than reg->reg moves. */ 931 expensive than reg->reg moves. */
958 #define BRANCH_COST(speed_p, predictable_p) 2 932 #define BRANCH_COST(speed_p, predictable_p) 2
1201 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 1175 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
1202 "r24", "r25", "gp", "fp", "sp", rname29, rname30, "blink", \ 1176 "r24", "r25", "gp", "fp", "sp", rname29, rname30, "blink", \
1203 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ 1177 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
1204 "d1", "d1", "d2", "d2", "r44", "r45", "r46", "r47", \ 1178 "d1", "d1", "d2", "d2", "r44", "r45", "r46", "r47", \
1205 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ 1179 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
1206 rname56,rname57,rname58,rname59,"lp_count", "cc", "ap", "pcl", \ 1180 rname56,rname57,rname58,rname59,"lp_count", "cc", "limm", "pcl", \
1207 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", \ 1181 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", \
1208 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", \ 1182 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", \
1209 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", \ 1183 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", \
1210 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31", \ 1184 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31", \
1211 "vr32", "vr33", "vr34", "vr35", "vr36", "vr37", "vr38", "vr39", \ 1185 "vr32", "vr33", "vr34", "vr35", "vr36", "vr37", "vr38", "vr39", \
1212 "vr40", "vr41", "vr42", "vr43", "vr44", "vr45", "vr46", "vr47", \ 1186 "vr40", "vr41", "vr42", "vr43", "vr44", "vr45", "vr46", "vr47", \
1213 "vr48", "vr49", "vr50", "vr51", "vr52", "vr53", "vr54", "vr55", \ 1187 "vr48", "vr49", "vr50", "vr51", "vr52", "vr53", "vr54", "vr55", \
1214 "vr56", "vr57", "vr58", "vr59", "vr60", "vr61", "vr62", "vr63", \ 1188 "vr56", "vr57", "vr58", "vr59", "vr60", "vr61", "vr62", "vr63", \
1215 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \ 1189 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \
1216 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \ 1190 "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", \
1217 "lp_start", "lp_end" \ 1191 "arg", "frame" \
1218 } 1192 }
1219 1193
1220 #define ADDITIONAL_REGISTER_NAMES \ 1194 #define ADDITIONAL_REGISTER_NAMES \
1221 { \ 1195 { \
1222 {"ilink", 29}, \ 1196 {"ilink", 29}, \
1264 do { \ 1238 do { \
1265 char label[30]; \ 1239 char label[30]; \
1266 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1240 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1267 fprintf (FILE, "\t.word "); \ 1241 fprintf (FILE, "\t.word "); \
1268 assemble_name (FILE, label); \ 1242 assemble_name (FILE, label); \
1269 fprintf(FILE, "\n"); \ 1243 fprintf (FILE, "\n"); \
1270 } while (0) 1244 } while (0)
1271 1245
1272 /* This is how to output an element of a case-vector that is relative. */ 1246 /* This is how to output an element of a case-vector that is relative. */
1273 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1247 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1274 do { \ 1248 do { \
1275 char label[30]; \ 1249 char label[30]; \
1276 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1250 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1277 switch (GET_MODE (BODY)) \ 1251 if (!TARGET_BI_BIH) \
1278 { \ 1252 { \
1279 case E_QImode: fprintf (FILE, "\t.byte "); break; \ 1253 switch (GET_MODE (BODY)) \
1280 case E_HImode: fprintf (FILE, "\t.hword "); break; \ 1254 { \
1281 case E_SImode: fprintf (FILE, "\t.word "); break; \ 1255 case E_QImode: fprintf (FILE, "\t.byte "); break; \
1282 default: gcc_unreachable (); \ 1256 case E_HImode: fprintf (FILE, "\t.hword "); break; \
1283 } \ 1257 case E_SImode: fprintf (FILE, "\t.word "); break; \
1284 assemble_name (FILE, label); \ 1258 default: gcc_unreachable (); \
1285 fprintf (FILE, "-"); \ 1259 } \
1286 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ 1260 assemble_name (FILE, label); \
1287 assemble_name (FILE, label); \ 1261 fprintf (FILE, "-"); \
1288 if (TARGET_COMPACT_CASESI) \ 1262 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \
1289 fprintf (FILE, " + %d", 4 + arc_get_unalign ()); \ 1263 assemble_name (FILE, label); \
1290 fprintf(FILE, "\n"); \ 1264 fprintf (FILE, "\n"); \
1291 } while (0) 1265 } \
1266 else \
1267 { \
1268 switch (GET_MODE (BODY)) \
1269 { \
1270 case E_SImode: fprintf (FILE, "\tb\t@"); break; \
1271 case E_HImode: \
1272 case E_QImode: fprintf (FILE, "\tb_s\t@"); break; \
1273 default: gcc_unreachable (); \
1274 } \
1275 assemble_name (FILE, label); \
1276 fprintf(FILE, "\n"); \
1277 } \
1278 } while (0)
1279
1280 /* Defined to also emit an .align in elfos.h. We don't want that. */
1281 #undef ASM_OUTPUT_CASE_LABEL
1292 1282
1293 /* ADDR_DIFF_VECs are in the text section and thus can affect the 1283 /* ADDR_DIFF_VECs are in the text section and thus can affect the
1294 current alignment. */ 1284 current alignment. */
1295 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ 1285 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \
1296 do \ 1286 do \
1350 /* Prefer STABS (for now). */ 1340 /* Prefer STABS (for now). */
1351 #undef PREFERRED_DEBUGGING_TYPE 1341 #undef PREFERRED_DEBUGGING_TYPE
1352 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 1342 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1353 1343
1354 /* How to renumber registers for dbx and gdb. */ 1344 /* How to renumber registers for dbx and gdb. */
1355 #define DBX_REGISTER_NUMBER(REGNO) \ 1345 #define DBX_REGISTER_NUMBER(REGNO) \
1356 ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \ 1346 ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \
1357 ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \ 1347 ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \
1358 : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 59) \ 1348 : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 58) \
1359 ? ((REGNO) == 57 \ 1349 ? (((REGNO) == 57) \
1360 ? 58 /* MMED */ \ 1350 ? 58 /* MMED */ \
1361 : ((REGNO) & 1) ^ TARGET_BIG_ENDIAN \ 1351 : 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \
1362 ? 59 /* MHI */ \
1363 : 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \
1364 : (REGNO)) 1352 : (REGNO))
1365 1353
1354 /* Use gcc hard register numbering for eh_frame. */
1366 #define DWARF_FRAME_REGNUM(REG) (REG) 1355 #define DWARF_FRAME_REGNUM(REG) (REG)
1367 1356
1357 /* Map register numbers held in the call frame info that gcc has
1358 collected using DWARF_FRAME_REGNUM to those that should be output
1359 in .debug_frame and .eh_frame. */
1360 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
1361 ((TARGET_MULMAC_32BY16_SET && (REGNO) >= 56 && (REGNO) <= 57) \
1362 ? ((REGNO) ^ !TARGET_BIG_ENDIAN) \
1363 : (TARGET_MUL64_SET && (REGNO) >= 57 && (REGNO) <= 58) \
1364 ? (((REGNO) == 57) \
1365 ? 58 /* MMED */ \
1366 : 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \
1367 : (REGNO))
1368
1368 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (31) 1369 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (31)
1369 1370
1370 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 31) 1371 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 31)
1371 1372
1372 /* Frame info. */ 1373 /* Frame info. */
1373 1374
1374 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 1375 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM)
1375 1376
1376 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 1377 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
1377
1378 #define EH_RETURN_HANDLER_RTX arc_eh_return_address_location ()
1379 1378
1380 /* Turn off splitting of long stabs. */ 1379 /* Turn off splitting of long stabs. */
1381 #define DBX_CONTIN_LENGTH 0 1380 #define DBX_CONTIN_LENGTH 0
1382 1381
1383 /* Miscellaneous. */ 1382 /* Miscellaneous. */
1384 1383
1385 /* Specify the machine mode that this machine uses 1384 /* Specify the machine mode that this machine uses
1386 for the index in the tablejump instruction. 1385 for the index in the tablejump instruction.
1387 If we have pc relative case vectors, we start the case vector shortening 1386 If we have pc relative case vectors, we start the case vector shortening
1388 with QImode. */ 1387 with QImode. */
1389 #define CASE_VECTOR_MODE \ 1388 #define CASE_VECTOR_MODE \
1390 ((optimize && (CASE_VECTOR_PC_RELATIVE || flag_pic)) ? QImode : Pmode) 1389 (TARGET_BI_BIH ? SImode \
1390 : (optimize && (CASE_VECTOR_PC_RELATIVE || flag_pic)) ? QImode : Pmode)
1391 1391
1392 /* Define as C expression which evaluates to nonzero if the tablejump 1392 /* Define as C expression which evaluates to nonzero if the tablejump
1393 instruction expects the table to contain offsets from the address of the 1393 instruction expects the table to contain offsets from the address of the
1394 table. 1394 table.
1395 Do not define this if the table should contain absolute addresses. */ 1395 Do not define this if the table should contain absolute addresses. */
1396 #define CASE_VECTOR_PC_RELATIVE TARGET_CASE_VECTOR_PC_RELATIVE 1396 #define CASE_VECTOR_PC_RELATIVE \
1397 1397 (TARGET_CASE_VECTOR_PC_RELATIVE || TARGET_BI_BIH)
1398 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ 1398
1399 CASE_VECTOR_SHORTEN_MODE_1 \ 1399 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1400 (MIN_OFFSET, TARGET_COMPACT_CASESI ? MAX_OFFSET + 6 : MAX_OFFSET, BODY) 1400 (TARGET_BI_BIH ? \
1401 1401 ((MIN_OFFSET) >= -512 && (MAX_OFFSET) <= 508 ? HImode : SImode) \
1402 #define CASE_VECTOR_SHORTEN_MODE_1(MIN_OFFSET, MAX_OFFSET, BODY) \ 1402 : ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1403 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ 1403 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1404 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ 1404 : (MIN_OFFSET) >= -128 && (MAX_OFFSET) <= 127 \
1405 : (MIN_OFFSET) >= -128 && (MAX_OFFSET) <= 127 \ 1405 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1406 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ 1406 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 65535 \
1407 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 65535 \ 1407 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, HImode) \
1408 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, HImode) \ 1408 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 \
1409 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 \ 1409 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, HImode) \
1410 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, HImode) \ 1410 : SImode))
1411 : SImode) 1411
1412 1412 #define ADDR_VEC_ALIGN(VEC_INSN) \
1413 #define ADDR_VEC_ALIGN(VEC_INSN) \ 1413 (TARGET_BI_BIH ? 0 \
1414 (exact_log2 (GET_MODE_SIZE (as_a <scalar_int_mode> \ 1414 : exact_log2 (GET_MODE_SIZE (as_a <scalar_int_mode> \
1415 (GET_MODE (PATTERN (VEC_INSN)))))) 1415 (GET_MODE (PATTERN (VEC_INSN))))))
1416 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
1417 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) \
1418 ASM_OUTPUT_ALIGN ((FILE), ADDR_VEC_ALIGN (TABLE))
1419 1416
1420 #define INSN_LENGTH_ALIGNMENT(INSN) \ 1417 #define INSN_LENGTH_ALIGNMENT(INSN) \
1421 ((JUMP_TABLE_DATA_P (INSN) \ 1418 ((JUMP_TABLE_DATA_P (INSN) \
1422 && GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC \ 1419 && GET_CODE (PATTERN (INSN)) == ADDR_DIFF_VEC \
1423 && GET_MODE (PATTERN (INSN)) == QImode) \ 1420 && GET_MODE (PATTERN (INSN)) == QImode) \
1436 1433
1437 /* Max number of bytes we can move from memory to memory 1434 /* Max number of bytes we can move from memory to memory
1438 in one reasonably fast instruction. */ 1435 in one reasonably fast instruction. */
1439 #define MOVE_MAX 4 1436 #define MOVE_MAX 4
1440 1437
1441 /* Undo the effects of the movmem pattern presence on STORE_BY_PIECES_P . */ 1438 /* Undo the effects of the cpymem pattern presence on STORE_BY_PIECES_P . */
1442 #define MOVE_RATIO(SPEED) ((SPEED) ? 15 : 3) 1439 #define MOVE_RATIO(SPEED) ((SPEED) ? 15 : 3)
1443 1440
1444 /* Define this to be nonzero if shift instructions ignore all but the 1441 /* Define this to be nonzero if shift instructions ignore all but the
1445 low-order few bits. 1442 low-order few bits.
1446 */ 1443 */
1543 1540
1544 #define REVERSE_CONDITION(CODE,MODE) \ 1541 #define REVERSE_CONDITION(CODE,MODE) \
1545 (((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode \ 1542 (((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode \
1546 || (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode \ 1543 || (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode \
1547 || (MODE) == CC_FPXmode || (MODE) == CC_FPU_UNEQmode \ 1544 || (MODE) == CC_FPXmode || (MODE) == CC_FPU_UNEQmode \
1548 || (MODE) == CC_FPUmode) \ 1545 || (MODE) == CC_FPUmode || (MODE) == CC_FPUEmode) \
1549 ? reverse_condition_maybe_unordered ((CODE)) \ 1546 ? reverse_condition_maybe_unordered ((CODE)) \
1550 : reverse_condition ((CODE))) 1547 : reverse_condition ((CODE)))
1551 1548
1552 #define ADJUST_INSN_LENGTH(X, LENGTH) \ 1549 #define ADJUST_INSN_LENGTH(X, LENGTH) \
1553 ((LENGTH) \ 1550 ((LENGTH) \
1636 #define TARGET_FPX_QUARK (TARGET_EM && TARGET_SPFP \ 1633 #define TARGET_FPX_QUARK (TARGET_EM && TARGET_SPFP \
1637 && (arc_fpu_build == FPX_QK)) 1634 && (arc_fpu_build == FPX_QK))
1638 /* DBNZ support is available for ARCv2 core3 and newer cpus. */ 1635 /* DBNZ support is available for ARCv2 core3 and newer cpus. */
1639 #define TARGET_DBNZ (TARGET_V2 && (arc_tune >= ARC_TUNE_CORE_3)) 1636 #define TARGET_DBNZ (TARGET_V2 && (arc_tune >= ARC_TUNE_CORE_3))
1640 1637
1638 /* BI/BIH feature macro. */
1639 #define TARGET_BI_BIH (TARGET_BRANCH_INDEX && TARGET_CODE_DENSITY)
1640
1641 /* The default option for BI/BIH instructions. */
1642 #define DEFAULT_BRANCH_INDEX 0
1643
1644 #ifndef TARGET_LRA
1645 #define TARGET_LRA arc_lra_p()
1646 #endif
1647
1641 #endif /* GCC_ARC_H */ 1648 #endif /* GCC_ARC_H */