Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/i386/cpuid.h @ 145:1830386684a0

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
children
comparison
equal deleted inserted replaced
131:84e7813d76e9 145:1830386684a0
1 /* 1 /*
2 * Copyright (C) 2007-2018 Free Software Foundation, Inc. 2 * Copyright (C) 2007-2020 Free Software Foundation, Inc.
3 * 3 *
4 * This file is free software; you can redistribute it and/or modify it 4 * This file is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the 5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 3, or (at your option) any 6 * Free Software Foundation; either version 3, or (at your option) any
7 * later version. 7 * later version.
18 * You should have received a copy of the GNU General Public License and 18 * You should have received a copy of the GNU General Public License and
19 * a copy of the GCC Runtime Library Exception along with this program; 19 * a copy of the GCC Runtime Library Exception along with this program;
20 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 20 * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
21 * <http://www.gnu.org/licenses/>. 21 * <http://www.gnu.org/licenses/>.
22 */ 22 */
23
24 /* %eax */
25 #define bit_AVX512BF16 (1 << 5)
23 26
24 /* %ecx */ 27 /* %ecx */
25 #define bit_SSE3 (1 << 0) 28 #define bit_SSE3 (1 << 0)
26 #define bit_PCLMUL (1 << 1) 29 #define bit_PCLMUL (1 << 1)
27 #define bit_LZCNT (1 << 5) 30 #define bit_LZCNT (1 << 5)
108 #define bit_AVX512BITALG (1 << 12) 111 #define bit_AVX512BITALG (1 << 12)
109 #define bit_AVX512VPOPCNTDQ (1 << 14) 112 #define bit_AVX512VPOPCNTDQ (1 << 14)
110 #define bit_RDPID (1 << 22) 113 #define bit_RDPID (1 << 22)
111 #define bit_MOVDIRI (1 << 27) 114 #define bit_MOVDIRI (1 << 27)
112 #define bit_MOVDIR64B (1 << 28) 115 #define bit_MOVDIR64B (1 << 28)
116 #define bit_ENQCMD (1 << 29)
113 #define bit_CLDEMOTE (1 << 25) 117 #define bit_CLDEMOTE (1 << 25)
114 118
115 /* %edx */ 119 /* %edx */
116 #define bit_AVX5124VNNIW (1 << 2) 120 #define bit_AVX5124VNNIW (1 << 2)
117 #define bit_AVX5124FMAPS (1 << 3) 121 #define bit_AVX5124FMAPS (1 << 3)
122 #define bit_AVX512VP2INTERSECT (1 << 8)
118 #define bit_IBT (1 << 20) 123 #define bit_IBT (1 << 20)
119 #define bit_PCONFIG (1 << 18) 124 #define bit_PCONFIG (1 << 18)
120 /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */ 125 /* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
121 #define bit_BNDREGS (1 << 3) 126 #define bit_BNDREGS (1 << 3)
122 #define bit_BNDCSR (1 << 4) 127 #define bit_BNDCSR (1 << 4)
124 /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */ 129 /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
125 #define bit_XSAVEOPT (1 << 0) 130 #define bit_XSAVEOPT (1 << 0)
126 #define bit_XSAVEC (1 << 1) 131 #define bit_XSAVEC (1 << 1)
127 #define bit_XSAVES (1 << 3) 132 #define bit_XSAVES (1 << 3)
128 133
134 /* PT sub leaf (%eax == 14, %ecx == 0) */
135 /* %ebx */
136 #define bit_PTWRITE (1 << 4)
137
129 /* Signatures for different CPU implementations as returned in uses 138 /* Signatures for different CPU implementations as returned in uses
130 of cpuid with level 0. */ 139 of cpuid with level 0. */
131 #define signature_AMD_ebx 0x68747541 140 #define signature_AMD_ebx 0x68747541
132 #define signature_AMD_ecx 0x444d4163 141 #define signature_AMD_ecx 0x444d4163
133 #define signature_AMD_edx 0x69746e65 142 #define signature_AMD_edx 0x69746e65
178 187
179 #define signature_VORTEX_ebx 0x74726f56 188 #define signature_VORTEX_ebx 0x74726f56
180 #define signature_VORTEX_ecx 0x436f5320 189 #define signature_VORTEX_ecx 0x436f5320
181 #define signature_VORTEX_edx 0x36387865 190 #define signature_VORTEX_edx 0x36387865
182 191
192 #ifndef __x86_64__
193 /* At least one cpu (Winchip 2) does not set %ebx and %ecx
194 for cpuid leaf 1. Forcibly zero the two registers before
195 calling cpuid as a precaution. */
196 #define __cpuid(level, a, b, c, d) \
197 do { \
198 if (__builtin_constant_p (level) && (level) != 1) \
199 __asm__ ("cpuid\n\t" \
200 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
201 : "0" (level)); \
202 else \
203 __asm__ ("cpuid\n\t" \
204 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
205 : "0" (level), "1" (0), "2" (0)); \
206 } while (0)
207 #else
183 #define __cpuid(level, a, b, c, d) \ 208 #define __cpuid(level, a, b, c, d) \
184 __asm__ ("cpuid\n\t" \ 209 __asm__ ("cpuid\n\t" \
185 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ 210 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
186 : "0" (level)) 211 : "0" (level))
212 #endif
187 213
188 #define __cpuid_count(level, count, a, b, c, d) \ 214 #define __cpuid_count(level, count, a, b, c, d) \
189 __asm__ ("cpuid\n\t" \ 215 __asm__ ("cpuid\n\t" \
190 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \ 216 : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
191 : "0" (level), "2" (count)) 217 : "0" (level), "2" (count))