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comparison gcc/config/mips/mips-msa.md @ 145:1830386684a0

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gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
children
comparison
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131:84e7813d76e9 145:1830386684a0
1 ;; Machine Description for MIPS MSA ASE 1 ;; Machine Description for MIPS MSA ASE
2 ;; Based on the MIPS MSA spec Revision 1.11 8/4/2014 2 ;; Based on the MIPS MSA spec Revision 1.11 8/4/2014
3 ;; 3 ;;
4 ;; Copyright (C) 2015-2018 Free Software Foundation, Inc. 4 ;; Copyright (C) 2015-2020 Free Software Foundation, Inc.
5 ;; 5 ;;
6 ;; This file is part of GCC. 6 ;; This file is part of GCC.
7 ;; 7 ;;
8 ;; GCC is free software; you can redistribute it and/or modify 8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by 9 ;; it under the terms of the GNU General Public License as published by
344 { 344 {
345 /* We need to do the SLDI operation in V16QImode and adjust 345 /* We need to do the SLDI operation in V16QImode and adjust
346 operands[2] accordingly. */ 346 operands[2] accordingly. */
347 rtx wd = gen_reg_rtx (V16QImode); 347 rtx wd = gen_reg_rtx (V16QImode);
348 rtx ws = gen_reg_rtx (V16QImode); 348 rtx ws = gen_reg_rtx (V16QImode);
349 emit_move_insn (ws, gen_rtx_SUBREG (V16QImode, operands[1], 0)); 349 emit_move_insn (ws, gen_lowpart (V16QImode, operands[1]));
350 rtx n = GEN_INT (val * GET_MODE_SIZE (<UNITMODE>mode)); 350 rtx n = GEN_INT (val * GET_MODE_SIZE (<UNITMODE>mode));
351 gcc_assert (INTVAL (n) < GET_MODE_NUNITS (V16QImode)); 351 gcc_assert (INTVAL (n) < GET_MODE_NUNITS (V16QImode));
352 emit_insn (gen_msa_sldi_b (wd, ws, ws, n)); 352 emit_insn (gen_msa_sldi_b (wd, ws, ws, n));
353 temp = gen_reg_rtx (<MODE>mode); 353 temp = gen_reg_rtx (<MODE>mode);
354 emit_move_insn (temp, gen_rtx_SUBREG (<MODE>mode, wd, 0)); 354 emit_move_insn (temp, gen_lowpart (<MODE>mode, wd));
355 } 355 }
356 emit_insn (gen_msa_vec_extract_<msafmt_f> (operands[0], temp)); 356 emit_insn (gen_msa_vec_extract_<msafmt_f> (operands[0], temp));
357 DONE; 357 DONE;
358 }) 358 })
359 359
434 mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands); 434 mips_expand_vec_cond_expr (<MSA:MODE>mode, <MSA:VIMODE>mode, operands);
435 DONE; 435 DONE;
436 }) 436 })
437 437
438 (define_insn "msa_insert_<msafmt_f>" 438 (define_insn "msa_insert_<msafmt_f>"
439 [(set (match_operand:MSA 0 "register_operand" "=f") 439 [(set (match_operand:MSA 0 "register_operand" "=f,f")
440 (vec_merge:MSA 440 (vec_merge:MSA
441 (vec_duplicate:MSA 441 (vec_duplicate:MSA
442 (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ")) 442 (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ,f"))
443 (match_operand:MSA 2 "register_operand" "0") 443 (match_operand:MSA 2 "register_operand" "0,0")
444 (match_operand 3 "const_<bitmask>_operand" "")))] 444 (match_operand 3 "const_<bitmask>_operand" "")))]
445 "ISA_HAS_MSA" 445 "ISA_HAS_MSA"
446 { 446 {
447 if (which_alternative == 1)
448 return "insve.<msafmt>\t%w0[%y3],%w1[0]";
449
447 if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode)) 450 if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode))
448 return "#"; 451 return "#";
449 else 452 else
450 return "insert.<msafmt>\t%w0[%y3],%z1"; 453 return "insert.<msafmt>\t%w0[%y3],%z1";
451 } 454 }
460 (match_operand:MSA_D 2 "register_operand") 463 (match_operand:MSA_D 2 "register_operand")
461 (match_operand 3 "const_<bitmask>_operand")))] 464 (match_operand 3 "const_<bitmask>_operand")))]
462 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT" 465 "reload_completed && ISA_HAS_MSA && !TARGET_64BIT"
463 [(const_int 0)] 466 [(const_int 0)]
464 { 467 {
468 if (REG_P (operands[1]) && FP_REG_P (REGNO (operands[1])))
469 FAIL;
465 mips_split_msa_insert_d (operands[0], operands[2], operands[3], operands[1]); 470 mips_split_msa_insert_d (operands[0], operands[2], operands[3], operands[1]);
466 DONE; 471 DONE;
467 }) 472 })
468 473
469 (define_insn "msa_insve_<msafmt_f>" 474 (define_insn "msa_insve_<msafmt_f>"
2712 MIPS_BRANCH ("<msabr_neg>.<msafmt>", 2717 MIPS_BRANCH ("<msabr_neg>.<msafmt>",
2713 "%w1,%0")); 2718 "%w1,%0"));
2714 } 2719 }
2715 [(set_attr "type" "simd_branch") 2720 [(set_attr "type" "simd_branch")
2716 (set_attr "mode" "<MODE>") 2721 (set_attr "mode" "<MODE>")
2717 (set_attr "compact_form" "never")]) 2722 (set_attr "compact_form" "never")
2723 (set_attr "branch_likely" "no")])
2718 2724
2719 (define_insn "msa_<msabr>_v_<msafmt_f>" 2725 (define_insn "msa_<msabr>_v_<msafmt_f>"
2720 [(set (pc) (if_then_else 2726 [(set (pc) (if_then_else
2721 (equality_op 2727 (equality_op
2722 (unspec:SI [(match_operand:MSA 1 "register_operand" "f")] 2728 (unspec:SI [(match_operand:MSA 1 "register_operand" "f")]
2731 MIPS_BRANCH ("<msabr_neg>.v", 2737 MIPS_BRANCH ("<msabr_neg>.v",
2732 "%w1,%0")); 2738 "%w1,%0"));
2733 } 2739 }
2734 [(set_attr "type" "simd_branch") 2740 [(set_attr "type" "simd_branch")
2735 (set_attr "mode" "TI") 2741 (set_attr "mode" "TI")
2736 (set_attr "compact_form" "never")]) 2742 (set_attr "compact_form" "never")
2743 (set_attr "branch_likely" "no")])