Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/mips/mips.c @ 145:1830386684a0

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
children
comparison
equal deleted inserted replaced
131:84e7813d76e9 145:1830386684a0
1 /* Subroutines used for MIPS code generation. 1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2018 Free Software Foundation, Inc. 2 Copyright (C) 1989-2020 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr. 3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org. 4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and 5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com. 6 Brendan Eich, brendan@microunity.com.
7 7
834 DEFAULT_COSTS 834 DEFAULT_COSTS
835 }, 835 },
836 { /* Loongson-2F */ 836 { /* Loongson-2F */
837 DEFAULT_COSTS 837 DEFAULT_COSTS
838 }, 838 },
839 { /* Loongson-3A */ 839 { /* Loongson gs464. */
840 DEFAULT_COSTS
841 },
842 { /* Loongson gs464e. */
843 DEFAULT_COSTS
844 },
845 { /* Loongson gs264e. */
840 DEFAULT_COSTS 846 DEFAULT_COSTS
841 }, 847 },
842 { /* M4k */ 848 { /* M4k */
843 DEFAULT_COSTS 849 DEFAULT_COSTS
844 }, 850 },
2401 into register R. If R does not get allocated a hard register, and 2407 into register R. If R does not get allocated a hard register, and
2402 R is used in an operand that allows both registers and memory 2408 R is used in an operand that allows both registers and memory
2403 references, reload will consider forcing C into memory and using 2409 references, reload will consider forcing C into memory and using
2404 one of the instruction's memory alternatives. Returning false 2410 one of the instruction's memory alternatives. Returning false
2405 here will force it to use an input reload instead. */ 2411 here will force it to use an input reload instead. */
2406 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x)) 2412 if ((CONST_INT_P (x) || GET_CODE (x) == CONST_VECTOR)
2413 && mips_legitimate_constant_p (mode, x))
2407 return true; 2414 return true;
2408 2415
2409 split_const (x, &base, &offset); 2416 split_const (x, &base, &offset);
2410 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type)) 2417 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
2411 { 2418 {
3023 3030
3024 static void 3031 static void
3025 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type) 3032 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
3026 { 3033 {
3027 if (mips_split_move_p (dest, src, split_type)) 3034 if (mips_split_move_p (dest, src, split_type))
3028 mips_split_move (dest, src, split_type); 3035 mips_split_move (dest, src, split_type, NULL);
3029 else 3036 else
3030 mips_emit_move (dest, src); 3037 mips_emit_move (dest, src);
3031 } 3038 }
3032 3039
3033 /* Emit an instruction of the form (set TARGET (CODE OP0)). */ 3040 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
4772 /* Otherwise split all multiword moves. */ 4779 /* Otherwise split all multiword moves. */
4773 return size > UNITS_PER_WORD; 4780 return size > UNITS_PER_WORD;
4774 } 4781 }
4775 4782
4776 /* Split a move from SRC to DEST, given that mips_split_move_p holds. 4783 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4777 SPLIT_TYPE describes the split condition. */ 4784 SPLIT_TYPE describes the split condition. INSN is the insn being
4785 split, if we know it, NULL otherwise. */
4778 4786
4779 void 4787 void
4780 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type) 4788 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type, rtx insn_)
4781 { 4789 {
4782 rtx low_dest; 4790 rtx low_dest;
4783 4791
4784 gcc_checking_assert (mips_split_move_p (dest, src, split_type)); 4792 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4785 if (MSA_SUPPORTED_MODE_P (GET_MODE (dest))) 4793 if (MSA_SUPPORTED_MODE_P (GET_MODE (dest)))
4833 } 4841 }
4834 else 4842 else
4835 { 4843 {
4836 mips_emit_move (low_dest, mips_subword (src, false)); 4844 mips_emit_move (low_dest, mips_subword (src, false));
4837 mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); 4845 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4846 }
4847 }
4848
4849 /* This is a hack. See if the next insn uses DEST and if so, see if we
4850 can forward SRC for DEST. This is most useful if the next insn is a
4851 simple store. */
4852 rtx_insn *insn = (rtx_insn *)insn_;
4853 struct mips_address_info addr = {};
4854 if (insn)
4855 {
4856 rtx_insn *next = next_nonnote_nondebug_insn_bb (insn);
4857 if (next)
4858 {
4859 rtx set = single_set (next);
4860 if (set && SET_SRC (set) == dest)
4861 {
4862 if (MEM_P (src))
4863 {
4864 rtx tmp = XEXP (src, 0);
4865 mips_classify_address (&addr, tmp, GET_MODE (tmp), true);
4866 if (addr.reg && !reg_overlap_mentioned_p (dest, addr.reg))
4867 validate_change (next, &SET_SRC (set), src, false);
4868 }
4869 else
4870 validate_change (next, &SET_SRC (set), src, false);
4871 }
4838 } 4872 }
4839 } 4873 }
4840 } 4874 }
4841 4875
4842 /* Return the split type for instruction INSN. */ 4876 /* Return the split type for instruction INSN. */
5062 holds. */ 5096 holds. */
5063 5097
5064 void 5098 void
5065 mips_split_move_insn (rtx dest, rtx src, rtx insn) 5099 mips_split_move_insn (rtx dest, rtx src, rtx insn)
5066 { 5100 {
5067 mips_split_move (dest, src, mips_insn_split_type (insn)); 5101 mips_split_move (dest, src, mips_insn_split_type (insn), insn);
5068 } 5102 }
5069 5103
5070 /* Return the appropriate instructions to move SRC into DEST. Assume 5104 /* Return the appropriate instructions to move SRC into DEST. Assume
5071 that SRC is operand 1 and DEST is operand 0. */ 5105 that SRC is operand 1 and DEST is operand 0. */
5072 5106
5941 } 5975 }
5942 5976
5943 /* Implement TARGET_FUNCTION_ARG. */ 5977 /* Implement TARGET_FUNCTION_ARG. */
5944 5978
5945 static rtx 5979 static rtx
5946 mips_function_arg (cumulative_args_t cum_v, machine_mode mode, 5980 mips_function_arg (cumulative_args_t cum_v, const function_arg_info &arg)
5947 const_tree type, bool named)
5948 { 5981 {
5949 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 5982 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5950 struct mips_arg_info info; 5983 struct mips_arg_info info;
5951 5984
5952 /* We will be called with a mode of VOIDmode after the last argument 5985 /* We will be called with an end marker after the last argument
5953 has been seen. Whatever we return will be passed to the call expander. 5986 has been seen. Whatever we return will be passed to the call expander.
5954 If we need a MIPS16 fp_code, return a REG with the code stored as 5987 If we need a MIPS16 fp_code, return a REG with the code stored as
5955 the mode. */ 5988 the mode. */
5956 if (mode == VOIDmode) 5989 if (arg.end_marker_p ())
5957 { 5990 {
5958 if (TARGET_MIPS16 && cum->fp_code != 0) 5991 if (TARGET_MIPS16 && cum->fp_code != 0)
5959 return gen_rtx_REG ((machine_mode) cum->fp_code, 0); 5992 return gen_rtx_REG ((machine_mode) cum->fp_code, 0);
5960 else 5993 else
5961 return NULL; 5994 return NULL;
5962 } 5995 }
5963 5996
5964 mips_get_arg_info (&info, cum, mode, type, named); 5997 mips_get_arg_info (&info, cum, arg.mode, arg.type, arg.named);
5965 5998
5966 /* Return straight away if the whole argument is passed on the stack. */ 5999 /* Return straight away if the whole argument is passed on the stack. */
5967 if (info.reg_offset == MAX_ARGS_IN_REGISTERS) 6000 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5968 return NULL; 6001 return NULL;
5969 6002
5970 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure 6003 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5971 contains a double in its entirety, then that 64-bit chunk is passed 6004 contains a double in its entirety, then that 64-bit chunk is passed
5972 in a floating-point register. */ 6005 in a floating-point register. */
5973 if (TARGET_NEWABI 6006 if (TARGET_NEWABI
5974 && TARGET_HARD_FLOAT 6007 && TARGET_HARD_FLOAT
5975 && named 6008 && arg.named
5976 && type != 0 6009 && arg.type != 0
5977 && TREE_CODE (type) == RECORD_TYPE 6010 && TREE_CODE (arg.type) == RECORD_TYPE
5978 && TYPE_SIZE_UNIT (type) 6011 && TYPE_SIZE_UNIT (arg.type)
5979 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type))) 6012 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (arg.type)))
5980 { 6013 {
5981 tree field; 6014 tree field;
5982 6015
5983 /* First check to see if there is any such field. */ 6016 /* First check to see if there is any such field. */
5984 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) 6017 for (field = TYPE_FIELDS (arg.type); field; field = DECL_CHAIN (field))
5985 if (TREE_CODE (field) == FIELD_DECL 6018 if (TREE_CODE (field) == FIELD_DECL
5986 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) 6019 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5987 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD 6020 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5988 && tree_fits_shwi_p (bit_position (field)) 6021 && tree_fits_shwi_p (bit_position (field))
5989 && int_bit_position (field) % BITS_PER_WORD == 0) 6022 && int_bit_position (field) % BITS_PER_WORD == 0)
5998 HOST_WIDE_INT bitpos; 6031 HOST_WIDE_INT bitpos;
5999 rtx ret; 6032 rtx ret;
6000 6033
6001 /* assign_parms checks the mode of ENTRY_PARM, so we must 6034 /* assign_parms checks the mode of ENTRY_PARM, so we must
6002 use the actual mode here. */ 6035 use the actual mode here. */
6003 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words)); 6036 ret = gen_rtx_PARALLEL (arg.mode, rtvec_alloc (info.reg_words));
6004 6037
6005 bitpos = 0; 6038 bitpos = 0;
6006 field = TYPE_FIELDS (type); 6039 field = TYPE_FIELDS (arg.type);
6007 for (i = 0; i < info.reg_words; i++) 6040 for (i = 0; i < info.reg_words; i++)
6008 { 6041 {
6009 rtx reg; 6042 rtx reg;
6010 6043
6011 for (; field; field = DECL_CHAIN (field)) 6044 for (; field; field = DECL_CHAIN (field))
6034 /* Handle the n32/n64 conventions for passing complex floating-point 6067 /* Handle the n32/n64 conventions for passing complex floating-point
6035 arguments in FPR pairs. The real part goes in the lower register 6068 arguments in FPR pairs. The real part goes in the lower register
6036 and the imaginary part goes in the upper register. */ 6069 and the imaginary part goes in the upper register. */
6037 if (TARGET_NEWABI 6070 if (TARGET_NEWABI
6038 && info.fpr_p 6071 && info.fpr_p
6039 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 6072 && GET_MODE_CLASS (arg.mode) == MODE_COMPLEX_FLOAT)
6040 { 6073 {
6041 rtx real, imag; 6074 rtx real, imag;
6042 machine_mode inner; 6075 machine_mode inner;
6043 unsigned int regno; 6076 unsigned int regno;
6044 6077
6045 inner = GET_MODE_INNER (mode); 6078 inner = GET_MODE_INNER (arg.mode);
6046 regno = FP_ARG_FIRST + info.reg_offset; 6079 regno = FP_ARG_FIRST + info.reg_offset;
6047 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner)) 6080 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
6048 { 6081 {
6049 /* Real part in registers, imaginary part on stack. */ 6082 /* Real part in registers, imaginary part on stack. */
6050 gcc_assert (info.stack_words == info.reg_words); 6083 gcc_assert (info.stack_words == info.reg_words);
6058 const0_rtx); 6091 const0_rtx);
6059 imag = gen_rtx_EXPR_LIST (VOIDmode, 6092 imag = gen_rtx_EXPR_LIST (VOIDmode,
6060 gen_rtx_REG (inner, 6093 gen_rtx_REG (inner,
6061 regno + info.reg_words / 2), 6094 regno + info.reg_words / 2),
6062 GEN_INT (GET_MODE_SIZE (inner))); 6095 GEN_INT (GET_MODE_SIZE (inner)));
6063 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag)); 6096 return gen_rtx_PARALLEL (arg.mode, gen_rtvec (2, real, imag));
6064 } 6097 }
6065 } 6098 }
6066 6099
6067 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT)); 6100 return gen_rtx_REG (arg.mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
6068 } 6101 }
6069 6102
6070 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */ 6103 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
6071 6104
6072 static void 6105 static void
6073 mips_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, 6106 mips_function_arg_advance (cumulative_args_t cum_v,
6074 const_tree type, bool named) 6107 const function_arg_info &arg)
6075 { 6108 {
6076 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 6109 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
6077 struct mips_arg_info info; 6110 struct mips_arg_info info;
6078 6111
6079 mips_get_arg_info (&info, cum, mode, type, named); 6112 mips_get_arg_info (&info, cum, arg.mode, arg.type, arg.named);
6080 6113
6081 if (!info.fpr_p) 6114 if (!info.fpr_p)
6082 cum->gp_reg_found = true; 6115 cum->gp_reg_found = true;
6083 6116
6084 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for 6117 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
6085 an explanation of what this code does. It assumes that we're using 6118 an explanation of what this code does. It assumes that we're using
6086 either the o32 or the o64 ABI, both of which pass at most 2 arguments 6119 either the o32 or the o64 ABI, both of which pass at most 2 arguments
6087 in FPRs. */ 6120 in FPRs. */
6088 if (cum->arg_number < 2 && info.fpr_p) 6121 if (cum->arg_number < 2 && info.fpr_p)
6089 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2); 6122 cum->fp_code += (arg.mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
6090 6123
6091 /* Advance the register count. This has the effect of setting 6124 /* Advance the register count. This has the effect of setting
6092 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned 6125 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
6093 argument required us to skip the final GPR and pass the whole 6126 argument required us to skip the final GPR and pass the whole
6094 argument on the stack. */ 6127 argument on the stack. */
6105 } 6138 }
6106 6139
6107 /* Implement TARGET_ARG_PARTIAL_BYTES. */ 6140 /* Implement TARGET_ARG_PARTIAL_BYTES. */
6108 6141
6109 static int 6142 static int
6110 mips_arg_partial_bytes (cumulative_args_t cum, 6143 mips_arg_partial_bytes (cumulative_args_t cum, const function_arg_info &arg)
6111 machine_mode mode, tree type, bool named)
6112 { 6144 {
6113 struct mips_arg_info info; 6145 struct mips_arg_info info;
6114 6146
6115 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named); 6147 mips_get_arg_info (&info, get_cumulative_args (cum),
6148 arg.mode, arg.type, arg.named);
6116 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0; 6149 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
6117 } 6150 }
6118 6151
6119 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at 6152 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
6120 least PARM_BOUNDARY bits of alignment, but will be given anything up 6153 least PARM_BOUNDARY bits of alignment, but will be given anything up
6200 } 6233 }
6201 6234
6202 /* Return nonzero when an argument must be passed by reference. */ 6235 /* Return nonzero when an argument must be passed by reference. */
6203 6236
6204 static bool 6237 static bool
6205 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED, 6238 mips_pass_by_reference (cumulative_args_t, const function_arg_info &arg)
6206 machine_mode mode, const_tree type,
6207 bool named ATTRIBUTE_UNUSED)
6208 { 6239 {
6209 if (mips_abi == ABI_EABI) 6240 if (mips_abi == ABI_EABI)
6210 { 6241 {
6211 int size; 6242 int size;
6212 6243
6213 /* ??? How should SCmode be handled? */ 6244 /* ??? How should SCmode be handled? */
6214 if (mode == DImode || mode == DFmode 6245 if (arg.mode == DImode || arg.mode == DFmode
6215 || mode == DQmode || mode == UDQmode 6246 || arg.mode == DQmode || arg.mode == UDQmode
6216 || mode == DAmode || mode == UDAmode) 6247 || arg.mode == DAmode || arg.mode == UDAmode)
6217 return 0; 6248 return 0;
6218 6249
6219 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 6250 size = arg.type_size_in_bytes ();
6220 return size == -1 || size > UNITS_PER_WORD; 6251 return size == -1 || size > UNITS_PER_WORD;
6221 } 6252 }
6222 else 6253 else
6223 { 6254 {
6224 /* If we have a variable-sized parameter, we have no choice. */ 6255 /* If we have a variable-sized parameter, we have no choice. */
6225 return targetm.calls.must_pass_in_stack (mode, type); 6256 return targetm.calls.must_pass_in_stack (arg);
6226 } 6257 }
6227 } 6258 }
6228 6259
6229 /* Implement TARGET_CALLEE_COPIES. */ 6260 /* Implement TARGET_CALLEE_COPIES. */
6230 6261
6231 static bool 6262 static bool
6232 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED, 6263 mips_callee_copies (cumulative_args_t, const function_arg_info &arg)
6233 machine_mode mode ATTRIBUTE_UNUSED, 6264 {
6234 const_tree type ATTRIBUTE_UNUSED, bool named) 6265 return mips_abi == ABI_EABI && arg.named;
6235 {
6236 return mips_abi == ABI_EABI && named;
6237 } 6266 }
6238 6267
6239 /* See whether VALTYPE is a record whose fields should be returned in 6268 /* See whether VALTYPE is a record whose fields should be returned in
6240 floating-point registers. If so, return the number of fields and 6269 floating-point registers. If so, return the number of fields and
6241 list them in FIELDS (which should have two elements). Return 0 6270 list them in FIELDS (which should have two elements). Return 0
6511 } 6540 }
6512 6541
6513 /* Implement TARGET_SETUP_INCOMING_VARARGS. */ 6542 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
6514 6543
6515 static void 6544 static void
6516 mips_setup_incoming_varargs (cumulative_args_t cum, machine_mode mode, 6545 mips_setup_incoming_varargs (cumulative_args_t cum,
6517 tree type, int *pretend_size ATTRIBUTE_UNUSED, 6546 const function_arg_info &arg,
6518 int no_rtl) 6547 int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
6519 { 6548 {
6520 CUMULATIVE_ARGS local_cum; 6549 CUMULATIVE_ARGS local_cum;
6521 int gp_saved, fp_saved; 6550 int gp_saved, fp_saved;
6522 6551
6523 /* The caller has advanced CUM up to, but not beyond, the last named 6552 /* The caller has advanced CUM up to, but not beyond, the last named
6524 argument. Advance a local copy of CUM past the last "real" named 6553 argument. Advance a local copy of CUM past the last "real" named
6525 argument, to find out how many registers are left over. */ 6554 argument, to find out how many registers are left over. */
6526 local_cum = *get_cumulative_args (cum); 6555 local_cum = *get_cumulative_args (cum);
6527 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type, 6556 mips_function_arg_advance (pack_cumulative_args (&local_cum), arg);
6528 true);
6529 6557
6530 /* Found out how many registers we need to save. */ 6558 /* Found out how many registers we need to save. */
6531 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; 6559 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
6532 fp_saved = (EABI_FLOAT_VARARGS_P 6560 fp_saved = (EABI_FLOAT_VARARGS_P
6533 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs 6561 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
6745 { 6773 {
6746 tree addr, t, type_size, rounded_size, valist_tmp; 6774 tree addr, t, type_size, rounded_size, valist_tmp;
6747 unsigned HOST_WIDE_INT align, boundary; 6775 unsigned HOST_WIDE_INT align, boundary;
6748 bool indirect; 6776 bool indirect;
6749 6777
6750 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false); 6778 indirect = pass_va_arg_by_reference (type);
6751 if (indirect) 6779 if (indirect)
6752 type = build_pointer_type (type); 6780 type = build_pointer_type (type);
6753 6781
6754 align = PARM_BOUNDARY / BITS_PER_UNIT; 6782 align = PARM_BOUNDARY / BITS_PER_UNIT;
6755 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type); 6783 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
6832 gimple_seq *post_p) 6860 gimple_seq *post_p)
6833 { 6861 {
6834 tree addr; 6862 tree addr;
6835 bool indirect_p; 6863 bool indirect_p;
6836 6864
6837 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0); 6865 indirect_p = pass_va_arg_by_reference (type);
6838 if (indirect_p) 6866 if (indirect_p)
6839 type = build_pointer_type (type); 6867 type = build_pointer_type (type);
6840 6868
6841 if (!EABI_FLOAT_VARARGS_P) 6869 if (!EABI_FLOAT_VARARGS_P)
6842 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p); 6870 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
7273 if (mode == SFmode) 7301 if (mode == SFmode)
7274 mips_output_32bit_xfer (direction, gparg, fparg); 7302 mips_output_32bit_xfer (direction, gparg, fparg);
7275 else 7303 else
7276 mips_output_64bit_xfer (direction, gparg, fparg); 7304 mips_output_64bit_xfer (direction, gparg, fparg);
7277 7305
7278 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true); 7306 function_arg_info arg (mode, /*named=*/true);
7307 mips_function_arg_advance (pack_cumulative_args (&cum), arg);
7279 } 7308 }
7280 } 7309 }
7281 7310
7282 /* Write a MIPS16 stub for the current function. This stub is used 7311 /* Write a MIPS16 stub for the current function. This stub is used
7283 for functions which take arguments in the floating-point registers. 7312 for functions which take arguments in the floating-point registers.
7903 enum by_pieces_operation op, 7932 enum by_pieces_operation op,
7904 bool speed_p) 7933 bool speed_p)
7905 { 7934 {
7906 if (op == STORE_BY_PIECES) 7935 if (op == STORE_BY_PIECES)
7907 return mips_store_by_pieces_p (size, align); 7936 return mips_store_by_pieces_p (size, align);
7908 if (op == MOVE_BY_PIECES && HAVE_movmemsi) 7937 if (op == MOVE_BY_PIECES && HAVE_cpymemsi)
7909 { 7938 {
7910 /* movmemsi is meant to generate code that is at least as good as 7939 /* cpymemsi is meant to generate code that is at least as good as
7911 move_by_pieces. However, movmemsi effectively uses a by-pieces 7940 move_by_pieces. However, cpymemsi effectively uses a by-pieces
7912 implementation both for moves smaller than a word and for 7941 implementation both for moves smaller than a word and for
7913 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT 7942 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7914 bytes. We should allow the tree-level optimisers to do such 7943 bytes. We should allow the tree-level optimisers to do such
7915 moves by pieces, as it often exposes other optimization 7944 moves by pieces, as it often exposes other optimization
7916 opportunities. We might as well continue to use movmemsi at 7945 opportunities. We might as well continue to use cpymemsi at
7917 the rtl level though, as it produces better code when 7946 the rtl level though, as it produces better code when
7918 scheduling is disabled (such as at -O). */ 7947 scheduling is disabled (such as at -O). */
7919 if (currently_expanding_to_rtl) 7948 if (currently_expanding_to_rtl)
7920 return false; 7949 return false;
7921 if (align < BITS_PER_WORD) 7950 if (align < BITS_PER_WORD)
8056 if (offset < length) 8085 if (offset < length)
8057 { 8086 {
8058 src = adjust_address (src, BLKmode, offset); 8087 src = adjust_address (src, BLKmode, offset);
8059 dest = adjust_address (dest, BLKmode, offset); 8088 dest = adjust_address (dest, BLKmode, offset);
8060 move_by_pieces (dest, src, length - offset, 8089 move_by_pieces (dest, src, length - offset,
8061 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0); 8090 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), RETURN_BEGIN);
8062 } 8091 }
8063 } 8092 }
8064 8093
8065 /* Helper function for doing a loop-based block operation on memory 8094 /* Helper function for doing a loop-based block operation on memory
8066 reference MEM. Each iteration of the loop will operate on LENGTH 8095 reference MEM. Each iteration of the loop will operate on LENGTH
8130 else 8159 else
8131 /* Temporary fix for PR79150. */ 8160 /* Temporary fix for PR79150. */
8132 emit_insn (gen_nop ()); 8161 emit_insn (gen_nop ());
8133 } 8162 }
8134 8163
8135 /* Expand a movmemsi instruction, which copies LENGTH bytes from 8164 /* Expand a cpymemsi instruction, which copies LENGTH bytes from
8136 memory reference SRC to memory reference DEST. */ 8165 memory reference SRC to memory reference DEST. */
8137 8166
8138 bool 8167 bool
8139 mips_expand_block_move (rtx dest, rtx src, rtx length) 8168 mips_expand_block_move (rtx dest, rtx src, rtx length)
8140 { 8169 {
9553 static machine_mode 9582 static machine_mode
9554 mips_dwarf_frame_reg_mode (int regno) 9583 mips_dwarf_frame_reg_mode (int regno)
9555 { 9584 {
9556 machine_mode mode = default_dwarf_frame_reg_mode (regno); 9585 machine_mode mode = default_dwarf_frame_reg_mode (regno);
9557 9586
9558 if (FP_REG_P (regno) && mips_abi == ABI_32 && TARGET_FLOAT64) 9587 if (FP_REG_P (regno) && mips_abi == ABI_32 && !TARGET_FLOAT32)
9559 mode = SImode; 9588 mode = SImode;
9560 9589
9561 return mode; 9590 return mode;
9562 } 9591 }
9563 9592
9744 void 9773 void
9745 mips_declare_object_name (FILE *stream, const char *name, 9774 mips_declare_object_name (FILE *stream, const char *name,
9746 tree decl ATTRIBUTE_UNUSED) 9775 tree decl ATTRIBUTE_UNUSED)
9747 { 9776 {
9748 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE 9777 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
9749 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); 9778 #ifdef USE_GNU_UNIQUE_OBJECT
9779 /* As in elfos.h. */
9780 if (USE_GNU_UNIQUE_OBJECT && DECL_ONE_ONLY (decl)
9781 && (!DECL_ARTIFICIAL (decl) || !TREE_READONLY (decl)))
9782 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "gnu_unique_object");
9783 else
9784 #endif
9785 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
9750 #endif 9786 #endif
9751 9787
9752 size_directive_output = 0; 9788 size_directive_output = 0;
9753 if (!flag_inhibit_size_directive && DECL_SIZE (decl)) 9789 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
9754 { 9790 {
10606 /* If the global pointer is call-saved, try to use a call-clobbered 10642 /* If the global pointer is call-saved, try to use a call-clobbered
10607 alternative. */ 10643 alternative. */
10608 if (TARGET_CALL_SAVED_GP && crtl->is_leaf) 10644 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
10609 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 10645 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
10610 if (!df_regs_ever_live_p (regno) 10646 if (!df_regs_ever_live_p (regno)
10611 && call_really_used_regs[regno] 10647 && call_used_regs[regno]
10612 && !fixed_regs[regno] 10648 && !fixed_regs[regno]
10613 && regno != PIC_FUNCTION_ADDR_REGNUM) 10649 && regno != PIC_FUNCTION_ADDR_REGNUM)
10614 return regno; 10650 return regno;
10615 10651
10616 return GLOBAL_POINTER_REGNUM; 10652 return GLOBAL_POINTER_REGNUM;
10759 if (regno == STACK_POINTER_REGNUM) 10795 if (regno == STACK_POINTER_REGNUM)
10760 return false; 10796 return false;
10761 10797
10762 /* Otherwise, return true for registers that aren't ordinarily 10798 /* Otherwise, return true for registers that aren't ordinarily
10763 call-clobbered. */ 10799 call-clobbered. */
10764 return call_really_used_regs[regno]; 10800 return call_used_regs[regno];
10765 } 10801 }
10766 10802
10767 return false; 10803 return false;
10768 } 10804 }
10769 10805
10782 if (cfun->machine->interrupt_handler_p 10818 if (cfun->machine->interrupt_handler_p
10783 && mips_interrupt_extra_call_saved_reg_p (regno)) 10819 && mips_interrupt_extra_call_saved_reg_p (regno))
10784 return true; 10820 return true;
10785 10821
10786 /* call_insns preserve $28 unless they explicitly say otherwise, 10822 /* call_insns preserve $28 unless they explicitly say otherwise,
10787 so call_really_used_regs[] treats $28 as call-saved. However, 10823 so call_used_regs[] treats $28 as call-saved. However,
10788 we want the ABI property rather than the default call_insn 10824 we want the ABI property rather than the default call_insn
10789 property here. */ 10825 property here. */
10790 return (regno == GLOBAL_POINTER_REGNUM 10826 return (regno == GLOBAL_POINTER_REGNUM
10791 ? TARGET_CALL_SAVED_GP 10827 ? TARGET_CALL_SAVED_GP
10792 : !call_really_used_regs[regno]); 10828 : !call_used_regs[regno]);
10793 } 10829 }
10794 10830
10795 /* Return true if the function body might clobber register REGNO. 10831 /* Return true if the function body might clobber register REGNO.
10796 We know that REGNO is call-saved. */ 10832 We know that REGNO is call-saved. */
10797 10833
11943 11979
11944 static void 11980 static void
11945 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size) 11981 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
11946 { 11982 {
11947 if (TARGET_MIPS16) 11983 if (TARGET_MIPS16)
11948 sorry ("-fstack-check=specific not implemented for MIPS16"); 11984 sorry ("%<-fstack-check=specific%> not implemented for MIPS16");
11949 11985
11950 /* See if we have a constant small number of probes to generate. If so, 11986 /* See if we have a constant small number of probes to generate. If so,
11951 that's the easy case. */ 11987 that's the easy case. */
11952 if (first + size <= 32768) 11988 if (first + size <= 32768)
11953 { 11989 {
12795 CCFmode because CCFmode double-precision compares will write a 12831 CCFmode because CCFmode double-precision compares will write a
12796 64-bit value to a register. */ 12832 64-bit value to a register. */
12797 if (mode == CCFmode) 12833 if (mode == CCFmode)
12798 return !(TARGET_FLOATXX && (regno & 1) != 0); 12834 return !(TARGET_FLOATXX && (regno & 1) != 0);
12799 12835
12800 /* Allow 64-bit vector modes for Loongson-2E/2F. */ 12836 /* Allow 64-bit vector modes for Loongson MultiMedia extensions
12801 if (TARGET_LOONGSON_VECTORS 12837 Instructions (MMI). */
12838 if (TARGET_LOONGSON_MMI
12802 && (mode == V2SImode 12839 && (mode == V2SImode
12803 || mode == V4HImode 12840 || mode == V4HImode
12804 || mode == V8QImode 12841 || mode == V8QImode
12805 || mode == DImode)) 12842 || mode == DImode))
12806 return true; 12843 return true;
12897 single-precision registers are not considered callee-saved for o32 12934 single-precision registers are not considered callee-saved for o32
12898 FPXX as they will be clobbered when run on an FR=1 FPU. MSA vector 12935 FPXX as they will be clobbered when run on an FR=1 FPU. MSA vector
12899 registers with MODE > 64 bits are part clobbered too. */ 12936 registers with MODE > 64 bits are part clobbered too. */
12900 12937
12901 static bool 12938 static bool
12902 mips_hard_regno_call_part_clobbered (unsigned int regno, machine_mode mode) 12939 mips_hard_regno_call_part_clobbered (unsigned int, unsigned int regno,
12940 machine_mode mode)
12903 { 12941 {
12904 if (TARGET_FLOATXX 12942 if (TARGET_FLOATXX
12905 && hard_regno_nregs (regno, mode) == 1 12943 && hard_regno_nregs (regno, mode) == 1
12906 && FP_REG_P (regno) 12944 && FP_REG_P (regno)
12907 && (regno & 1) != 0) 12945 && (regno & 1) != 0)
12943 { 12981 {
12944 int size; 12982 int size;
12945 HARD_REG_SET left; 12983 HARD_REG_SET left;
12946 12984
12947 size = 0x8000; 12985 size = 0x8000;
12948 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]); 12986 left = reg_class_contents[rclass];
12949 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS])) 12987 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
12950 { 12988 {
12951 if (mips_hard_regno_mode_ok (ST_REG_FIRST, mode)) 12989 if (mips_hard_regno_mode_ok (ST_REG_FIRST, mode))
12952 size = MIN (size, 4); 12990 size = MIN (size, 4);
12953 12991
12954 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]); 12992 left &= ~reg_class_contents[ST_REGS];
12955 } 12993 }
12956 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS])) 12994 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
12957 { 12995 {
12958 if (mips_hard_regno_mode_ok (FP_REG_FIRST, mode)) 12996 if (mips_hard_regno_mode_ok (FP_REG_FIRST, mode))
12959 { 12997 {
12961 size = MIN (size, UNITS_PER_MSA_REG); 12999 size = MIN (size, UNITS_PER_MSA_REG);
12962 else 13000 else
12963 size = MIN (size, UNITS_PER_FPREG); 13001 size = MIN (size, UNITS_PER_FPREG);
12964 } 13002 }
12965 13003
12966 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]); 13004 left &= ~reg_class_contents[FP_REGS];
12967 } 13005 }
12968 if (!hard_reg_set_empty_p (left)) 13006 if (!hard_reg_set_empty_p (left))
12969 size = MIN (size, UNITS_PER_WORD); 13007 size = MIN (size, UNITS_PER_WORD);
12970 return (GET_MODE_SIZE (mode) + size - 1) / size; 13008 return (GET_MODE_SIZE (mode) + size - 1) / size;
12971 } 13009 }
13366 return TARGET_DSP; 13404 return TARGET_DSP;
13367 13405
13368 case E_V2SImode: 13406 case E_V2SImode:
13369 case E_V4HImode: 13407 case E_V4HImode:
13370 case E_V8QImode: 13408 case E_V8QImode:
13371 return TARGET_LOONGSON_VECTORS; 13409 return TARGET_LOONGSON_MMI;
13372 13410
13373 default: 13411 default:
13374 return MSA_SUPPORTED_MODE_P (mode); 13412 return MSA_SUPPORTED_MODE_P (mode);
13375 } 13413 }
13376 } 13414 }
13420 break; 13458 break;
13421 } 13459 }
13422 return word_mode; 13460 return word_mode;
13423 } 13461 }
13424 13462
13425 /* Implement TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES. */ 13463 /* Implement TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES. */
13426 13464
13427 static void 13465 static unsigned int
13428 mips_autovectorize_vector_sizes (vector_sizes *sizes) 13466 mips_autovectorize_vector_modes (vector_modes *modes, bool)
13429 { 13467 {
13430 if (ISA_HAS_MSA) 13468 if (ISA_HAS_MSA)
13431 sizes->safe_push (16); 13469 modes->safe_push (V16QImode);
13470 return 0;
13432 } 13471 }
13433 13472
13434 /* Implement TARGET_INIT_LIBFUNCS. */ 13473 /* Implement TARGET_INIT_LIBFUNCS. */
13435 13474
13436 static void 13475 static void
14599 case PROCESSOR_R9000: 14638 case PROCESSOR_R9000:
14600 case PROCESSOR_OCTEON: 14639 case PROCESSOR_OCTEON:
14601 case PROCESSOR_OCTEON2: 14640 case PROCESSOR_OCTEON2:
14602 case PROCESSOR_OCTEON3: 14641 case PROCESSOR_OCTEON3:
14603 case PROCESSOR_I6400: 14642 case PROCESSOR_I6400:
14643 case PROCESSOR_GS264E:
14604 return 2; 14644 return 2;
14605 14645
14606 case PROCESSOR_SB1: 14646 case PROCESSOR_SB1:
14607 case PROCESSOR_SB1A: 14647 case PROCESSOR_SB1A:
14608 /* This is actually 4, but we get better performance if we claim 3. 14648 /* This is actually 4, but we get better performance if we claim 3.
14611 reach the theoretical max of 4. */ 14651 reach the theoretical max of 4. */
14612 return 3; 14652 return 3;
14613 14653
14614 case PROCESSOR_LOONGSON_2E: 14654 case PROCESSOR_LOONGSON_2E:
14615 case PROCESSOR_LOONGSON_2F: 14655 case PROCESSOR_LOONGSON_2F:
14616 case PROCESSOR_LOONGSON_3A: 14656 case PROCESSOR_GS464:
14657 case PROCESSOR_GS464E:
14617 case PROCESSOR_P5600: 14658 case PROCESSOR_P5600:
14618 case PROCESSOR_P6600: 14659 case PROCESSOR_P6600:
14619 return 4; 14660 return 4;
14620 14661
14621 case PROCESSOR_XLP: 14662 case PROCESSOR_XLP:
14743 { 14784 {
14744 /* Can schedule up to 4 of the 6 function units in any one cycle. */ 14785 /* Can schedule up to 4 of the 6 function units in any one cycle. */
14745 if (TUNE_SB1) 14786 if (TUNE_SB1)
14746 return 4; 14787 return 4;
14747 14788
14748 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A) 14789 if (TUNE_LOONGSON_2EF || TUNE_GS464 || TUNE_GS464E)
14749 return 4; 14790 return 4;
14750 14791
14751 if (TUNE_OCTEON) 14792 if (TUNE_OCTEON || TUNE_GS264E)
14752 return 2; 14793 return 2;
14753 14794
14754 if (TUNE_P5600 || TUNE_P6600 || TUNE_I6400) 14795 if (TUNE_P5600 || TUNE_P6600 || TUNE_I6400)
14755 return 4; 14796 return 4;
14756 14797
14855 and INSN. */ 14896 and INSN. */
14856 14897
14857 static bool 14898 static bool
14858 vr4130_true_reg_dependence_p (rtx insn) 14899 vr4130_true_reg_dependence_p (rtx insn)
14859 { 14900 {
14860 note_stores (PATTERN (vr4130_last_insn), 14901 note_stores (vr4130_last_insn, vr4130_true_reg_dependence_p_1, &insn);
14861 vr4130_true_reg_dependence_p_1, &insn);
14862 return insn == 0; 14902 return insn == 0;
14863 } 14903 }
14864 14904
14865 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of 14905 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
14866 the ready queue and that INSN2 is the instruction after it, return 14906 the ready queue and that INSN2 is the instruction after it, return
15139 return write; 15179 return write;
15140 15180
15141 /* store_retained / load_retained. */ 15181 /* store_retained / load_retained. */
15142 return GEN_INT (INTVAL (write) + 6); 15182 return GEN_INT (INTVAL (write) + 6);
15143 } 15183 }
15184
15185 /* Loongson EXT2 only implements pref hint=0 (prefetch for load) and hint=1
15186 (prefetch for store), other hint just scale to hint = 0 and hint = 1. */
15187
15188 rtx
15189 mips_loongson_ext2_prefetch_cookie (rtx write, rtx)
15190 {
15191 /* store. */
15192 if (INTVAL (write) == 1)
15193 return GEN_INT (INTVAL (write));
15194
15195 /* load. */
15196 if (INTVAL (write) == 0)
15197 return GEN_INT (INTVAL (write));
15198
15199 gcc_unreachable ();
15200 }
15201
15144 15202
15145 /* Flags that indicate when a built-in function is available. 15203 /* Flags that indicate when a built-in function is available.
15146 15204
15147 BUILTIN_AVAIL_NON_MIPS16 15205 BUILTIN_AVAIL_NON_MIPS16
15148 The function is available on the current target if !TARGET_MIPS16. 15206 The function is available on the current target if !TARGET_MIPS16.
15190 /* The function's prototype. */ 15248 /* The function's prototype. */
15191 enum mips_function_type function_type; 15249 enum mips_function_type function_type;
15192 15250
15193 /* Whether the function is available. */ 15251 /* Whether the function is available. */
15194 unsigned int (*avail) (void); 15252 unsigned int (*avail) (void);
15253
15254 /* Whether the function is pure. */
15255 bool is_pure;
15195 }; 15256 };
15196 15257
15197 AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI) 15258 AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI)
15198 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT) 15259 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
15199 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT) 15260 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
15201 AVAIL_NON_MIPS16 (dsp, TARGET_DSP) 15262 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
15202 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2) 15263 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
15203 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP) 15264 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
15204 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP) 15265 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
15205 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2) 15266 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
15206 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS) 15267 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_MMI)
15207 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) 15268 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
15208 AVAIL_NON_MIPS16 (msa, TARGET_MSA) 15269 AVAIL_NON_MIPS16 (msa, TARGET_MSA)
15209 15270
15210 /* Construct a mips_builtin_description from the given arguments. 15271 /* Construct a mips_builtin_description from the given arguments.
15211 15272
15221 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields. 15282 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
15222 15283
15223 AVAIL is the name of the availability predicate, without the leading 15284 AVAIL is the name of the availability predicate, without the leading
15224 mips_builtin_avail_. */ 15285 mips_builtin_avail_. */
15225 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \ 15286 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
15226 FUNCTION_TYPE, AVAIL) \ 15287 FUNCTION_TYPE, AVAIL, PURE) \
15227 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \ 15288 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
15228 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \ 15289 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
15229 mips_builtin_avail_ ## AVAIL } 15290 mips_builtin_avail_ ## AVAIL, PURE }
15230 15291
15231 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function 15292 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
15232 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL 15293 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
15233 are as for MIPS_BUILTIN. */ 15294 are as for MIPS_BUILTIN. */
15234 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ 15295 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
15235 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL) 15296 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, \
15297 AVAIL, false)
15298
15299 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT pure function
15300 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
15301 are as for MIPS_BUILTIN. */
15302 #define DIRECT_BUILTIN_PURE(INSN, FUNCTION_TYPE, AVAIL) \
15303 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, \
15304 AVAIL, true)
15236 15305
15237 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which 15306 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
15238 are subject to mips_builtin_avail_<AVAIL>. */ 15307 are subject to mips_builtin_avail_<AVAIL>. */
15239 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \ 15308 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
15240 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \ 15309 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
15241 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \ 15310 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL, \
15311 false), \
15242 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \ 15312 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
15243 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL) 15313 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL, false)
15244 15314
15245 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps. 15315 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
15246 The lower and upper forms are subject to mips_builtin_avail_<AVAIL> 15316 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
15247 while the any and all forms are subject to mips_builtin_avail_mips3d. */ 15317 while the any and all forms are subject to mips_builtin_avail_mips3d. */
15248 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \ 15318 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
15249 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \ 15319 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
15250 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \ 15320 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
15251 mips3d), \ 15321 mips3d, false), \
15252 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \ 15322 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
15253 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \ 15323 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
15254 mips3d), \ 15324 mips3d, false), \
15255 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \ 15325 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
15256 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \ 15326 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
15257 AVAIL), \ 15327 AVAIL, false), \
15258 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \ 15328 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
15259 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \ 15329 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
15260 AVAIL) 15330 AVAIL, false)
15261 15331
15262 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions 15332 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
15263 are subject to mips_builtin_avail_mips3d. */ 15333 are subject to mips_builtin_avail_mips3d. */
15264 #define CMP_4S_BUILTINS(INSN, COND) \ 15334 #define CMP_4S_BUILTINS(INSN, COND) \
15265 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \ 15335 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
15266 MIPS_BUILTIN_CMP_ANY, \ 15336 MIPS_BUILTIN_CMP_ANY, \
15267 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \ 15337 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d, false), \
15268 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \ 15338 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
15269 MIPS_BUILTIN_CMP_ALL, \ 15339 MIPS_BUILTIN_CMP_ALL, \
15270 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d) 15340 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d, false)
15271 15341
15272 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison 15342 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
15273 instruction requires mips_builtin_avail_<AVAIL>. */ 15343 instruction requires mips_builtin_avail_<AVAIL>. */
15274 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \ 15344 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
15275 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \ 15345 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
15276 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ 15346 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
15277 AVAIL), \ 15347 AVAIL, false), \
15278 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \ 15348 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
15279 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ 15349 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
15280 AVAIL) 15350 AVAIL, false)
15281 15351
15282 /* Define all the built-in functions related to C.cond.fmt condition COND. */ 15352 /* Define all the built-in functions related to C.cond.fmt condition COND. */
15283 #define CMP_BUILTINS(COND) \ 15353 #define CMP_BUILTINS(COND) \
15284 MOVTF_BUILTINS (c, COND, paired_single), \ 15354 MOVTF_BUILTINS (c, COND, paired_single), \
15285 MOVTF_BUILTINS (cabs, COND, mips3d), \ 15355 MOVTF_BUILTINS (cabs, COND, mips3d), \
15292 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET 15362 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
15293 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE 15363 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
15294 and AVAIL are as for MIPS_BUILTIN. */ 15364 and AVAIL are as for MIPS_BUILTIN. */
15295 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ 15365 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
15296 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \ 15366 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
15297 FUNCTION_TYPE, AVAIL) 15367 FUNCTION_TYPE, AVAIL, false)
15298 15368
15299 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP 15369 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
15300 branch instruction. AVAIL is as for MIPS_BUILTIN. */ 15370 branch instruction. AVAIL is as for MIPS_BUILTIN. */
15301 #define BPOSGE_BUILTIN(VALUE, AVAIL) \ 15371 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
15302 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \ 15372 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
15303 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL) 15373 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL, false)
15304 15374
15305 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME> 15375 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
15306 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a 15376 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
15307 builtin_description field. */ 15377 builtin_description field. */
15308 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \ 15378 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
15309 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \ 15379 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
15310 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \ 15380 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
15311 FUNCTION_TYPE, mips_builtin_avail_loongson } 15381 FUNCTION_TYPE, mips_builtin_avail_loongson, false }
15312 15382
15313 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN> 15383 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
15314 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a 15384 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
15315 builtin_description field. */ 15385 builtin_description field. */
15316 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \ 15386 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
15320 We use functions of this form when the same insn can be usefully applied 15390 We use functions of this form when the same insn can be usefully applied
15321 to more than one datatype. */ 15391 to more than one datatype. */
15322 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \ 15392 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
15323 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE) 15393 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
15324 15394
15325 /* Define an MSA MIPS_BUILTIN_DIRECT function __builtin_msa_<INSN> 15395 /* Define an MSA MIPS_BUILTIN_DIRECT pure function __builtin_msa_<INSN>
15396 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15397 field. */
15398 #define MSA_BUILTIN_PURE(INSN, FUNCTION_TYPE) \
15399 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15400 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \
15401 FUNCTION_TYPE, mips_builtin_avail_msa, true }
15402
15403 /* Define an MSA MIPS_BUILTIN_DIRECT non-pure function __builtin_msa_<INSN>
15326 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description 15404 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15327 field. */ 15405 field. */
15328 #define MSA_BUILTIN(INSN, FUNCTION_TYPE) \ 15406 #define MSA_BUILTIN(INSN, FUNCTION_TYPE) \
15329 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \ 15407 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15330 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \ 15408 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \
15331 FUNCTION_TYPE, mips_builtin_avail_msa } 15409 FUNCTION_TYPE, mips_builtin_avail_msa, false }
15332 15410
15333 /* Define a remapped MSA MIPS_BUILTIN_DIRECT function __builtin_msa_<INSN> 15411 /* Define a remapped MSA MIPS_BUILTIN_DIRECT function __builtin_msa_<INSN>
15334 for instruction CODE_FOR_msa_<INSN2>. FUNCTION_TYPE is 15412 for instruction CODE_FOR_msa_<INSN2>. FUNCTION_TYPE is
15335 a builtin_description field. */ 15413 a builtin_description field. */
15336 #define MSA_BUILTIN_REMAP(INSN, INSN2, FUNCTION_TYPE) \ 15414 #define MSA_BUILTIN_REMAP(INSN, INSN2, FUNCTION_TYPE) \
15337 { CODE_FOR_msa_ ## INSN2, MIPS_FP_COND_f, \ 15415 { CODE_FOR_msa_ ## INSN2, MIPS_FP_COND_f, \
15338 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \ 15416 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT, \
15339 FUNCTION_TYPE, mips_builtin_avail_msa } 15417 FUNCTION_TYPE, mips_builtin_avail_msa, false }
15340 15418
15341 /* Define an MSA MIPS_BUILTIN_MSA_TEST_BRANCH function __builtin_msa_<INSN> 15419 /* Define an MSA MIPS_BUILTIN_MSA_TEST_BRANCH function __builtin_msa_<INSN>
15342 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description 15420 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15343 field. */ 15421 field. */
15344 #define MSA_BUILTIN_TEST_BRANCH(INSN, FUNCTION_TYPE) \ 15422 #define MSA_BUILTIN_TEST_BRANCH(INSN, FUNCTION_TYPE) \
15345 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \ 15423 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15346 "__builtin_msa_" #INSN, MIPS_BUILTIN_MSA_TEST_BRANCH, \ 15424 "__builtin_msa_" #INSN, MIPS_BUILTIN_MSA_TEST_BRANCH, \
15347 FUNCTION_TYPE, mips_builtin_avail_msa } 15425 FUNCTION_TYPE, mips_builtin_avail_msa, false }
15348 15426
15349 /* Define an MSA MIPS_BUILTIN_DIRECT_NO_TARGET function __builtin_msa_<INSN> 15427 /* Define an MSA MIPS_BUILTIN_DIRECT_NO_TARGET function __builtin_msa_<INSN>
15350 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description 15428 for instruction CODE_FOR_msa_<INSN>. FUNCTION_TYPE is a builtin_description
15351 field. */ 15429 field. */
15352 #define MSA_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE) \ 15430 #define MSA_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE) \
15353 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \ 15431 { CODE_FOR_msa_ ## INSN, MIPS_FP_COND_f, \
15354 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \ 15432 "__builtin_msa_" #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
15355 FUNCTION_TYPE, mips_builtin_avail_msa } 15433 FUNCTION_TYPE, mips_builtin_avail_msa, false }
15356 15434
15357 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2 15435 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
15358 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3 15436 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
15359 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3 15437 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
15360 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3 15438 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
15595 #define MIPS_GET_FCSR 0 15673 #define MIPS_GET_FCSR 0
15596 DIRECT_BUILTIN (get_fcsr, MIPS_USI_FTYPE_VOID, hard_float), 15674 DIRECT_BUILTIN (get_fcsr, MIPS_USI_FTYPE_VOID, hard_float),
15597 #define MIPS_SET_FCSR 1 15675 #define MIPS_SET_FCSR 1
15598 DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float), 15676 DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float),
15599 15677
15600 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), 15678 DIRECT_BUILTIN_PURE (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
15601 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), 15679 DIRECT_BUILTIN_PURE (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
15602 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), 15680 DIRECT_BUILTIN_PURE (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
15603 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), 15681 DIRECT_BUILTIN_PURE (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
15604 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single), 15682 DIRECT_BUILTIN_PURE (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
15605 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single), 15683 DIRECT_BUILTIN_PURE (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
15606 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single), 15684 DIRECT_BUILTIN_PURE (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
15607 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single), 15685 DIRECT_BUILTIN_PURE (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
15608 15686
15609 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single), 15687 DIRECT_BUILTIN_PURE (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
15610 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), 15688 DIRECT_BUILTIN_PURE (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
15611 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), 15689 DIRECT_BUILTIN_PURE (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
15612 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), 15690 DIRECT_BUILTIN_PURE (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
15613 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d), 15691 DIRECT_BUILTIN_PURE (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
15614 15692
15615 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d), 15693 DIRECT_BUILTIN_PURE (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
15616 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d), 15694 DIRECT_BUILTIN_PURE (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
15617 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), 15695 DIRECT_BUILTIN_PURE (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
15618 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d), 15696 DIRECT_BUILTIN_PURE (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
15619 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d), 15697 DIRECT_BUILTIN_PURE (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
15620 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), 15698 DIRECT_BUILTIN_PURE (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
15621 15699
15622 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d), 15700 DIRECT_BUILTIN_PURE (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
15623 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d), 15701 DIRECT_BUILTIN_PURE (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
15624 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), 15702 DIRECT_BUILTIN_PURE (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
15625 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d), 15703 DIRECT_BUILTIN_PURE (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
15626 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d), 15704 DIRECT_BUILTIN_PURE (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
15627 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), 15705 DIRECT_BUILTIN_PURE (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
15628 15706
15629 MIPS_FP_CONDITIONS (CMP_BUILTINS), 15707 MIPS_FP_CONDITIONS (CMP_BUILTINS),
15630 15708
15631 /* Built-in functions for the SB-1 processor. */ 15709 /* Built-in functions for the SB-1 processor. */
15632 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single), 15710 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
15633 15711
15634 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */ 15712 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
15635 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 15713 DIRECT_BUILTIN_PURE (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15636 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 15714 DIRECT_BUILTIN_PURE (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15637 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp), 15715 DIRECT_BUILTIN_PURE (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
15638 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), 15716 DIRECT_BUILTIN_PURE (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
15639 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), 15717 DIRECT_BUILTIN_PURE (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
15640 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 15718 DIRECT_BUILTIN_PURE (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15641 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 15719 DIRECT_BUILTIN_PURE (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15642 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp), 15720 DIRECT_BUILTIN_PURE (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
15643 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), 15721 DIRECT_BUILTIN_PURE (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
15644 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), 15722 DIRECT_BUILTIN_PURE (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
15645 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp), 15723 DIRECT_BUILTIN_PURE (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
15646 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp), 15724 DIRECT_BUILTIN_PURE (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
15647 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp), 15725 DIRECT_BUILTIN_PURE (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
15648 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp), 15726 DIRECT_BUILTIN_PURE (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
15649 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp), 15727 DIRECT_BUILTIN_PURE (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
15650 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp), 15728 DIRECT_BUILTIN_PURE (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
15651 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp), 15729 DIRECT_BUILTIN_PURE (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
15652 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp), 15730 DIRECT_BUILTIN_PURE (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
15653 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp), 15731 DIRECT_BUILTIN_PURE (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
15654 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp), 15732 DIRECT_BUILTIN_PURE (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
15655 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp), 15733 DIRECT_BUILTIN_PURE (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
15656 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp), 15734 DIRECT_BUILTIN_PURE (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
15657 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp), 15735 DIRECT_BUILTIN_PURE (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
15658 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp), 15736 DIRECT_BUILTIN_PURE (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
15659 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp), 15737 DIRECT_BUILTIN_PURE (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
15660 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp), 15738 DIRECT_BUILTIN_PURE (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
15661 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp), 15739 DIRECT_BUILTIN_PURE (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
15662 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp), 15740 DIRECT_BUILTIN_PURE (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
15663 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp), 15741 DIRECT_BUILTIN_PURE (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
15664 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp), 15742 DIRECT_BUILTIN_PURE (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
15665 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp), 15743 DIRECT_BUILTIN_PURE (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
15666 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), 15744 DIRECT_BUILTIN_PURE (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
15667 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), 15745 DIRECT_BUILTIN_PURE (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
15668 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp), 15746 DIRECT_BUILTIN_PURE (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
15669 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp), 15747 DIRECT_BUILTIN_PURE (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
15670 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), 15748 DIRECT_BUILTIN_PURE (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
15671 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), 15749 DIRECT_BUILTIN_PURE (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
15672 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp), 15750 DIRECT_BUILTIN_PURE (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
15673 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp), 15751 DIRECT_BUILTIN_PURE (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
15674 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp), 15752 DIRECT_BUILTIN_PURE (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
15675 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 15753 DIRECT_BUILTIN_PURE (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15676 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp), 15754 DIRECT_BUILTIN_PURE (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
15677 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp), 15755 DIRECT_BUILTIN_PURE (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
15678 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp), 15756 DIRECT_BUILTIN_PURE (bitrev, MIPS_SI_FTYPE_SI, dsp),
15679 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp), 15757 DIRECT_BUILTIN_PURE (insv, MIPS_SI_FTYPE_SI_SI, dsp),
15680 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp), 15758 DIRECT_BUILTIN_PURE (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
15681 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp), 15759 DIRECT_BUILTIN_PURE (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
15682 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), 15760 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
15683 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), 15761 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
15684 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), 15762 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
15685 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), 15763 DIRECT_BUILTIN_PURE (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
15686 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), 15764 DIRECT_BUILTIN_PURE (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
15687 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), 15765 DIRECT_BUILTIN_PURE (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
15688 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), 15766 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
15689 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), 15767 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
15690 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), 15768 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
15691 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), 15769 DIRECT_BUILTIN_PURE (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
15692 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 15770 DIRECT_BUILTIN_PURE (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15693 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), 15771 DIRECT_BUILTIN_PURE (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
15694 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp), 15772 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
15695 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp), 15773 DIRECT_BUILTIN_PURE (rddsp, MIPS_SI_FTYPE_SI, dsp),
15696 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp), 15774 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
15697 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp), 15775 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
15698 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp), 15776 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
15699 BPOSGE_BUILTIN (32, dsp), 15777 BPOSGE_BUILTIN (32, dsp),
15700 15778
15701 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */ 15779 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
15702 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2), 15780 DIRECT_BUILTIN_PURE (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
15703 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 15781 DIRECT_BUILTIN_PURE (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15704 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 15782 DIRECT_BUILTIN_PURE (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15705 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), 15783 DIRECT_BUILTIN_PURE (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
15706 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), 15784 DIRECT_BUILTIN_PURE (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
15707 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2), 15785 DIRECT_BUILTIN_PURE (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
15708 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2), 15786 DIRECT_BUILTIN_PURE (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
15709 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), 15787 DIRECT_BUILTIN_PURE (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
15710 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), 15788 DIRECT_BUILTIN_PURE (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
15711 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), 15789 DIRECT_BUILTIN_PURE (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
15712 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 15790 DIRECT_BUILTIN_PURE (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15713 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 15791 DIRECT_BUILTIN_PURE (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15714 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2), 15792 DIRECT_BUILTIN_PURE (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
15715 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 15793 DIRECT_BUILTIN_PURE (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15716 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2), 15794 DIRECT_BUILTIN_PURE (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
15717 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2), 15795 DIRECT_BUILTIN_PURE (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
15718 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2), 15796 DIRECT_BUILTIN_PURE (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
15719 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2), 15797 DIRECT_BUILTIN_PURE (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
15720 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2), 15798 DIRECT_BUILTIN_PURE (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
15721 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2), 15799 DIRECT_BUILTIN_PURE (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
15722 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2), 15800 DIRECT_BUILTIN_PURE (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
15723 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2), 15801 DIRECT_BUILTIN_PURE (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
15724 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 15802 DIRECT_BUILTIN_PURE (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15725 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 15803 DIRECT_BUILTIN_PURE (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15726 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), 15804 DIRECT_BUILTIN_PURE (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
15727 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), 15805 DIRECT_BUILTIN_PURE (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
15728 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 15806 DIRECT_BUILTIN_PURE (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15729 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 15807 DIRECT_BUILTIN_PURE (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15730 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2), 15808 DIRECT_BUILTIN_PURE (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
15731 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2), 15809 DIRECT_BUILTIN_PURE (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
15732 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 15810 DIRECT_BUILTIN_PURE (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15733 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), 15811 DIRECT_BUILTIN_PURE (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
15734 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2), 15812 DIRECT_BUILTIN_PURE (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
15735 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2), 15813 DIRECT_BUILTIN_PURE (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
15736 15814
15737 /* Built-in functions for the DSP ASE (32-bit only). */ 15815 /* Built-in functions for the DSP ASE (32-bit only). */
15738 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), 15816 DIRECT_BUILTIN_PURE (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
15739 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), 15817 DIRECT_BUILTIN_PURE (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
15740 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), 15818 DIRECT_BUILTIN_PURE (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
15741 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), 15819 DIRECT_BUILTIN_PURE (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
15742 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 15820 DIRECT_BUILTIN_PURE (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15743 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 15821 DIRECT_BUILTIN_PURE (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15744 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 15822 DIRECT_BUILTIN_PURE (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15745 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), 15823 DIRECT_BUILTIN_PURE (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
15746 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), 15824 DIRECT_BUILTIN_PURE (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
15747 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 15825 DIRECT_BUILTIN_PURE (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15748 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 15826 DIRECT_BUILTIN_PURE (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15749 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 15827 DIRECT_BUILTIN_PURE (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15750 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), 15828 DIRECT_BUILTIN_PURE (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
15751 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32), 15829 DIRECT_BUILTIN_PURE (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
15752 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32), 15830 DIRECT_BUILTIN_PURE (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
15753 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32), 15831 DIRECT_BUILTIN_PURE (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
15754 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32), 15832 DIRECT_BUILTIN_PURE (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
15755 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32), 15833 DIRECT_BUILTIN_PURE (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
15756 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32), 15834 DIRECT_BUILTIN_PURE (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
15757 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32), 15835 DIRECT_BUILTIN_PURE (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
15758 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32), 15836 DIRECT_BUILTIN_PURE (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
15759 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), 15837 DIRECT_BUILTIN_PURE (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
15760 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32), 15838 DIRECT_BUILTIN_PURE (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
15761 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), 15839 DIRECT_BUILTIN_PURE (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
15762 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32), 15840 DIRECT_BUILTIN_PURE (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
15763 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32), 15841 DIRECT_BUILTIN_PURE (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
15764 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32), 15842 DIRECT_BUILTIN_PURE (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
15765 15843
15766 /* Built-in functions for the DSP ASE (64-bit only). */ 15844 /* Built-in functions for the DSP ASE (64-bit only). */
15767 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64), 15845 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
15768 15846
15769 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */ 15847 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
15770 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 15848 DIRECT_BUILTIN_PURE (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15771 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 15849 DIRECT_BUILTIN_PURE (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15772 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 15850 DIRECT_BUILTIN_PURE (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15773 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 15851 DIRECT_BUILTIN_PURE (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15774 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 15852 DIRECT_BUILTIN_PURE (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15775 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 15853 DIRECT_BUILTIN_PURE (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15776 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 15854 DIRECT_BUILTIN_PURE (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15777 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 15855 DIRECT_BUILTIN_PURE (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15778 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), 15856 DIRECT_BUILTIN_PURE (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
15779 15857
15780 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */ 15858 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
15781 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI), 15859 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
15782 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI), 15860 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
15783 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI), 15861 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
15880 15958
15881 /* Sundry other built-in functions. */ 15959 /* Sundry other built-in functions. */
15882 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache), 15960 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache),
15883 15961
15884 /* Built-in functions for MSA. */ 15962 /* Built-in functions for MSA. */
15885 MSA_BUILTIN (sll_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 15963 MSA_BUILTIN_PURE (sll_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15886 MSA_BUILTIN (sll_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 15964 MSA_BUILTIN_PURE (sll_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15887 MSA_BUILTIN (sll_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 15965 MSA_BUILTIN_PURE (sll_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15888 MSA_BUILTIN (sll_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 15966 MSA_BUILTIN_PURE (sll_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15889 MSA_BUILTIN (slli_b, MIPS_V16QI_FTYPE_V16QI_UQI), 15967 MSA_BUILTIN_PURE (slli_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15890 MSA_BUILTIN (slli_h, MIPS_V8HI_FTYPE_V8HI_UQI), 15968 MSA_BUILTIN_PURE (slli_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15891 MSA_BUILTIN (slli_w, MIPS_V4SI_FTYPE_V4SI_UQI), 15969 MSA_BUILTIN_PURE (slli_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15892 MSA_BUILTIN (slli_d, MIPS_V2DI_FTYPE_V2DI_UQI), 15970 MSA_BUILTIN_PURE (slli_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15893 MSA_BUILTIN (sra_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 15971 MSA_BUILTIN_PURE (sra_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15894 MSA_BUILTIN (sra_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 15972 MSA_BUILTIN_PURE (sra_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15895 MSA_BUILTIN (sra_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 15973 MSA_BUILTIN_PURE (sra_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15896 MSA_BUILTIN (sra_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 15974 MSA_BUILTIN_PURE (sra_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15897 MSA_BUILTIN (srai_b, MIPS_V16QI_FTYPE_V16QI_UQI), 15975 MSA_BUILTIN_PURE (srai_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15898 MSA_BUILTIN (srai_h, MIPS_V8HI_FTYPE_V8HI_UQI), 15976 MSA_BUILTIN_PURE (srai_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15899 MSA_BUILTIN (srai_w, MIPS_V4SI_FTYPE_V4SI_UQI), 15977 MSA_BUILTIN_PURE (srai_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15900 MSA_BUILTIN (srai_d, MIPS_V2DI_FTYPE_V2DI_UQI), 15978 MSA_BUILTIN_PURE (srai_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15901 MSA_BUILTIN (srar_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 15979 MSA_BUILTIN_PURE (srar_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15902 MSA_BUILTIN (srar_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 15980 MSA_BUILTIN_PURE (srar_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15903 MSA_BUILTIN (srar_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 15981 MSA_BUILTIN_PURE (srar_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15904 MSA_BUILTIN (srar_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 15982 MSA_BUILTIN_PURE (srar_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15905 MSA_BUILTIN (srari_b, MIPS_V16QI_FTYPE_V16QI_UQI), 15983 MSA_BUILTIN_PURE (srari_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15906 MSA_BUILTIN (srari_h, MIPS_V8HI_FTYPE_V8HI_UQI), 15984 MSA_BUILTIN_PURE (srari_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15907 MSA_BUILTIN (srari_w, MIPS_V4SI_FTYPE_V4SI_UQI), 15985 MSA_BUILTIN_PURE (srari_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15908 MSA_BUILTIN (srari_d, MIPS_V2DI_FTYPE_V2DI_UQI), 15986 MSA_BUILTIN_PURE (srari_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15909 MSA_BUILTIN (srl_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 15987 MSA_BUILTIN_PURE (srl_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15910 MSA_BUILTIN (srl_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 15988 MSA_BUILTIN_PURE (srl_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15911 MSA_BUILTIN (srl_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 15989 MSA_BUILTIN_PURE (srl_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15912 MSA_BUILTIN (srl_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 15990 MSA_BUILTIN_PURE (srl_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15913 MSA_BUILTIN (srli_b, MIPS_V16QI_FTYPE_V16QI_UQI), 15991 MSA_BUILTIN_PURE (srli_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15914 MSA_BUILTIN (srli_h, MIPS_V8HI_FTYPE_V8HI_UQI), 15992 MSA_BUILTIN_PURE (srli_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15915 MSA_BUILTIN (srli_w, MIPS_V4SI_FTYPE_V4SI_UQI), 15993 MSA_BUILTIN_PURE (srli_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15916 MSA_BUILTIN (srli_d, MIPS_V2DI_FTYPE_V2DI_UQI), 15994 MSA_BUILTIN_PURE (srli_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15917 MSA_BUILTIN (srlr_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 15995 MSA_BUILTIN_PURE (srlr_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15918 MSA_BUILTIN (srlr_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 15996 MSA_BUILTIN_PURE (srlr_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15919 MSA_BUILTIN (srlr_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 15997 MSA_BUILTIN_PURE (srlr_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15920 MSA_BUILTIN (srlr_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 15998 MSA_BUILTIN_PURE (srlr_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15921 MSA_BUILTIN (srlri_b, MIPS_V16QI_FTYPE_V16QI_UQI), 15999 MSA_BUILTIN_PURE (srlri_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15922 MSA_BUILTIN (srlri_h, MIPS_V8HI_FTYPE_V8HI_UQI), 16000 MSA_BUILTIN_PURE (srlri_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15923 MSA_BUILTIN (srlri_w, MIPS_V4SI_FTYPE_V4SI_UQI), 16001 MSA_BUILTIN_PURE (srlri_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15924 MSA_BUILTIN (srlri_d, MIPS_V2DI_FTYPE_V2DI_UQI), 16002 MSA_BUILTIN_PURE (srlri_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15925 MSA_BUILTIN (bclr_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16003 MSA_BUILTIN_PURE (bclr_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
15926 MSA_BUILTIN (bclr_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI), 16004 MSA_BUILTIN_PURE (bclr_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
15927 MSA_BUILTIN (bclr_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI), 16005 MSA_BUILTIN_PURE (bclr_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
15928 MSA_BUILTIN (bclr_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI), 16006 MSA_BUILTIN_PURE (bclr_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
15929 MSA_BUILTIN (bclri_b, MIPS_UV16QI_FTYPE_UV16QI_UQI), 16007 MSA_BUILTIN_PURE (bclri_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
15930 MSA_BUILTIN (bclri_h, MIPS_UV8HI_FTYPE_UV8HI_UQI), 16008 MSA_BUILTIN_PURE (bclri_h, MIPS_UV8HI_FTYPE_UV8HI_UQI),
15931 MSA_BUILTIN (bclri_w, MIPS_UV4SI_FTYPE_UV4SI_UQI), 16009 MSA_BUILTIN_PURE (bclri_w, MIPS_UV4SI_FTYPE_UV4SI_UQI),
15932 MSA_BUILTIN (bclri_d, MIPS_UV2DI_FTYPE_UV2DI_UQI), 16010 MSA_BUILTIN_PURE (bclri_d, MIPS_UV2DI_FTYPE_UV2DI_UQI),
15933 MSA_BUILTIN (bset_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16011 MSA_BUILTIN_PURE (bset_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
15934 MSA_BUILTIN (bset_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI), 16012 MSA_BUILTIN_PURE (bset_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
15935 MSA_BUILTIN (bset_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI), 16013 MSA_BUILTIN_PURE (bset_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
15936 MSA_BUILTIN (bset_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI), 16014 MSA_BUILTIN_PURE (bset_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
15937 MSA_BUILTIN (bseti_b, MIPS_UV16QI_FTYPE_UV16QI_UQI), 16015 MSA_BUILTIN_PURE (bseti_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
15938 MSA_BUILTIN (bseti_h, MIPS_UV8HI_FTYPE_UV8HI_UQI), 16016 MSA_BUILTIN_PURE (bseti_h, MIPS_UV8HI_FTYPE_UV8HI_UQI),
15939 MSA_BUILTIN (bseti_w, MIPS_UV4SI_FTYPE_UV4SI_UQI), 16017 MSA_BUILTIN_PURE (bseti_w, MIPS_UV4SI_FTYPE_UV4SI_UQI),
15940 MSA_BUILTIN (bseti_d, MIPS_UV2DI_FTYPE_UV2DI_UQI), 16018 MSA_BUILTIN_PURE (bseti_d, MIPS_UV2DI_FTYPE_UV2DI_UQI),
15941 MSA_BUILTIN (bneg_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16019 MSA_BUILTIN_PURE (bneg_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
15942 MSA_BUILTIN (bneg_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI), 16020 MSA_BUILTIN_PURE (bneg_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
15943 MSA_BUILTIN (bneg_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI), 16021 MSA_BUILTIN_PURE (bneg_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
15944 MSA_BUILTIN (bneg_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI), 16022 MSA_BUILTIN_PURE (bneg_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
15945 MSA_BUILTIN (bnegi_b, MIPS_UV16QI_FTYPE_UV16QI_UQI), 16023 MSA_BUILTIN_PURE (bnegi_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
15946 MSA_BUILTIN (bnegi_h, MIPS_UV8HI_FTYPE_UV8HI_UQI), 16024 MSA_BUILTIN_PURE (bnegi_h, MIPS_UV8HI_FTYPE_UV8HI_UQI),
15947 MSA_BUILTIN (bnegi_w, MIPS_UV4SI_FTYPE_UV4SI_UQI), 16025 MSA_BUILTIN_PURE (bnegi_w, MIPS_UV4SI_FTYPE_UV4SI_UQI),
15948 MSA_BUILTIN (bnegi_d, MIPS_UV2DI_FTYPE_UV2DI_UQI), 16026 MSA_BUILTIN_PURE (bnegi_d, MIPS_UV2DI_FTYPE_UV2DI_UQI),
15949 MSA_BUILTIN (binsl_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI), 16027 MSA_BUILTIN_PURE (binsl_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI),
15950 MSA_BUILTIN (binsl_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UV8HI), 16028 MSA_BUILTIN_PURE (binsl_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UV8HI),
15951 MSA_BUILTIN (binsl_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UV4SI), 16029 MSA_BUILTIN_PURE (binsl_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UV4SI),
15952 MSA_BUILTIN (binsl_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UV2DI), 16030 MSA_BUILTIN_PURE (binsl_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UV2DI),
15953 MSA_BUILTIN (binsli_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI), 16031 MSA_BUILTIN_PURE (binsli_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI),
15954 MSA_BUILTIN (binsli_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UQI), 16032 MSA_BUILTIN_PURE (binsli_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UQI),
15955 MSA_BUILTIN (binsli_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UQI), 16033 MSA_BUILTIN_PURE (binsli_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UQI),
15956 MSA_BUILTIN (binsli_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UQI), 16034 MSA_BUILTIN_PURE (binsli_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UQI),
15957 MSA_BUILTIN (binsr_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI), 16035 MSA_BUILTIN_PURE (binsr_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI),
15958 MSA_BUILTIN (binsr_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UV8HI), 16036 MSA_BUILTIN_PURE (binsr_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UV8HI),
15959 MSA_BUILTIN (binsr_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UV4SI), 16037 MSA_BUILTIN_PURE (binsr_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UV4SI),
15960 MSA_BUILTIN (binsr_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UV2DI), 16038 MSA_BUILTIN_PURE (binsr_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UV2DI),
15961 MSA_BUILTIN (binsri_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI), 16039 MSA_BUILTIN_PURE (binsri_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI),
15962 MSA_BUILTIN (binsri_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UQI), 16040 MSA_BUILTIN_PURE (binsri_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI_UQI),
15963 MSA_BUILTIN (binsri_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UQI), 16041 MSA_BUILTIN_PURE (binsri_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI_UQI),
15964 MSA_BUILTIN (binsri_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UQI), 16042 MSA_BUILTIN_PURE (binsri_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI_UQI),
15965 MSA_BUILTIN (addv_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16043 MSA_BUILTIN_PURE (addv_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15966 MSA_BUILTIN (addv_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16044 MSA_BUILTIN_PURE (addv_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15967 MSA_BUILTIN (addv_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16045 MSA_BUILTIN_PURE (addv_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15968 MSA_BUILTIN (addv_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16046 MSA_BUILTIN_PURE (addv_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15969 MSA_BUILTIN (addvi_b, MIPS_V16QI_FTYPE_V16QI_UQI), 16047 MSA_BUILTIN_PURE (addvi_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15970 MSA_BUILTIN (addvi_h, MIPS_V8HI_FTYPE_V8HI_UQI), 16048 MSA_BUILTIN_PURE (addvi_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15971 MSA_BUILTIN (addvi_w, MIPS_V4SI_FTYPE_V4SI_UQI), 16049 MSA_BUILTIN_PURE (addvi_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15972 MSA_BUILTIN (addvi_d, MIPS_V2DI_FTYPE_V2DI_UQI), 16050 MSA_BUILTIN_PURE (addvi_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15973 MSA_BUILTIN (subv_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16051 MSA_BUILTIN_PURE (subv_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15974 MSA_BUILTIN (subv_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16052 MSA_BUILTIN_PURE (subv_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15975 MSA_BUILTIN (subv_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16053 MSA_BUILTIN_PURE (subv_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15976 MSA_BUILTIN (subv_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16054 MSA_BUILTIN_PURE (subv_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15977 MSA_BUILTIN (subvi_b, MIPS_V16QI_FTYPE_V16QI_UQI), 16055 MSA_BUILTIN_PURE (subvi_b, MIPS_V16QI_FTYPE_V16QI_UQI),
15978 MSA_BUILTIN (subvi_h, MIPS_V8HI_FTYPE_V8HI_UQI), 16056 MSA_BUILTIN_PURE (subvi_h, MIPS_V8HI_FTYPE_V8HI_UQI),
15979 MSA_BUILTIN (subvi_w, MIPS_V4SI_FTYPE_V4SI_UQI), 16057 MSA_BUILTIN_PURE (subvi_w, MIPS_V4SI_FTYPE_V4SI_UQI),
15980 MSA_BUILTIN (subvi_d, MIPS_V2DI_FTYPE_V2DI_UQI), 16058 MSA_BUILTIN_PURE (subvi_d, MIPS_V2DI_FTYPE_V2DI_UQI),
15981 MSA_BUILTIN (max_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16059 MSA_BUILTIN_PURE (max_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15982 MSA_BUILTIN (max_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16060 MSA_BUILTIN_PURE (max_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15983 MSA_BUILTIN (max_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16061 MSA_BUILTIN_PURE (max_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
15984 MSA_BUILTIN (max_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16062 MSA_BUILTIN_PURE (max_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
15985 MSA_BUILTIN (maxi_s_b, MIPS_V16QI_FTYPE_V16QI_QI), 16063 MSA_BUILTIN_PURE (maxi_s_b, MIPS_V16QI_FTYPE_V16QI_QI),
15986 MSA_BUILTIN (maxi_s_h, MIPS_V8HI_FTYPE_V8HI_QI), 16064 MSA_BUILTIN_PURE (maxi_s_h, MIPS_V8HI_FTYPE_V8HI_QI),
15987 MSA_BUILTIN (maxi_s_w, MIPS_V4SI_FTYPE_V4SI_QI), 16065 MSA_BUILTIN_PURE (maxi_s_w, MIPS_V4SI_FTYPE_V4SI_QI),
15988 MSA_BUILTIN (maxi_s_d, MIPS_V2DI_FTYPE_V2DI_QI), 16066 MSA_BUILTIN_PURE (maxi_s_d, MIPS_V2DI_FTYPE_V2DI_QI),
15989 MSA_BUILTIN (max_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16067 MSA_BUILTIN_PURE (max_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
15990 MSA_BUILTIN (max_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI), 16068 MSA_BUILTIN_PURE (max_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
15991 MSA_BUILTIN (max_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI), 16069 MSA_BUILTIN_PURE (max_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
15992 MSA_BUILTIN (max_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI), 16070 MSA_BUILTIN_PURE (max_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
15993 MSA_BUILTIN (maxi_u_b, MIPS_UV16QI_FTYPE_UV16QI_UQI), 16071 MSA_BUILTIN_PURE (maxi_u_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
15994 MSA_BUILTIN (maxi_u_h, MIPS_UV8HI_FTYPE_UV8HI_UQI), 16072 MSA_BUILTIN_PURE (maxi_u_h, MIPS_UV8HI_FTYPE_UV8HI_UQI),
15995 MSA_BUILTIN (maxi_u_w, MIPS_UV4SI_FTYPE_UV4SI_UQI), 16073 MSA_BUILTIN_PURE (maxi_u_w, MIPS_UV4SI_FTYPE_UV4SI_UQI),
15996 MSA_BUILTIN (maxi_u_d, MIPS_UV2DI_FTYPE_UV2DI_UQI), 16074 MSA_BUILTIN_PURE (maxi_u_d, MIPS_UV2DI_FTYPE_UV2DI_UQI),
15997 MSA_BUILTIN (min_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16075 MSA_BUILTIN_PURE (min_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
15998 MSA_BUILTIN (min_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16076 MSA_BUILTIN_PURE (min_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
15999 MSA_BUILTIN (min_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16077 MSA_BUILTIN_PURE (min_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16000 MSA_BUILTIN (min_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16078 MSA_BUILTIN_PURE (min_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16001 MSA_BUILTIN (mini_s_b, MIPS_V16QI_FTYPE_V16QI_QI), 16079 MSA_BUILTIN_PURE (mini_s_b, MIPS_V16QI_FTYPE_V16QI_QI),
16002 MSA_BUILTIN (mini_s_h, MIPS_V8HI_FTYPE_V8HI_QI), 16080 MSA_BUILTIN_PURE (mini_s_h, MIPS_V8HI_FTYPE_V8HI_QI),
16003 MSA_BUILTIN (mini_s_w, MIPS_V4SI_FTYPE_V4SI_QI), 16081 MSA_BUILTIN_PURE (mini_s_w, MIPS_V4SI_FTYPE_V4SI_QI),
16004 MSA_BUILTIN (mini_s_d, MIPS_V2DI_FTYPE_V2DI_QI), 16082 MSA_BUILTIN_PURE (mini_s_d, MIPS_V2DI_FTYPE_V2DI_QI),
16005 MSA_BUILTIN (min_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16083 MSA_BUILTIN_PURE (min_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16006 MSA_BUILTIN (min_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI), 16084 MSA_BUILTIN_PURE (min_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16007 MSA_BUILTIN (min_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI), 16085 MSA_BUILTIN_PURE (min_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16008 MSA_BUILTIN (min_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI), 16086 MSA_BUILTIN_PURE (min_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16009 MSA_BUILTIN (mini_u_b, MIPS_UV16QI_FTYPE_UV16QI_UQI), 16087 MSA_BUILTIN_PURE (mini_u_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
16010 MSA_BUILTIN (mini_u_h, MIPS_UV8HI_FTYPE_UV8HI_UQI), 16088 MSA_BUILTIN_PURE (mini_u_h, MIPS_UV8HI_FTYPE_UV8HI_UQI),
16011 MSA_BUILTIN (mini_u_w, MIPS_UV4SI_FTYPE_UV4SI_UQI), 16089 MSA_BUILTIN_PURE (mini_u_w, MIPS_UV4SI_FTYPE_UV4SI_UQI),
16012 MSA_BUILTIN (mini_u_d, MIPS_UV2DI_FTYPE_UV2DI_UQI), 16090 MSA_BUILTIN_PURE (mini_u_d, MIPS_UV2DI_FTYPE_UV2DI_UQI),
16013 MSA_BUILTIN (max_a_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16091 MSA_BUILTIN_PURE (max_a_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16014 MSA_BUILTIN (max_a_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16092 MSA_BUILTIN_PURE (max_a_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16015 MSA_BUILTIN (max_a_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16093 MSA_BUILTIN_PURE (max_a_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16016 MSA_BUILTIN (max_a_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16094 MSA_BUILTIN_PURE (max_a_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16017 MSA_BUILTIN (min_a_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16095 MSA_BUILTIN_PURE (min_a_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16018 MSA_BUILTIN (min_a_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16096 MSA_BUILTIN_PURE (min_a_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16019 MSA_BUILTIN (min_a_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16097 MSA_BUILTIN_PURE (min_a_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16020 MSA_BUILTIN (min_a_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16098 MSA_BUILTIN_PURE (min_a_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16021 MSA_BUILTIN (ceq_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16099 MSA_BUILTIN (ceq_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16022 MSA_BUILTIN (ceq_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16100 MSA_BUILTIN (ceq_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16023 MSA_BUILTIN (ceq_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16101 MSA_BUILTIN (ceq_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16024 MSA_BUILTIN (ceq_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16102 MSA_BUILTIN (ceq_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16025 MSA_BUILTIN (ceqi_b, MIPS_V16QI_FTYPE_V16QI_QI), 16103 MSA_BUILTIN (ceqi_b, MIPS_V16QI_FTYPE_V16QI_QI),
16064 MSA_BUILTIN (ld_d, MIPS_V2DI_FTYPE_CVPOINTER_SI), 16142 MSA_BUILTIN (ld_d, MIPS_V2DI_FTYPE_CVPOINTER_SI),
16065 MSA_NO_TARGET_BUILTIN (st_b, MIPS_VOID_FTYPE_V16QI_CVPOINTER_SI), 16143 MSA_NO_TARGET_BUILTIN (st_b, MIPS_VOID_FTYPE_V16QI_CVPOINTER_SI),
16066 MSA_NO_TARGET_BUILTIN (st_h, MIPS_VOID_FTYPE_V8HI_CVPOINTER_SI), 16144 MSA_NO_TARGET_BUILTIN (st_h, MIPS_VOID_FTYPE_V8HI_CVPOINTER_SI),
16067 MSA_NO_TARGET_BUILTIN (st_w, MIPS_VOID_FTYPE_V4SI_CVPOINTER_SI), 16145 MSA_NO_TARGET_BUILTIN (st_w, MIPS_VOID_FTYPE_V4SI_CVPOINTER_SI),
16068 MSA_NO_TARGET_BUILTIN (st_d, MIPS_VOID_FTYPE_V2DI_CVPOINTER_SI), 16146 MSA_NO_TARGET_BUILTIN (st_d, MIPS_VOID_FTYPE_V2DI_CVPOINTER_SI),
16069 MSA_BUILTIN (sat_s_b, MIPS_V16QI_FTYPE_V16QI_UQI), 16147 MSA_BUILTIN_PURE (sat_s_b, MIPS_V16QI_FTYPE_V16QI_UQI),
16070 MSA_BUILTIN (sat_s_h, MIPS_V8HI_FTYPE_V8HI_UQI), 16148 MSA_BUILTIN_PURE (sat_s_h, MIPS_V8HI_FTYPE_V8HI_UQI),
16071 MSA_BUILTIN (sat_s_w, MIPS_V4SI_FTYPE_V4SI_UQI), 16149 MSA_BUILTIN_PURE (sat_s_w, MIPS_V4SI_FTYPE_V4SI_UQI),
16072 MSA_BUILTIN (sat_s_d, MIPS_V2DI_FTYPE_V2DI_UQI), 16150 MSA_BUILTIN_PURE (sat_s_d, MIPS_V2DI_FTYPE_V2DI_UQI),
16073 MSA_BUILTIN (sat_u_b, MIPS_UV16QI_FTYPE_UV16QI_UQI), 16151 MSA_BUILTIN_PURE (sat_u_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
16074 MSA_BUILTIN (sat_u_h, MIPS_UV8HI_FTYPE_UV8HI_UQI), 16152 MSA_BUILTIN_PURE (sat_u_h, MIPS_UV8HI_FTYPE_UV8HI_UQI),
16075 MSA_BUILTIN (sat_u_w, MIPS_UV4SI_FTYPE_UV4SI_UQI), 16153 MSA_BUILTIN_PURE (sat_u_w, MIPS_UV4SI_FTYPE_UV4SI_UQI),
16076 MSA_BUILTIN (sat_u_d, MIPS_UV2DI_FTYPE_UV2DI_UQI), 16154 MSA_BUILTIN_PURE (sat_u_d, MIPS_UV2DI_FTYPE_UV2DI_UQI),
16077 MSA_BUILTIN (add_a_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16155 MSA_BUILTIN_PURE (add_a_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16078 MSA_BUILTIN (add_a_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16156 MSA_BUILTIN_PURE (add_a_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16079 MSA_BUILTIN (add_a_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16157 MSA_BUILTIN_PURE (add_a_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16080 MSA_BUILTIN (add_a_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16158 MSA_BUILTIN_PURE (add_a_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16081 MSA_BUILTIN (adds_a_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16159 MSA_BUILTIN_PURE (adds_a_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16082 MSA_BUILTIN (adds_a_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16160 MSA_BUILTIN_PURE (adds_a_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16083 MSA_BUILTIN (adds_a_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16161 MSA_BUILTIN_PURE (adds_a_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16084 MSA_BUILTIN (adds_a_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16162 MSA_BUILTIN_PURE (adds_a_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16085 MSA_BUILTIN (adds_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16163 MSA_BUILTIN_PURE (adds_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16086 MSA_BUILTIN (adds_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16164 MSA_BUILTIN_PURE (adds_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16087 MSA_BUILTIN (adds_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16165 MSA_BUILTIN_PURE (adds_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16088 MSA_BUILTIN (adds_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16166 MSA_BUILTIN_PURE (adds_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16089 MSA_BUILTIN (adds_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16167 MSA_BUILTIN_PURE (adds_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16090 MSA_BUILTIN (adds_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI), 16168 MSA_BUILTIN_PURE (adds_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16091 MSA_BUILTIN (adds_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI), 16169 MSA_BUILTIN_PURE (adds_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16092 MSA_BUILTIN (adds_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI), 16170 MSA_BUILTIN_PURE (adds_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16093 MSA_BUILTIN (ave_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16171 MSA_BUILTIN_PURE (ave_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16094 MSA_BUILTIN (ave_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16172 MSA_BUILTIN_PURE (ave_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16095 MSA_BUILTIN (ave_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16173 MSA_BUILTIN_PURE (ave_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16096 MSA_BUILTIN (ave_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16174 MSA_BUILTIN_PURE (ave_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16097 MSA_BUILTIN (ave_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16175 MSA_BUILTIN_PURE (ave_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16098 MSA_BUILTIN (ave_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI), 16176 MSA_BUILTIN_PURE (ave_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16099 MSA_BUILTIN (ave_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI), 16177 MSA_BUILTIN_PURE (ave_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16100 MSA_BUILTIN (ave_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI), 16178 MSA_BUILTIN_PURE (ave_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16101 MSA_BUILTIN (aver_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16179 MSA_BUILTIN_PURE (aver_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16102 MSA_BUILTIN (aver_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16180 MSA_BUILTIN_PURE (aver_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16103 MSA_BUILTIN (aver_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16181 MSA_BUILTIN_PURE (aver_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16104 MSA_BUILTIN (aver_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16182 MSA_BUILTIN_PURE (aver_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16105 MSA_BUILTIN (aver_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16183 MSA_BUILTIN_PURE (aver_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16106 MSA_BUILTIN (aver_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI), 16184 MSA_BUILTIN_PURE (aver_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16107 MSA_BUILTIN (aver_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI), 16185 MSA_BUILTIN_PURE (aver_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16108 MSA_BUILTIN (aver_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI), 16186 MSA_BUILTIN_PURE (aver_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16109 MSA_BUILTIN (subs_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16187 MSA_BUILTIN_PURE (subs_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16110 MSA_BUILTIN (subs_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16188 MSA_BUILTIN_PURE (subs_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16111 MSA_BUILTIN (subs_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16189 MSA_BUILTIN_PURE (subs_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16112 MSA_BUILTIN (subs_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16190 MSA_BUILTIN_PURE (subs_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16113 MSA_BUILTIN (subs_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16191 MSA_BUILTIN_PURE (subs_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16114 MSA_BUILTIN (subs_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI), 16192 MSA_BUILTIN_PURE (subs_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16115 MSA_BUILTIN (subs_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI), 16193 MSA_BUILTIN_PURE (subs_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16116 MSA_BUILTIN (subs_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI), 16194 MSA_BUILTIN_PURE (subs_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16117 MSA_BUILTIN (subsuu_s_b, MIPS_V16QI_FTYPE_UV16QI_UV16QI), 16195 MSA_BUILTIN_PURE (subsuu_s_b, MIPS_V16QI_FTYPE_UV16QI_UV16QI),
16118 MSA_BUILTIN (subsuu_s_h, MIPS_V8HI_FTYPE_UV8HI_UV8HI), 16196 MSA_BUILTIN_PURE (subsuu_s_h, MIPS_V8HI_FTYPE_UV8HI_UV8HI),
16119 MSA_BUILTIN (subsuu_s_w, MIPS_V4SI_FTYPE_UV4SI_UV4SI), 16197 MSA_BUILTIN_PURE (subsuu_s_w, MIPS_V4SI_FTYPE_UV4SI_UV4SI),
16120 MSA_BUILTIN (subsuu_s_d, MIPS_V2DI_FTYPE_UV2DI_UV2DI), 16198 MSA_BUILTIN_PURE (subsuu_s_d, MIPS_V2DI_FTYPE_UV2DI_UV2DI),
16121 MSA_BUILTIN (subsus_u_b, MIPS_UV16QI_FTYPE_UV16QI_V16QI), 16199 MSA_BUILTIN_PURE (subsus_u_b, MIPS_UV16QI_FTYPE_UV16QI_V16QI),
16122 MSA_BUILTIN (subsus_u_h, MIPS_UV8HI_FTYPE_UV8HI_V8HI), 16200 MSA_BUILTIN_PURE (subsus_u_h, MIPS_UV8HI_FTYPE_UV8HI_V8HI),
16123 MSA_BUILTIN (subsus_u_w, MIPS_UV4SI_FTYPE_UV4SI_V4SI), 16201 MSA_BUILTIN_PURE (subsus_u_w, MIPS_UV4SI_FTYPE_UV4SI_V4SI),
16124 MSA_BUILTIN (subsus_u_d, MIPS_UV2DI_FTYPE_UV2DI_V2DI), 16202 MSA_BUILTIN_PURE (subsus_u_d, MIPS_UV2DI_FTYPE_UV2DI_V2DI),
16125 MSA_BUILTIN (asub_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16203 MSA_BUILTIN_PURE (asub_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16126 MSA_BUILTIN (asub_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16204 MSA_BUILTIN_PURE (asub_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16127 MSA_BUILTIN (asub_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16205 MSA_BUILTIN_PURE (asub_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16128 MSA_BUILTIN (asub_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16206 MSA_BUILTIN_PURE (asub_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16129 MSA_BUILTIN (asub_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16207 MSA_BUILTIN_PURE (asub_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16130 MSA_BUILTIN (asub_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI), 16208 MSA_BUILTIN_PURE (asub_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16131 MSA_BUILTIN (asub_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI), 16209 MSA_BUILTIN_PURE (asub_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16132 MSA_BUILTIN (asub_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI), 16210 MSA_BUILTIN_PURE (asub_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16133 MSA_BUILTIN (mulv_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16211 MSA_BUILTIN_PURE (mulv_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16134 MSA_BUILTIN (mulv_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16212 MSA_BUILTIN_PURE (mulv_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16135 MSA_BUILTIN (mulv_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16213 MSA_BUILTIN_PURE (mulv_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16136 MSA_BUILTIN (mulv_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16214 MSA_BUILTIN_PURE (mulv_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16137 MSA_BUILTIN (maddv_b, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI), 16215 MSA_BUILTIN_PURE (maddv_b, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI),
16138 MSA_BUILTIN (maddv_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI), 16216 MSA_BUILTIN_PURE (maddv_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16139 MSA_BUILTIN (maddv_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI), 16217 MSA_BUILTIN_PURE (maddv_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16140 MSA_BUILTIN (maddv_d, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI), 16218 MSA_BUILTIN_PURE (maddv_d, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI),
16141 MSA_BUILTIN (msubv_b, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI), 16219 MSA_BUILTIN_PURE (msubv_b, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI),
16142 MSA_BUILTIN (msubv_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI), 16220 MSA_BUILTIN_PURE (msubv_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16143 MSA_BUILTIN (msubv_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI), 16221 MSA_BUILTIN_PURE (msubv_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16144 MSA_BUILTIN (msubv_d, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI), 16222 MSA_BUILTIN_PURE (msubv_d, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI),
16145 MSA_BUILTIN (div_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16223 MSA_BUILTIN_PURE (div_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16146 MSA_BUILTIN (div_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16224 MSA_BUILTIN_PURE (div_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16147 MSA_BUILTIN (div_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16225 MSA_BUILTIN_PURE (div_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16148 MSA_BUILTIN (div_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16226 MSA_BUILTIN_PURE (div_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16149 MSA_BUILTIN (div_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16227 MSA_BUILTIN_PURE (div_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16150 MSA_BUILTIN (div_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI), 16228 MSA_BUILTIN_PURE (div_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16151 MSA_BUILTIN (div_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI), 16229 MSA_BUILTIN_PURE (div_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16152 MSA_BUILTIN (div_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI), 16230 MSA_BUILTIN_PURE (div_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16153 MSA_BUILTIN (hadd_s_h, MIPS_V8HI_FTYPE_V16QI_V16QI), 16231 MSA_BUILTIN_PURE (hadd_s_h, MIPS_V8HI_FTYPE_V16QI_V16QI),
16154 MSA_BUILTIN (hadd_s_w, MIPS_V4SI_FTYPE_V8HI_V8HI), 16232 MSA_BUILTIN_PURE (hadd_s_w, MIPS_V4SI_FTYPE_V8HI_V8HI),
16155 MSA_BUILTIN (hadd_s_d, MIPS_V2DI_FTYPE_V4SI_V4SI), 16233 MSA_BUILTIN_PURE (hadd_s_d, MIPS_V2DI_FTYPE_V4SI_V4SI),
16156 MSA_BUILTIN (hadd_u_h, MIPS_UV8HI_FTYPE_UV16QI_UV16QI), 16234 MSA_BUILTIN_PURE (hadd_u_h, MIPS_UV8HI_FTYPE_UV16QI_UV16QI),
16157 MSA_BUILTIN (hadd_u_w, MIPS_UV4SI_FTYPE_UV8HI_UV8HI), 16235 MSA_BUILTIN_PURE (hadd_u_w, MIPS_UV4SI_FTYPE_UV8HI_UV8HI),
16158 MSA_BUILTIN (hadd_u_d, MIPS_UV2DI_FTYPE_UV4SI_UV4SI), 16236 MSA_BUILTIN_PURE (hadd_u_d, MIPS_UV2DI_FTYPE_UV4SI_UV4SI),
16159 MSA_BUILTIN (hsub_s_h, MIPS_V8HI_FTYPE_V16QI_V16QI), 16237 MSA_BUILTIN_PURE (hsub_s_h, MIPS_V8HI_FTYPE_V16QI_V16QI),
16160 MSA_BUILTIN (hsub_s_w, MIPS_V4SI_FTYPE_V8HI_V8HI), 16238 MSA_BUILTIN_PURE (hsub_s_w, MIPS_V4SI_FTYPE_V8HI_V8HI),
16161 MSA_BUILTIN (hsub_s_d, MIPS_V2DI_FTYPE_V4SI_V4SI), 16239 MSA_BUILTIN_PURE (hsub_s_d, MIPS_V2DI_FTYPE_V4SI_V4SI),
16162 MSA_BUILTIN (hsub_u_h, MIPS_V8HI_FTYPE_UV16QI_UV16QI), 16240 MSA_BUILTIN_PURE (hsub_u_h, MIPS_V8HI_FTYPE_UV16QI_UV16QI),
16163 MSA_BUILTIN (hsub_u_w, MIPS_V4SI_FTYPE_UV8HI_UV8HI), 16241 MSA_BUILTIN_PURE (hsub_u_w, MIPS_V4SI_FTYPE_UV8HI_UV8HI),
16164 MSA_BUILTIN (hsub_u_d, MIPS_V2DI_FTYPE_UV4SI_UV4SI), 16242 MSA_BUILTIN_PURE (hsub_u_d, MIPS_V2DI_FTYPE_UV4SI_UV4SI),
16165 MSA_BUILTIN (mod_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16243 MSA_BUILTIN_PURE (mod_s_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16166 MSA_BUILTIN (mod_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16244 MSA_BUILTIN_PURE (mod_s_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16167 MSA_BUILTIN (mod_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16245 MSA_BUILTIN_PURE (mod_s_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16168 MSA_BUILTIN (mod_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16246 MSA_BUILTIN_PURE (mod_s_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16169 MSA_BUILTIN (mod_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16247 MSA_BUILTIN_PURE (mod_u_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16170 MSA_BUILTIN (mod_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI), 16248 MSA_BUILTIN_PURE (mod_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV8HI),
16171 MSA_BUILTIN (mod_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI), 16249 MSA_BUILTIN_PURE (mod_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV4SI),
16172 MSA_BUILTIN (mod_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI), 16250 MSA_BUILTIN_PURE (mod_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV2DI),
16173 MSA_BUILTIN (dotp_s_h, MIPS_V8HI_FTYPE_V16QI_V16QI), 16251 MSA_BUILTIN_PURE (dotp_s_h, MIPS_V8HI_FTYPE_V16QI_V16QI),
16174 MSA_BUILTIN (dotp_s_w, MIPS_V4SI_FTYPE_V8HI_V8HI), 16252 MSA_BUILTIN_PURE (dotp_s_w, MIPS_V4SI_FTYPE_V8HI_V8HI),
16175 MSA_BUILTIN (dotp_s_d, MIPS_V2DI_FTYPE_V4SI_V4SI), 16253 MSA_BUILTIN_PURE (dotp_s_d, MIPS_V2DI_FTYPE_V4SI_V4SI),
16176 MSA_BUILTIN (dotp_u_h, MIPS_UV8HI_FTYPE_UV16QI_UV16QI), 16254 MSA_BUILTIN_PURE (dotp_u_h, MIPS_UV8HI_FTYPE_UV16QI_UV16QI),
16177 MSA_BUILTIN (dotp_u_w, MIPS_UV4SI_FTYPE_UV8HI_UV8HI), 16255 MSA_BUILTIN_PURE (dotp_u_w, MIPS_UV4SI_FTYPE_UV8HI_UV8HI),
16178 MSA_BUILTIN (dotp_u_d, MIPS_UV2DI_FTYPE_UV4SI_UV4SI), 16256 MSA_BUILTIN_PURE (dotp_u_d, MIPS_UV2DI_FTYPE_UV4SI_UV4SI),
16179 MSA_BUILTIN (dpadd_s_h, MIPS_V8HI_FTYPE_V8HI_V16QI_V16QI), 16257 MSA_BUILTIN_PURE (dpadd_s_h, MIPS_V8HI_FTYPE_V8HI_V16QI_V16QI),
16180 MSA_BUILTIN (dpadd_s_w, MIPS_V4SI_FTYPE_V4SI_V8HI_V8HI), 16258 MSA_BUILTIN_PURE (dpadd_s_w, MIPS_V4SI_FTYPE_V4SI_V8HI_V8HI),
16181 MSA_BUILTIN (dpadd_s_d, MIPS_V2DI_FTYPE_V2DI_V4SI_V4SI), 16259 MSA_BUILTIN_PURE (dpadd_s_d, MIPS_V2DI_FTYPE_V2DI_V4SI_V4SI),
16182 MSA_BUILTIN (dpadd_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV16QI_UV16QI), 16260 MSA_BUILTIN_PURE (dpadd_u_h, MIPS_UV8HI_FTYPE_UV8HI_UV16QI_UV16QI),
16183 MSA_BUILTIN (dpadd_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV8HI_UV8HI), 16261 MSA_BUILTIN_PURE (dpadd_u_w, MIPS_UV4SI_FTYPE_UV4SI_UV8HI_UV8HI),
16184 MSA_BUILTIN (dpadd_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV4SI_UV4SI), 16262 MSA_BUILTIN_PURE (dpadd_u_d, MIPS_UV2DI_FTYPE_UV2DI_UV4SI_UV4SI),
16185 MSA_BUILTIN (dpsub_s_h, MIPS_V8HI_FTYPE_V8HI_V16QI_V16QI), 16263 MSA_BUILTIN_PURE (dpsub_s_h, MIPS_V8HI_FTYPE_V8HI_V16QI_V16QI),
16186 MSA_BUILTIN (dpsub_s_w, MIPS_V4SI_FTYPE_V4SI_V8HI_V8HI), 16264 MSA_BUILTIN_PURE (dpsub_s_w, MIPS_V4SI_FTYPE_V4SI_V8HI_V8HI),
16187 MSA_BUILTIN (dpsub_s_d, MIPS_V2DI_FTYPE_V2DI_V4SI_V4SI), 16265 MSA_BUILTIN_PURE (dpsub_s_d, MIPS_V2DI_FTYPE_V2DI_V4SI_V4SI),
16188 MSA_BUILTIN (dpsub_u_h, MIPS_V8HI_FTYPE_V8HI_UV16QI_UV16QI), 16266 MSA_BUILTIN_PURE (dpsub_u_h, MIPS_V8HI_FTYPE_V8HI_UV16QI_UV16QI),
16189 MSA_BUILTIN (dpsub_u_w, MIPS_V4SI_FTYPE_V4SI_UV8HI_UV8HI), 16267 MSA_BUILTIN_PURE (dpsub_u_w, MIPS_V4SI_FTYPE_V4SI_UV8HI_UV8HI),
16190 MSA_BUILTIN (dpsub_u_d, MIPS_V2DI_FTYPE_V2DI_UV4SI_UV4SI), 16268 MSA_BUILTIN_PURE (dpsub_u_d, MIPS_V2DI_FTYPE_V2DI_UV4SI_UV4SI),
16191 MSA_BUILTIN (sld_b, MIPS_V16QI_FTYPE_V16QI_V16QI_SI), 16269 MSA_BUILTIN_PURE (sld_b, MIPS_V16QI_FTYPE_V16QI_V16QI_SI),
16192 MSA_BUILTIN (sld_h, MIPS_V8HI_FTYPE_V8HI_V8HI_SI), 16270 MSA_BUILTIN_PURE (sld_h, MIPS_V8HI_FTYPE_V8HI_V8HI_SI),
16193 MSA_BUILTIN (sld_w, MIPS_V4SI_FTYPE_V4SI_V4SI_SI), 16271 MSA_BUILTIN_PURE (sld_w, MIPS_V4SI_FTYPE_V4SI_V4SI_SI),
16194 MSA_BUILTIN (sld_d, MIPS_V2DI_FTYPE_V2DI_V2DI_SI), 16272 MSA_BUILTIN_PURE (sld_d, MIPS_V2DI_FTYPE_V2DI_V2DI_SI),
16195 MSA_BUILTIN (sldi_b, MIPS_V16QI_FTYPE_V16QI_V16QI_UQI), 16273 MSA_BUILTIN_PURE (sldi_b, MIPS_V16QI_FTYPE_V16QI_V16QI_UQI),
16196 MSA_BUILTIN (sldi_h, MIPS_V8HI_FTYPE_V8HI_V8HI_UQI), 16274 MSA_BUILTIN_PURE (sldi_h, MIPS_V8HI_FTYPE_V8HI_V8HI_UQI),
16197 MSA_BUILTIN (sldi_w, MIPS_V4SI_FTYPE_V4SI_V4SI_UQI), 16275 MSA_BUILTIN_PURE (sldi_w, MIPS_V4SI_FTYPE_V4SI_V4SI_UQI),
16198 MSA_BUILTIN (sldi_d, MIPS_V2DI_FTYPE_V2DI_V2DI_UQI), 16276 MSA_BUILTIN_PURE (sldi_d, MIPS_V2DI_FTYPE_V2DI_V2DI_UQI),
16199 MSA_BUILTIN (splat_b, MIPS_V16QI_FTYPE_V16QI_SI), 16277 MSA_BUILTIN_PURE (splat_b, MIPS_V16QI_FTYPE_V16QI_SI),
16200 MSA_BUILTIN (splat_h, MIPS_V8HI_FTYPE_V8HI_SI), 16278 MSA_BUILTIN_PURE (splat_h, MIPS_V8HI_FTYPE_V8HI_SI),
16201 MSA_BUILTIN (splat_w, MIPS_V4SI_FTYPE_V4SI_SI), 16279 MSA_BUILTIN_PURE (splat_w, MIPS_V4SI_FTYPE_V4SI_SI),
16202 MSA_BUILTIN (splat_d, MIPS_V2DI_FTYPE_V2DI_SI), 16280 MSA_BUILTIN_PURE (splat_d, MIPS_V2DI_FTYPE_V2DI_SI),
16203 MSA_BUILTIN (splati_b, MIPS_V16QI_FTYPE_V16QI_UQI), 16281 MSA_BUILTIN_PURE (splati_b, MIPS_V16QI_FTYPE_V16QI_UQI),
16204 MSA_BUILTIN (splati_h, MIPS_V8HI_FTYPE_V8HI_UQI), 16282 MSA_BUILTIN_PURE (splati_h, MIPS_V8HI_FTYPE_V8HI_UQI),
16205 MSA_BUILTIN (splati_w, MIPS_V4SI_FTYPE_V4SI_UQI), 16283 MSA_BUILTIN_PURE (splati_w, MIPS_V4SI_FTYPE_V4SI_UQI),
16206 MSA_BUILTIN (splati_d, MIPS_V2DI_FTYPE_V2DI_UQI), 16284 MSA_BUILTIN_PURE (splati_d, MIPS_V2DI_FTYPE_V2DI_UQI),
16207 MSA_BUILTIN (pckev_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16285 MSA_BUILTIN_PURE (pckev_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16208 MSA_BUILTIN (pckev_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16286 MSA_BUILTIN_PURE (pckev_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16209 MSA_BUILTIN (pckev_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16287 MSA_BUILTIN_PURE (pckev_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16210 MSA_BUILTIN (pckev_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16288 MSA_BUILTIN_PURE (pckev_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16211 MSA_BUILTIN (pckod_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16289 MSA_BUILTIN_PURE (pckod_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16212 MSA_BUILTIN (pckod_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16290 MSA_BUILTIN_PURE (pckod_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16213 MSA_BUILTIN (pckod_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16291 MSA_BUILTIN_PURE (pckod_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16214 MSA_BUILTIN (pckod_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16292 MSA_BUILTIN_PURE (pckod_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16215 MSA_BUILTIN (ilvl_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16293 MSA_BUILTIN_PURE (ilvl_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16216 MSA_BUILTIN (ilvl_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16294 MSA_BUILTIN_PURE (ilvl_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16217 MSA_BUILTIN (ilvl_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16295 MSA_BUILTIN_PURE (ilvl_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16218 MSA_BUILTIN (ilvl_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16296 MSA_BUILTIN_PURE (ilvl_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16219 MSA_BUILTIN (ilvr_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16297 MSA_BUILTIN_PURE (ilvr_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16220 MSA_BUILTIN (ilvr_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16298 MSA_BUILTIN_PURE (ilvr_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16221 MSA_BUILTIN (ilvr_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16299 MSA_BUILTIN_PURE (ilvr_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16222 MSA_BUILTIN (ilvr_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16300 MSA_BUILTIN_PURE (ilvr_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16223 MSA_BUILTIN (ilvev_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16301 MSA_BUILTIN_PURE (ilvev_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16224 MSA_BUILTIN (ilvev_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16302 MSA_BUILTIN_PURE (ilvev_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16225 MSA_BUILTIN (ilvev_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16303 MSA_BUILTIN_PURE (ilvev_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16226 MSA_BUILTIN (ilvev_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16304 MSA_BUILTIN_PURE (ilvev_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16227 MSA_BUILTIN (ilvod_b, MIPS_V16QI_FTYPE_V16QI_V16QI), 16305 MSA_BUILTIN_PURE (ilvod_b, MIPS_V16QI_FTYPE_V16QI_V16QI),
16228 MSA_BUILTIN (ilvod_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16306 MSA_BUILTIN_PURE (ilvod_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16229 MSA_BUILTIN (ilvod_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16307 MSA_BUILTIN_PURE (ilvod_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16230 MSA_BUILTIN (ilvod_d, MIPS_V2DI_FTYPE_V2DI_V2DI), 16308 MSA_BUILTIN_PURE (ilvod_d, MIPS_V2DI_FTYPE_V2DI_V2DI),
16231 MSA_BUILTIN (vshf_b, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI), 16309 MSA_BUILTIN_PURE (vshf_b, MIPS_V16QI_FTYPE_V16QI_V16QI_V16QI),
16232 MSA_BUILTIN (vshf_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI), 16310 MSA_BUILTIN_PURE (vshf_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16233 MSA_BUILTIN (vshf_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI), 16311 MSA_BUILTIN_PURE (vshf_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16234 MSA_BUILTIN (vshf_d, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI), 16312 MSA_BUILTIN_PURE (vshf_d, MIPS_V2DI_FTYPE_V2DI_V2DI_V2DI),
16235 MSA_BUILTIN (and_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16313 MSA_BUILTIN_PURE (and_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16236 MSA_BUILTIN (andi_b, MIPS_UV16QI_FTYPE_UV16QI_UQI), 16314 MSA_BUILTIN_PURE (andi_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
16237 MSA_BUILTIN (or_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16315 MSA_BUILTIN_PURE (or_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16238 MSA_BUILTIN (ori_b, MIPS_UV16QI_FTYPE_UV16QI_UQI), 16316 MSA_BUILTIN_PURE (ori_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
16239 MSA_BUILTIN (nor_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16317 MSA_BUILTIN_PURE (nor_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16240 MSA_BUILTIN (nori_b, MIPS_UV16QI_FTYPE_UV16QI_UQI), 16318 MSA_BUILTIN_PURE (nori_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
16241 MSA_BUILTIN (xor_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI), 16319 MSA_BUILTIN_PURE (xor_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI),
16242 MSA_BUILTIN (xori_b, MIPS_UV16QI_FTYPE_UV16QI_UQI), 16320 MSA_BUILTIN_PURE (xori_b, MIPS_UV16QI_FTYPE_UV16QI_UQI),
16243 MSA_BUILTIN (bmnz_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI), 16321 MSA_BUILTIN_PURE (bmnz_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI),
16244 MSA_BUILTIN (bmnzi_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI), 16322 MSA_BUILTIN_PURE (bmnzi_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI),
16245 MSA_BUILTIN (bmz_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI), 16323 MSA_BUILTIN_PURE (bmz_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI),
16246 MSA_BUILTIN (bmzi_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI), 16324 MSA_BUILTIN_PURE (bmzi_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI),
16247 MSA_BUILTIN (bsel_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI), 16325 MSA_BUILTIN_PURE (bsel_v, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UV16QI),
16248 MSA_BUILTIN (bseli_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI), 16326 MSA_BUILTIN_PURE (bseli_b, MIPS_UV16QI_FTYPE_UV16QI_UV16QI_UQI),
16249 MSA_BUILTIN (shf_b, MIPS_V16QI_FTYPE_V16QI_UQI), 16327 MSA_BUILTIN_PURE (shf_b, MIPS_V16QI_FTYPE_V16QI_UQI),
16250 MSA_BUILTIN (shf_h, MIPS_V8HI_FTYPE_V8HI_UQI), 16328 MSA_BUILTIN_PURE (shf_h, MIPS_V8HI_FTYPE_V8HI_UQI),
16251 MSA_BUILTIN (shf_w, MIPS_V4SI_FTYPE_V4SI_UQI), 16329 MSA_BUILTIN_PURE (shf_w, MIPS_V4SI_FTYPE_V4SI_UQI),
16252 MSA_BUILTIN_TEST_BRANCH (bnz_v, MIPS_SI_FTYPE_UV16QI), 16330 MSA_BUILTIN_TEST_BRANCH (bnz_v, MIPS_SI_FTYPE_UV16QI),
16253 MSA_BUILTIN_TEST_BRANCH (bz_v, MIPS_SI_FTYPE_UV16QI), 16331 MSA_BUILTIN_TEST_BRANCH (bz_v, MIPS_SI_FTYPE_UV16QI),
16254 MSA_BUILTIN (fill_b, MIPS_V16QI_FTYPE_SI), 16332 MSA_BUILTIN_PURE (fill_b, MIPS_V16QI_FTYPE_SI),
16255 MSA_BUILTIN (fill_h, MIPS_V8HI_FTYPE_SI), 16333 MSA_BUILTIN_PURE (fill_h, MIPS_V8HI_FTYPE_SI),
16256 MSA_BUILTIN (fill_w, MIPS_V4SI_FTYPE_SI), 16334 MSA_BUILTIN_PURE (fill_w, MIPS_V4SI_FTYPE_SI),
16257 MSA_BUILTIN (fill_d, MIPS_V2DI_FTYPE_DI), 16335 MSA_BUILTIN_PURE (fill_d, MIPS_V2DI_FTYPE_DI),
16258 MSA_BUILTIN (pcnt_b, MIPS_V16QI_FTYPE_V16QI), 16336 MSA_BUILTIN_PURE (pcnt_b, MIPS_V16QI_FTYPE_V16QI),
16259 MSA_BUILTIN (pcnt_h, MIPS_V8HI_FTYPE_V8HI), 16337 MSA_BUILTIN_PURE (pcnt_h, MIPS_V8HI_FTYPE_V8HI),
16260 MSA_BUILTIN (pcnt_w, MIPS_V4SI_FTYPE_V4SI), 16338 MSA_BUILTIN_PURE (pcnt_w, MIPS_V4SI_FTYPE_V4SI),
16261 MSA_BUILTIN (pcnt_d, MIPS_V2DI_FTYPE_V2DI), 16339 MSA_BUILTIN_PURE (pcnt_d, MIPS_V2DI_FTYPE_V2DI),
16262 MSA_BUILTIN (nloc_b, MIPS_V16QI_FTYPE_V16QI), 16340 MSA_BUILTIN_PURE (nloc_b, MIPS_V16QI_FTYPE_V16QI),
16263 MSA_BUILTIN (nloc_h, MIPS_V8HI_FTYPE_V8HI), 16341 MSA_BUILTIN_PURE (nloc_h, MIPS_V8HI_FTYPE_V8HI),
16264 MSA_BUILTIN (nloc_w, MIPS_V4SI_FTYPE_V4SI), 16342 MSA_BUILTIN_PURE (nloc_w, MIPS_V4SI_FTYPE_V4SI),
16265 MSA_BUILTIN (nloc_d, MIPS_V2DI_FTYPE_V2DI), 16343 MSA_BUILTIN_PURE (nloc_d, MIPS_V2DI_FTYPE_V2DI),
16266 MSA_BUILTIN (nlzc_b, MIPS_V16QI_FTYPE_V16QI), 16344 MSA_BUILTIN_PURE (nlzc_b, MIPS_V16QI_FTYPE_V16QI),
16267 MSA_BUILTIN (nlzc_h, MIPS_V8HI_FTYPE_V8HI), 16345 MSA_BUILTIN_PURE (nlzc_h, MIPS_V8HI_FTYPE_V8HI),
16268 MSA_BUILTIN (nlzc_w, MIPS_V4SI_FTYPE_V4SI), 16346 MSA_BUILTIN_PURE (nlzc_w, MIPS_V4SI_FTYPE_V4SI),
16269 MSA_BUILTIN (nlzc_d, MIPS_V2DI_FTYPE_V2DI), 16347 MSA_BUILTIN_PURE (nlzc_d, MIPS_V2DI_FTYPE_V2DI),
16270 MSA_BUILTIN (copy_s_b, MIPS_SI_FTYPE_V16QI_UQI), 16348 MSA_BUILTIN_PURE (copy_s_b, MIPS_SI_FTYPE_V16QI_UQI),
16271 MSA_BUILTIN (copy_s_h, MIPS_SI_FTYPE_V8HI_UQI), 16349 MSA_BUILTIN_PURE (copy_s_h, MIPS_SI_FTYPE_V8HI_UQI),
16272 MSA_BUILTIN (copy_s_w, MIPS_SI_FTYPE_V4SI_UQI), 16350 MSA_BUILTIN_PURE (copy_s_w, MIPS_SI_FTYPE_V4SI_UQI),
16273 MSA_BUILTIN (copy_s_d, MIPS_DI_FTYPE_V2DI_UQI), 16351 MSA_BUILTIN_PURE (copy_s_d, MIPS_DI_FTYPE_V2DI_UQI),
16274 MSA_BUILTIN (copy_u_b, MIPS_USI_FTYPE_V16QI_UQI), 16352 MSA_BUILTIN_PURE (copy_u_b, MIPS_USI_FTYPE_V16QI_UQI),
16275 MSA_BUILTIN (copy_u_h, MIPS_USI_FTYPE_V8HI_UQI), 16353 MSA_BUILTIN_PURE (copy_u_h, MIPS_USI_FTYPE_V8HI_UQI),
16276 MSA_BUILTIN_REMAP (copy_u_w, copy_s_w, MIPS_USI_FTYPE_V4SI_UQI), 16354 MSA_BUILTIN_REMAP (copy_u_w, copy_s_w, MIPS_USI_FTYPE_V4SI_UQI),
16277 MSA_BUILTIN_REMAP (copy_u_d, copy_s_d, MIPS_UDI_FTYPE_V2DI_UQI), 16355 MSA_BUILTIN_REMAP (copy_u_d, copy_s_d, MIPS_UDI_FTYPE_V2DI_UQI),
16278 MSA_BUILTIN (insert_b, MIPS_V16QI_FTYPE_V16QI_UQI_SI), 16356 MSA_BUILTIN_PURE (insert_b, MIPS_V16QI_FTYPE_V16QI_UQI_SI),
16279 MSA_BUILTIN (insert_h, MIPS_V8HI_FTYPE_V8HI_UQI_SI), 16357 MSA_BUILTIN_PURE (insert_h, MIPS_V8HI_FTYPE_V8HI_UQI_SI),
16280 MSA_BUILTIN (insert_w, MIPS_V4SI_FTYPE_V4SI_UQI_SI), 16358 MSA_BUILTIN_PURE (insert_w, MIPS_V4SI_FTYPE_V4SI_UQI_SI),
16281 MSA_BUILTIN (insert_d, MIPS_V2DI_FTYPE_V2DI_UQI_DI), 16359 MSA_BUILTIN_PURE (insert_d, MIPS_V2DI_FTYPE_V2DI_UQI_DI),
16282 MSA_BUILTIN (insve_b, MIPS_V16QI_FTYPE_V16QI_UQI_V16QI), 16360 MSA_BUILTIN_PURE (insve_b, MIPS_V16QI_FTYPE_V16QI_UQI_V16QI),
16283 MSA_BUILTIN (insve_h, MIPS_V8HI_FTYPE_V8HI_UQI_V8HI), 16361 MSA_BUILTIN_PURE (insve_h, MIPS_V8HI_FTYPE_V8HI_UQI_V8HI),
16284 MSA_BUILTIN (insve_w, MIPS_V4SI_FTYPE_V4SI_UQI_V4SI), 16362 MSA_BUILTIN_PURE (insve_w, MIPS_V4SI_FTYPE_V4SI_UQI_V4SI),
16285 MSA_BUILTIN (insve_d, MIPS_V2DI_FTYPE_V2DI_UQI_V2DI), 16363 MSA_BUILTIN_PURE (insve_d, MIPS_V2DI_FTYPE_V2DI_UQI_V2DI),
16286 MSA_BUILTIN_TEST_BRANCH (bnz_b, MIPS_SI_FTYPE_UV16QI), 16364 MSA_BUILTIN_TEST_BRANCH (bnz_b, MIPS_SI_FTYPE_UV16QI),
16287 MSA_BUILTIN_TEST_BRANCH (bnz_h, MIPS_SI_FTYPE_UV8HI), 16365 MSA_BUILTIN_TEST_BRANCH (bnz_h, MIPS_SI_FTYPE_UV8HI),
16288 MSA_BUILTIN_TEST_BRANCH (bnz_w, MIPS_SI_FTYPE_UV4SI), 16366 MSA_BUILTIN_TEST_BRANCH (bnz_w, MIPS_SI_FTYPE_UV4SI),
16289 MSA_BUILTIN_TEST_BRANCH (bnz_d, MIPS_SI_FTYPE_UV2DI), 16367 MSA_BUILTIN_TEST_BRANCH (bnz_d, MIPS_SI_FTYPE_UV2DI),
16290 MSA_BUILTIN_TEST_BRANCH (bz_b, MIPS_SI_FTYPE_UV16QI), 16368 MSA_BUILTIN_TEST_BRANCH (bz_b, MIPS_SI_FTYPE_UV16QI),
16291 MSA_BUILTIN_TEST_BRANCH (bz_h, MIPS_SI_FTYPE_UV8HI), 16369 MSA_BUILTIN_TEST_BRANCH (bz_h, MIPS_SI_FTYPE_UV8HI),
16292 MSA_BUILTIN_TEST_BRANCH (bz_w, MIPS_SI_FTYPE_UV4SI), 16370 MSA_BUILTIN_TEST_BRANCH (bz_w, MIPS_SI_FTYPE_UV4SI),
16293 MSA_BUILTIN_TEST_BRANCH (bz_d, MIPS_SI_FTYPE_UV2DI), 16371 MSA_BUILTIN_TEST_BRANCH (bz_d, MIPS_SI_FTYPE_UV2DI),
16294 MSA_BUILTIN (ldi_b, MIPS_V16QI_FTYPE_HI), 16372 MSA_BUILTIN_PURE (ldi_b, MIPS_V16QI_FTYPE_HI),
16295 MSA_BUILTIN (ldi_h, MIPS_V8HI_FTYPE_HI), 16373 MSA_BUILTIN_PURE (ldi_h, MIPS_V8HI_FTYPE_HI),
16296 MSA_BUILTIN (ldi_w, MIPS_V4SI_FTYPE_HI), 16374 MSA_BUILTIN_PURE (ldi_w, MIPS_V4SI_FTYPE_HI),
16297 MSA_BUILTIN (ldi_d, MIPS_V2DI_FTYPE_HI), 16375 MSA_BUILTIN_PURE (ldi_d, MIPS_V2DI_FTYPE_HI),
16298 MSA_BUILTIN (fcaf_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16376 MSA_BUILTIN_PURE (fcaf_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16299 MSA_BUILTIN (fcaf_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16377 MSA_BUILTIN_PURE (fcaf_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16300 MSA_BUILTIN (fcor_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16378 MSA_BUILTIN_PURE (fcor_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16301 MSA_BUILTIN (fcor_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16379 MSA_BUILTIN_PURE (fcor_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16302 MSA_BUILTIN (fcun_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16380 MSA_BUILTIN_PURE (fcun_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16303 MSA_BUILTIN (fcun_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16381 MSA_BUILTIN_PURE (fcun_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16304 MSA_BUILTIN (fcune_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16382 MSA_BUILTIN_PURE (fcune_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16305 MSA_BUILTIN (fcune_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16383 MSA_BUILTIN_PURE (fcune_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16306 MSA_BUILTIN (fcueq_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16384 MSA_BUILTIN_PURE (fcueq_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16307 MSA_BUILTIN (fcueq_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16385 MSA_BUILTIN_PURE (fcueq_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16308 MSA_BUILTIN (fceq_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16386 MSA_BUILTIN_PURE (fceq_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16309 MSA_BUILTIN (fceq_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16387 MSA_BUILTIN_PURE (fceq_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16310 MSA_BUILTIN (fcne_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16388 MSA_BUILTIN_PURE (fcne_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16311 MSA_BUILTIN (fcne_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16389 MSA_BUILTIN_PURE (fcne_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16312 MSA_BUILTIN (fclt_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16390 MSA_BUILTIN_PURE (fclt_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16313 MSA_BUILTIN (fclt_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16391 MSA_BUILTIN_PURE (fclt_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16314 MSA_BUILTIN (fcult_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16392 MSA_BUILTIN_PURE (fcult_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16315 MSA_BUILTIN (fcult_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16393 MSA_BUILTIN_PURE (fcult_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16316 MSA_BUILTIN (fcle_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16394 MSA_BUILTIN_PURE (fcle_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16317 MSA_BUILTIN (fcle_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16395 MSA_BUILTIN_PURE (fcle_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16318 MSA_BUILTIN (fcule_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16396 MSA_BUILTIN_PURE (fcule_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16319 MSA_BUILTIN (fcule_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16397 MSA_BUILTIN_PURE (fcule_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16320 MSA_BUILTIN (fsaf_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16398 MSA_BUILTIN_PURE (fsaf_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16321 MSA_BUILTIN (fsaf_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16399 MSA_BUILTIN_PURE (fsaf_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16322 MSA_BUILTIN (fsor_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16400 MSA_BUILTIN_PURE (fsor_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16323 MSA_BUILTIN (fsor_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16401 MSA_BUILTIN_PURE (fsor_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16324 MSA_BUILTIN (fsun_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16402 MSA_BUILTIN_PURE (fsun_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16325 MSA_BUILTIN (fsun_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16403 MSA_BUILTIN_PURE (fsun_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16326 MSA_BUILTIN (fsune_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16404 MSA_BUILTIN_PURE (fsune_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16327 MSA_BUILTIN (fsune_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16405 MSA_BUILTIN_PURE (fsune_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16328 MSA_BUILTIN (fsueq_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16406 MSA_BUILTIN_PURE (fsueq_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16329 MSA_BUILTIN (fsueq_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16407 MSA_BUILTIN_PURE (fsueq_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16330 MSA_BUILTIN (fseq_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16408 MSA_BUILTIN_PURE (fseq_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16331 MSA_BUILTIN (fseq_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16409 MSA_BUILTIN_PURE (fseq_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16332 MSA_BUILTIN (fsne_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16410 MSA_BUILTIN_PURE (fsne_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16333 MSA_BUILTIN (fsne_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16411 MSA_BUILTIN_PURE (fsne_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16334 MSA_BUILTIN (fslt_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16412 MSA_BUILTIN_PURE (fslt_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16335 MSA_BUILTIN (fslt_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16413 MSA_BUILTIN_PURE (fslt_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16336 MSA_BUILTIN (fsult_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16414 MSA_BUILTIN_PURE (fsult_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16337 MSA_BUILTIN (fsult_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16415 MSA_BUILTIN_PURE (fsult_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16338 MSA_BUILTIN (fsle_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16416 MSA_BUILTIN_PURE (fsle_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16339 MSA_BUILTIN (fsle_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16417 MSA_BUILTIN_PURE (fsle_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16340 MSA_BUILTIN (fsule_w, MIPS_V4SI_FTYPE_V4SF_V4SF), 16418 MSA_BUILTIN_PURE (fsule_w, MIPS_V4SI_FTYPE_V4SF_V4SF),
16341 MSA_BUILTIN (fsule_d, MIPS_V2DI_FTYPE_V2DF_V2DF), 16419 MSA_BUILTIN_PURE (fsule_d, MIPS_V2DI_FTYPE_V2DF_V2DF),
16342 MSA_BUILTIN (fadd_w, MIPS_V4SF_FTYPE_V4SF_V4SF), 16420 MSA_BUILTIN_PURE (fadd_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16343 MSA_BUILTIN (fadd_d, MIPS_V2DF_FTYPE_V2DF_V2DF), 16421 MSA_BUILTIN_PURE (fadd_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16344 MSA_BUILTIN (fsub_w, MIPS_V4SF_FTYPE_V4SF_V4SF), 16422 MSA_BUILTIN_PURE (fsub_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16345 MSA_BUILTIN (fsub_d, MIPS_V2DF_FTYPE_V2DF_V2DF), 16423 MSA_BUILTIN_PURE (fsub_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16346 MSA_BUILTIN (fmul_w, MIPS_V4SF_FTYPE_V4SF_V4SF), 16424 MSA_BUILTIN_PURE (fmul_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16347 MSA_BUILTIN (fmul_d, MIPS_V2DF_FTYPE_V2DF_V2DF), 16425 MSA_BUILTIN_PURE (fmul_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16348 MSA_BUILTIN (fdiv_w, MIPS_V4SF_FTYPE_V4SF_V4SF), 16426 MSA_BUILTIN_PURE (fdiv_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16349 MSA_BUILTIN (fdiv_d, MIPS_V2DF_FTYPE_V2DF_V2DF), 16427 MSA_BUILTIN_PURE (fdiv_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16350 MSA_BUILTIN (fmadd_w, MIPS_V4SF_FTYPE_V4SF_V4SF_V4SF), 16428 MSA_BUILTIN_PURE (fmadd_w, MIPS_V4SF_FTYPE_V4SF_V4SF_V4SF),
16351 MSA_BUILTIN (fmadd_d, MIPS_V2DF_FTYPE_V2DF_V2DF_V2DF), 16429 MSA_BUILTIN_PURE (fmadd_d, MIPS_V2DF_FTYPE_V2DF_V2DF_V2DF),
16352 MSA_BUILTIN (fmsub_w, MIPS_V4SF_FTYPE_V4SF_V4SF_V4SF), 16430 MSA_BUILTIN_PURE (fmsub_w, MIPS_V4SF_FTYPE_V4SF_V4SF_V4SF),
16353 MSA_BUILTIN (fmsub_d, MIPS_V2DF_FTYPE_V2DF_V2DF_V2DF), 16431 MSA_BUILTIN_PURE (fmsub_d, MIPS_V2DF_FTYPE_V2DF_V2DF_V2DF),
16354 MSA_BUILTIN (fexp2_w, MIPS_V4SF_FTYPE_V4SF_V4SI), 16432 MSA_BUILTIN_PURE (fexp2_w, MIPS_V4SF_FTYPE_V4SF_V4SI),
16355 MSA_BUILTIN (fexp2_d, MIPS_V2DF_FTYPE_V2DF_V2DI), 16433 MSA_BUILTIN_PURE (fexp2_d, MIPS_V2DF_FTYPE_V2DF_V2DI),
16356 MSA_BUILTIN (fexdo_h, MIPS_V8HI_FTYPE_V4SF_V4SF), 16434 MSA_BUILTIN_PURE (fexdo_h, MIPS_V8HI_FTYPE_V4SF_V4SF),
16357 MSA_BUILTIN (fexdo_w, MIPS_V4SF_FTYPE_V2DF_V2DF), 16435 MSA_BUILTIN_PURE (fexdo_w, MIPS_V4SF_FTYPE_V2DF_V2DF),
16358 MSA_BUILTIN (ftq_h, MIPS_V8HI_FTYPE_V4SF_V4SF), 16436 MSA_BUILTIN_PURE (ftq_h, MIPS_V8HI_FTYPE_V4SF_V4SF),
16359 MSA_BUILTIN (ftq_w, MIPS_V4SI_FTYPE_V2DF_V2DF), 16437 MSA_BUILTIN_PURE (ftq_w, MIPS_V4SI_FTYPE_V2DF_V2DF),
16360 MSA_BUILTIN (fmin_w, MIPS_V4SF_FTYPE_V4SF_V4SF), 16438 MSA_BUILTIN_PURE (fmin_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16361 MSA_BUILTIN (fmin_d, MIPS_V2DF_FTYPE_V2DF_V2DF), 16439 MSA_BUILTIN_PURE (fmin_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16362 MSA_BUILTIN (fmin_a_w, MIPS_V4SF_FTYPE_V4SF_V4SF), 16440 MSA_BUILTIN_PURE (fmin_a_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16363 MSA_BUILTIN (fmin_a_d, MIPS_V2DF_FTYPE_V2DF_V2DF), 16441 MSA_BUILTIN_PURE (fmin_a_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16364 MSA_BUILTIN (fmax_w, MIPS_V4SF_FTYPE_V4SF_V4SF), 16442 MSA_BUILTIN_PURE (fmax_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16365 MSA_BUILTIN (fmax_d, MIPS_V2DF_FTYPE_V2DF_V2DF), 16443 MSA_BUILTIN_PURE (fmax_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16366 MSA_BUILTIN (fmax_a_w, MIPS_V4SF_FTYPE_V4SF_V4SF), 16444 MSA_BUILTIN_PURE (fmax_a_w, MIPS_V4SF_FTYPE_V4SF_V4SF),
16367 MSA_BUILTIN (fmax_a_d, MIPS_V2DF_FTYPE_V2DF_V2DF), 16445 MSA_BUILTIN_PURE (fmax_a_d, MIPS_V2DF_FTYPE_V2DF_V2DF),
16368 MSA_BUILTIN (mul_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16446 MSA_BUILTIN_PURE (mul_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16369 MSA_BUILTIN (mul_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16447 MSA_BUILTIN_PURE (mul_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16370 MSA_BUILTIN (mulr_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI), 16448 MSA_BUILTIN_PURE (mulr_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI),
16371 MSA_BUILTIN (mulr_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI), 16449 MSA_BUILTIN_PURE (mulr_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI),
16372 MSA_BUILTIN (madd_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI), 16450 MSA_BUILTIN_PURE (madd_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16373 MSA_BUILTIN (madd_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI), 16451 MSA_BUILTIN_PURE (madd_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16374 MSA_BUILTIN (maddr_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI), 16452 MSA_BUILTIN_PURE (maddr_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16375 MSA_BUILTIN (maddr_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI), 16453 MSA_BUILTIN_PURE (maddr_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16376 MSA_BUILTIN (msub_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI), 16454 MSA_BUILTIN_PURE (msub_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16377 MSA_BUILTIN (msub_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI), 16455 MSA_BUILTIN_PURE (msub_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16378 MSA_BUILTIN (msubr_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI), 16456 MSA_BUILTIN_PURE (msubr_q_h, MIPS_V8HI_FTYPE_V8HI_V8HI_V8HI),
16379 MSA_BUILTIN (msubr_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI), 16457 MSA_BUILTIN_PURE (msubr_q_w, MIPS_V4SI_FTYPE_V4SI_V4SI_V4SI),
16380 MSA_BUILTIN (fclass_w, MIPS_V4SI_FTYPE_V4SF), 16458 MSA_BUILTIN_PURE (fclass_w, MIPS_V4SI_FTYPE_V4SF),
16381 MSA_BUILTIN (fclass_d, MIPS_V2DI_FTYPE_V2DF), 16459 MSA_BUILTIN_PURE (fclass_d, MIPS_V2DI_FTYPE_V2DF),
16382 MSA_BUILTIN (fsqrt_w, MIPS_V4SF_FTYPE_V4SF), 16460 MSA_BUILTIN_PURE (fsqrt_w, MIPS_V4SF_FTYPE_V4SF),
16383 MSA_BUILTIN (fsqrt_d, MIPS_V2DF_FTYPE_V2DF), 16461 MSA_BUILTIN_PURE (fsqrt_d, MIPS_V2DF_FTYPE_V2DF),
16384 MSA_BUILTIN (frcp_w, MIPS_V4SF_FTYPE_V4SF), 16462 MSA_BUILTIN_PURE (frcp_w, MIPS_V4SF_FTYPE_V4SF),
16385 MSA_BUILTIN (frcp_d, MIPS_V2DF_FTYPE_V2DF), 16463 MSA_BUILTIN_PURE (frcp_d, MIPS_V2DF_FTYPE_V2DF),
16386 MSA_BUILTIN (frint_w, MIPS_V4SF_FTYPE_V4SF), 16464 MSA_BUILTIN_PURE (frint_w, MIPS_V4SF_FTYPE_V4SF),
16387 MSA_BUILTIN (frint_d, MIPS_V2DF_FTYPE_V2DF), 16465 MSA_BUILTIN_PURE (frint_d, MIPS_V2DF_FTYPE_V2DF),
16388 MSA_BUILTIN (frsqrt_w, MIPS_V4SF_FTYPE_V4SF), 16466 MSA_BUILTIN_PURE (frsqrt_w, MIPS_V4SF_FTYPE_V4SF),
16389 MSA_BUILTIN (frsqrt_d, MIPS_V2DF_FTYPE_V2DF), 16467 MSA_BUILTIN_PURE (frsqrt_d, MIPS_V2DF_FTYPE_V2DF),
16390 MSA_BUILTIN (flog2_w, MIPS_V4SF_FTYPE_V4SF), 16468 MSA_BUILTIN_PURE (flog2_w, MIPS_V4SF_FTYPE_V4SF),
16391 MSA_BUILTIN (flog2_d, MIPS_V2DF_FTYPE_V2DF), 16469 MSA_BUILTIN_PURE (flog2_d, MIPS_V2DF_FTYPE_V2DF),
16392 MSA_BUILTIN (fexupl_w, MIPS_V4SF_FTYPE_V8HI), 16470 MSA_BUILTIN_PURE (fexupl_w, MIPS_V4SF_FTYPE_V8HI),
16393 MSA_BUILTIN (fexupl_d, MIPS_V2DF_FTYPE_V4SF), 16471 MSA_BUILTIN_PURE (fexupl_d, MIPS_V2DF_FTYPE_V4SF),
16394 MSA_BUILTIN (fexupr_w, MIPS_V4SF_FTYPE_V8HI), 16472 MSA_BUILTIN_PURE (fexupr_w, MIPS_V4SF_FTYPE_V8HI),
16395 MSA_BUILTIN (fexupr_d, MIPS_V2DF_FTYPE_V4SF), 16473 MSA_BUILTIN_PURE (fexupr_d, MIPS_V2DF_FTYPE_V4SF),
16396 MSA_BUILTIN (ffql_w, MIPS_V4SF_FTYPE_V8HI), 16474 MSA_BUILTIN_PURE (ffql_w, MIPS_V4SF_FTYPE_V8HI),
16397 MSA_BUILTIN (ffql_d, MIPS_V2DF_FTYPE_V4SI), 16475 MSA_BUILTIN_PURE (ffql_d, MIPS_V2DF_FTYPE_V4SI),
16398 MSA_BUILTIN (ffqr_w, MIPS_V4SF_FTYPE_V8HI), 16476 MSA_BUILTIN_PURE (ffqr_w, MIPS_V4SF_FTYPE_V8HI),
16399 MSA_BUILTIN (ffqr_d, MIPS_V2DF_FTYPE_V4SI), 16477 MSA_BUILTIN_PURE (ffqr_d, MIPS_V2DF_FTYPE_V4SI),
16400 MSA_BUILTIN (ftint_s_w, MIPS_V4SI_FTYPE_V4SF), 16478 MSA_BUILTIN_PURE (ftint_s_w, MIPS_V4SI_FTYPE_V4SF),
16401 MSA_BUILTIN (ftint_s_d, MIPS_V2DI_FTYPE_V2DF), 16479 MSA_BUILTIN_PURE (ftint_s_d, MIPS_V2DI_FTYPE_V2DF),
16402 MSA_BUILTIN (ftint_u_w, MIPS_UV4SI_FTYPE_V4SF), 16480 MSA_BUILTIN_PURE (ftint_u_w, MIPS_UV4SI_FTYPE_V4SF),
16403 MSA_BUILTIN (ftint_u_d, MIPS_UV2DI_FTYPE_V2DF), 16481 MSA_BUILTIN_PURE (ftint_u_d, MIPS_UV2DI_FTYPE_V2DF),
16404 MSA_BUILTIN (ftrunc_s_w, MIPS_V4SI_FTYPE_V4SF), 16482 MSA_BUILTIN_PURE (ftrunc_s_w, MIPS_V4SI_FTYPE_V4SF),
16405 MSA_BUILTIN (ftrunc_s_d, MIPS_V2DI_FTYPE_V2DF), 16483 MSA_BUILTIN_PURE (ftrunc_s_d, MIPS_V2DI_FTYPE_V2DF),
16406 MSA_BUILTIN (ftrunc_u_w, MIPS_UV4SI_FTYPE_V4SF), 16484 MSA_BUILTIN_PURE (ftrunc_u_w, MIPS_UV4SI_FTYPE_V4SF),
16407 MSA_BUILTIN (ftrunc_u_d, MIPS_UV2DI_FTYPE_V2DF), 16485 MSA_BUILTIN_PURE (ftrunc_u_d, MIPS_UV2DI_FTYPE_V2DF),
16408 MSA_BUILTIN (ffint_s_w, MIPS_V4SF_FTYPE_V4SI), 16486 MSA_BUILTIN_PURE (ffint_s_w, MIPS_V4SF_FTYPE_V4SI),
16409 MSA_BUILTIN (ffint_s_d, MIPS_V2DF_FTYPE_V2DI), 16487 MSA_BUILTIN_PURE (ffint_s_d, MIPS_V2DF_FTYPE_V2DI),
16410 MSA_BUILTIN (ffint_u_w, MIPS_V4SF_FTYPE_UV4SI), 16488 MSA_BUILTIN_PURE (ffint_u_w, MIPS_V4SF_FTYPE_UV4SI),
16411 MSA_BUILTIN (ffint_u_d, MIPS_V2DF_FTYPE_UV2DI), 16489 MSA_BUILTIN_PURE (ffint_u_d, MIPS_V2DF_FTYPE_UV2DI),
16412 MSA_NO_TARGET_BUILTIN (ctcmsa, MIPS_VOID_FTYPE_UQI_SI), 16490 MSA_NO_TARGET_BUILTIN (ctcmsa, MIPS_VOID_FTYPE_UQI_SI),
16413 MSA_BUILTIN (cfcmsa, MIPS_SI_FTYPE_UQI), 16491 MSA_BUILTIN_PURE (cfcmsa, MIPS_SI_FTYPE_UQI),
16414 MSA_BUILTIN (move_v, MIPS_V16QI_FTYPE_V16QI), 16492 MSA_BUILTIN_PURE (move_v, MIPS_V16QI_FTYPE_V16QI),
16415 }; 16493 };
16416 16494
16417 /* Index I is the function declaration for mips_builtins[I], or null if the 16495 /* Index I is the function declaration for mips_builtins[I], or null if the
16418 function isn't defined on this target. */ 16496 function isn't defined on this target. */
16419 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)]; 16497 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
16560 { 16638 {
16561 mips_builtin_decls[i] 16639 mips_builtin_decls[i]
16562 = add_builtin_function (d->name, 16640 = add_builtin_function (d->name,
16563 mips_build_function_type (d->function_type), 16641 mips_build_function_type (d->function_type),
16564 i, BUILT_IN_MD, NULL, NULL); 16642 i, BUILT_IN_MD, NULL, NULL);
16643 if (mips_builtin_decls[i] && d->is_pure)
16644 DECL_PURE_P (mips_builtin_decls[i]) = 1;
16565 mips_get_builtin_decl_index[d->icode] = i; 16645 mips_get_builtin_decl_index[d->icode] = i;
16566 } 16646 }
16567 } 16647 }
16568 } 16648 }
16569 16649
16810 swap is needed for builtins. */ 16890 swap is needed for builtins. */
16811 gcc_assert (has_target_p && nops == 3); 16891 gcc_assert (has_target_p && nops == 3);
16812 std::swap (ops[1], ops[2]); 16892 std::swap (ops[1], ops[2]);
16813 break; 16893 break;
16814 16894
16895 case CODE_FOR_msa_maddv_b:
16896 case CODE_FOR_msa_maddv_h:
16897 case CODE_FOR_msa_maddv_w:
16898 case CODE_FOR_msa_maddv_d:
16899 case CODE_FOR_msa_fmadd_w:
16900 case CODE_FOR_msa_fmadd_d:
16901 case CODE_FOR_msa_fmsub_w:
16902 case CODE_FOR_msa_fmsub_d:
16903 /* fma(a, b, c) results into (a * b + c), however builtin_msa_fmadd expects
16904 it to be (a + b * c). Swap the 1st and 3rd operands. */
16905 std::swap (ops[1], ops[3]);
16906 break;
16907
16815 case CODE_FOR_msa_slli_b: 16908 case CODE_FOR_msa_slli_b:
16816 case CODE_FOR_msa_slli_h: 16909 case CODE_FOR_msa_slli_h:
16817 case CODE_FOR_msa_slli_w: 16910 case CODE_FOR_msa_slli_w:
16818 case CODE_FOR_msa_slli_d: 16911 case CODE_FOR_msa_slli_d:
16819 case CODE_FOR_msa_srai_b: 16912 case CODE_FOR_msa_srai_b:
16895 case CODE_FOR_msa_vshf_d: 16988 case CODE_FOR_msa_vshf_d:
16896 gcc_assert (has_target_p && nops == 4); 16989 gcc_assert (has_target_p && nops == 4);
16897 std::swap (ops[1], ops[3]); 16990 std::swap (ops[1], ops[3]);
16898 break; 16991 break;
16899 16992
16993 case CODE_FOR_msa_dpadd_s_w:
16994 case CODE_FOR_msa_dpadd_s_h:
16995 case CODE_FOR_msa_dpadd_s_d:
16996 case CODE_FOR_msa_dpadd_u_w:
16997 case CODE_FOR_msa_dpadd_u_h:
16998 case CODE_FOR_msa_dpadd_u_d:
16999 case CODE_FOR_msa_dpsub_s_w:
17000 case CODE_FOR_msa_dpsub_s_h:
17001 case CODE_FOR_msa_dpsub_s_d:
17002 case CODE_FOR_msa_dpsub_u_w:
17003 case CODE_FOR_msa_dpsub_u_h:
17004 case CODE_FOR_msa_dpsub_u_d:
17005 /* Force the operands which correspond to the same in-out register
17006 to have the same pseudo assigned to them. If the input operand
17007 is not REG, create one for it. */
17008 if (!REG_P (ops[1].value))
17009 ops[1].value = copy_to_mode_reg (ops[1].mode, ops[1].value);
17010 create_output_operand (&ops[0], ops[1].value, ops[1].mode);
17011 break;
17012
16900 default: 17013 default:
16901 break; 17014 break;
16902 } 17015 }
16903 17016
16904 if (error_opno != 0) 17017 if (error_opno != 0)
17145 tree fndecl; 17258 tree fndecl;
17146 unsigned int fcode, avail; 17259 unsigned int fcode, avail;
17147 const struct mips_builtin_description *d; 17260 const struct mips_builtin_description *d;
17148 17261
17149 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); 17262 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
17150 fcode = DECL_FUNCTION_CODE (fndecl); 17263 fcode = DECL_MD_FUNCTION_CODE (fndecl);
17151 gcc_assert (fcode < ARRAY_SIZE (mips_builtins)); 17264 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
17152 d = &mips_builtins[fcode]; 17265 d = &mips_builtins[fcode];
17153 avail = d->avail (); 17266 avail = d->avail ();
17154 gcc_assert (avail != 0); 17267 gcc_assert (avail != 0);
17155 if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16)) 17268 if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16))
17722 if (CALL_P (insn)) 17835 if (CALL_P (insn))
17723 return r10k_needs_protection_p_call (PATTERN (insn)); 17836 return r10k_needs_protection_p_call (PATTERN (insn));
17724 17837
17725 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE) 17838 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
17726 { 17839 {
17727 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn); 17840 note_stores (insn, r10k_needs_protection_p_store, &insn);
17728 return insn == NULL_RTX; 17841 return insn == NULL_RTX;
17729 } 17842 }
17730 17843
17731 return r10k_needs_protection_p_1 (PATTERN (insn), insn); 17844 return r10k_needs_protection_p_1 (PATTERN (insn), insn);
17732 } 17845 }
18231 state_transition (curr_state, insn); 18344 state_transition (curr_state, insn);
18232 state->insns_left = targetm.sched.variable_issue (0, false, insn, 18345 state->insns_left = targetm.sched.variable_issue (0, false, insn,
18233 state->insns_left); 18346 state->insns_left);
18234 18347
18235 mips_sim_insn = insn; 18348 mips_sim_insn = insn;
18236 note_stores (PATTERN (insn), mips_sim_record_set, state); 18349 note_stores (insn, mips_sim_record_set, state);
18237 } 18350 }
18238 18351
18239 /* Simulate issuing a NOP in state STATE. */ 18352 /* Simulate issuing a NOP in state STATE. */
18240 18353
18241 static void 18354 static void
18519 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */ 18632 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
18520 length = get_attr_length (insn); 18633 length = get_attr_length (insn);
18521 if (length > 0) 18634 if (length > 0)
18522 { 18635 {
18523 /* If the instruction is an asm statement or multi-instruction 18636 /* If the instruction is an asm statement or multi-instruction
18524 mips.md patern, the length is only an estimate. Insert an 18637 mips.md pattern, the length is only an estimate. Insert an
18525 8 byte alignment after it so that the following instructions 18638 8 byte alignment after it so that the following instructions
18526 can be handled correctly. */ 18639 can be handled correctly. */
18527 if (NONJUMP_INSN_P (SEQ_BEGIN (insn)) 18640 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
18528 && (recog_memoized (insn) < 0 || length >= 8)) 18641 && (recog_memoized (insn) < 0 || length >= 8))
18529 { 18642 {
18879 /* Profiled functions can't be all noreorder because the profiler 18992 /* Profiled functions can't be all noreorder because the profiler
18880 support uses assembler macros. */ 18993 support uses assembler macros. */
18881 if (crtl->profile) 18994 if (crtl->profile)
18882 cfun->machine->all_noreorder_p = false; 18995 cfun->machine->all_noreorder_p = false;
18883 18996
18884 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be 18997 /* Code compiled with -mfix-vr4120, -mfix-r5900, -mfix-rm7000 or
18885 all noreorder because we rely on the assembler to work around some 18998 -mfix-24k can't be all noreorder because we rely on the assembler
18886 errata. The R5900 too has several bugs. */ 18999 to work around some errata. The R5900 target has several bugs. */
18887 if (TARGET_FIX_VR4120 19000 if (TARGET_FIX_VR4120
18888 || TARGET_FIX_RM7000 19001 || TARGET_FIX_RM7000
18889 || TARGET_FIX_24K 19002 || TARGET_FIX_24K
18890 || TARGET_MIPS5900) 19003 || TARGET_FIX_R5900)
18891 cfun->machine->all_noreorder_p = false; 19004 cfun->machine->all_noreorder_p = false;
18892 19005
18893 /* The same is true for -mfix-vr4130 if we might generate MFLO or 19006 /* The same is true for -mfix-vr4130 if we might generate MFLO or
18894 MFHI instructions. Note that we avoid using MFLO and MFHI if 19007 MFHI instructions. Note that we avoid using MFLO and MFHI if
18895 the VR4130 MACC and DMACC instructions are available instead; 19008 the VR4130 MACC and DMACC instructions are available instead;
18961 CLEAR_HARD_REG_SET (uses); 19074 CLEAR_HARD_REG_SET (uses);
18962 note_uses (&PATTERN (SEQ_BEGIN (insn)), record_hard_reg_uses, 19075 note_uses (&PATTERN (SEQ_BEGIN (insn)), record_hard_reg_uses,
18963 &uses); 19076 &uses);
18964 HARD_REG_SET delay_sets; 19077 HARD_REG_SET delay_sets;
18965 CLEAR_HARD_REG_SET (delay_sets); 19078 CLEAR_HARD_REG_SET (delay_sets);
18966 note_stores (PATTERN (SEQ_END (insn)), record_hard_reg_sets, 19079 note_stores (SEQ_END (insn), record_hard_reg_sets,
18967 &delay_sets); 19080 &delay_sets);
18968 19081
18969 rtx_insn *prev = prev_active_insn (insn); 19082 rtx_insn *prev = prev_active_insn (insn);
18970 if (prev 19083 if (prev
18971 && GET_CODE (PATTERN (prev)) == SET 19084 && GET_CODE (PATTERN (prev)) == SET
18972 && MEM_P (SET_SRC (PATTERN (prev)))) 19085 && MEM_P (SET_SRC (PATTERN (prev))))
18973 { 19086 {
18974 HARD_REG_SET sets; 19087 HARD_REG_SET sets;
18975 CLEAR_HARD_REG_SET (sets); 19088 CLEAR_HARD_REG_SET (sets);
18976 note_stores (PATTERN (prev), record_hard_reg_sets, 19089 note_stores (prev, record_hard_reg_sets, &sets);
18977 &sets);
18978 19090
18979 /* Re-order if safe. */ 19091 /* Re-order if safe. */
18980 if (!hard_reg_set_intersect_p (delay_sets, uses) 19092 if (!hard_reg_set_intersect_p (delay_sets, uses)
18981 && hard_reg_set_intersect_p (uses, sets)) 19093 && hard_reg_set_intersect_p (uses, sets))
18982 { 19094 {
19374 static void 19486 static void
19375 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 19487 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
19376 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 19488 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
19377 tree function) 19489 tree function)
19378 { 19490 {
19491 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
19379 rtx this_rtx, temp1, temp2, fnaddr; 19492 rtx this_rtx, temp1, temp2, fnaddr;
19380 rtx_insn *insn; 19493 rtx_insn *insn;
19381 bool use_sibcall_p; 19494 bool use_sibcall_p;
19382 19495
19383 /* Pretend to be a post-reload pass while generating rtl. */ 19496 /* Pretend to be a post-reload pass while generating rtl. */
19486 "borrowed" from alpha.c. */ 19599 "borrowed" from alpha.c. */
19487 insn = get_insns (); 19600 insn = get_insns ();
19488 split_all_insns_noflow (); 19601 split_all_insns_noflow ();
19489 mips16_lay_out_constants (true); 19602 mips16_lay_out_constants (true);
19490 shorten_branches (insn); 19603 shorten_branches (insn);
19604 assemble_start_function (thunk_fndecl, fnname);
19491 final_start_function (insn, file, 1); 19605 final_start_function (insn, file, 1);
19492 final (insn, file, 1); 19606 final (insn, file, 1);
19493 final_end_function (); 19607 final_end_function ();
19608 assemble_end_function (thunk_fndecl, fnname);
19494 19609
19495 /* Clean up the vars set above. Note that final_end_function resets 19610 /* Clean up the vars set above. Note that final_end_function resets
19496 the global pointer for us. */ 19611 the global pointer for us. */
19497 reload_completed = 0; 19612 reload_completed = 0;
19498 } 19613 }
19568 19683
19569 if (flag_pic && !TARGET_OLDABI) 19684 if (flag_pic && !TARGET_OLDABI)
19570 sorry ("MIPS16 PIC for ABIs other than o32 and o64"); 19685 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
19571 19686
19572 if (TARGET_XGOT) 19687 if (TARGET_XGOT)
19573 sorry ("MIPS16 -mxgot code"); 19688 sorry ("MIPS16 %<-mxgot%> code");
19574 19689
19575 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI) 19690 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
19576 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64"); 19691 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
19577 19692
19578 if (TARGET_MSA) 19693 if (TARGET_MSA)
20162 mips_arch_info->name); 20277 mips_arch_info->name);
20163 TARGET_DSP = false; 20278 TARGET_DSP = false;
20164 TARGET_DSPR2 = false; 20279 TARGET_DSPR2 = false;
20165 } 20280 }
20166 20281
20282 /* Make sure that when TARGET_LOONGSON_MMI is true, TARGET_HARD_FLOAT_ABI
20283 is true. In o32 pairs of floating-point registers provide 64-bit
20284 values. */
20285 if (TARGET_LOONGSON_MMI && !TARGET_HARD_FLOAT_ABI)
20286 error ("%<-mloongson-mmi%> must be used with %<-mhard-float%>");
20287
20288 /* If TARGET_LOONGSON_EXT2, enable TARGET_LOONGSON_EXT. */
20289 if (TARGET_LOONGSON_EXT2)
20290 {
20291 /* Make sure that when TARGET_LOONGSON_EXT2 is true, TARGET_LOONGSON_EXT
20292 is true. If a user explicitly says -mloongson-ext2 -mno-loongson-ext
20293 then that is an error. */
20294 if (!TARGET_LOONGSON_EXT
20295 && (target_flags_explicit & MASK_LOONGSON_EXT) != 0)
20296 error ("%<-mloongson-ext2%> must be used with %<-mloongson-ext%>");
20297 target_flags |= MASK_LOONGSON_EXT;
20298 }
20299
20167 /* .eh_frame addresses should be the same width as a C pointer. 20300 /* .eh_frame addresses should be the same width as a C pointer.
20168 Most MIPS ABIs support only one pointer size, so the assembler 20301 Most MIPS ABIs support only one pointer size, so the assembler
20169 will usually know exactly how big an .eh_frame address is. 20302 will usually know exactly how big an .eh_frame address is.
20170 20303
20171 Unfortunately, this is not true of the 64-bit EABI. The ABI was 20304 Unfortunately, this is not true of the 64-bit EABI. The ABI was
20242 was selected explicitly. */ 20375 was selected explicitly. */
20243 if ((target_flags_explicit & MASK_FIX_R4400) == 0 20376 if ((target_flags_explicit & MASK_FIX_R4400) == 0
20244 && strcmp (mips_arch_info->name, "r4400") == 0) 20377 && strcmp (mips_arch_info->name, "r4400") == 0)
20245 target_flags |= MASK_FIX_R4400; 20378 target_flags |= MASK_FIX_R4400;
20246 20379
20380 /* Default to working around R5900 errata only if the processor
20381 was selected explicitly. */
20382 if ((target_flags_explicit & MASK_FIX_R5900) == 0
20383 && strcmp (mips_arch_info->name, "r5900") == 0)
20384 target_flags |= MASK_FIX_R5900;
20385
20247 /* Default to working around R10000 errata only if the processor 20386 /* Default to working around R10000 errata only if the processor
20248 was selected explicitly. */ 20387 was selected explicitly. */
20249 if ((target_flags_explicit & MASK_FIX_R10000) == 0 20388 if ((target_flags_explicit & MASK_FIX_R10000) == 0
20250 && strcmp (mips_arch_info->name, "r10000") == 0) 20389 && strcmp (mips_arch_info->name, "r10000") == 0)
20251 target_flags |= MASK_FIX_R10000; 20390 target_flags |= MASK_FIX_R10000;
20321 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi) 20460 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
20322 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps) 20461 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
20323 20462
20324 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]); 20463 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
20325 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]); 20464 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
20326 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
20327 SWAP_STRING (reg_names[i], reg_names[i + 1]); 20465 SWAP_STRING (reg_names[i], reg_names[i + 1]);
20328 20466
20329 #undef SWAP_STRING 20467 #undef SWAP_STRING
20330 #undef SWAP_INT 20468 #undef SWAP_INT
20331 } 20469 }
20341 /* These DSP control register fields are global. */ 20479 /* These DSP control register fields are global. */
20342 global_regs[CCDSP_PO_REGNUM] = 1; 20480 global_regs[CCDSP_PO_REGNUM] = 1;
20343 global_regs[CCDSP_SC_REGNUM] = 1; 20481 global_regs[CCDSP_SC_REGNUM] = 1;
20344 } 20482 }
20345 else 20483 else
20346 AND_COMPL_HARD_REG_SET (accessible_reg_set, 20484 accessible_reg_set &= ~reg_class_contents[DSP_ACC_REGS];
20347 reg_class_contents[(int) DSP_ACC_REGS]);
20348 20485
20349 if (!ISA_HAS_HILO) 20486 if (!ISA_HAS_HILO)
20350 AND_COMPL_HARD_REG_SET (accessible_reg_set, 20487 accessible_reg_set &= ~reg_class_contents[MD_REGS];
20351 reg_class_contents[(int) MD_REGS]);
20352 20488
20353 if (!TARGET_HARD_FLOAT) 20489 if (!TARGET_HARD_FLOAT)
20354 { 20490 accessible_reg_set &= ~(reg_class_contents[FP_REGS]
20355 AND_COMPL_HARD_REG_SET (accessible_reg_set, 20491 | reg_class_contents[ST_REGS]);
20356 reg_class_contents[(int) FP_REGS]);
20357 AND_COMPL_HARD_REG_SET (accessible_reg_set,
20358 reg_class_contents[(int) ST_REGS]);
20359 }
20360 else if (!ISA_HAS_8CC) 20492 else if (!ISA_HAS_8CC)
20361 { 20493 {
20362 /* We only have a single condition-code register. We implement 20494 /* We only have a single condition-code register. We implement
20363 this by fixing all the condition-code registers and generating 20495 this by fixing all the condition-code registers and generating
20364 RTL that refers directly to ST_REG_FIRST. */ 20496 RTL that refers directly to ST_REG_FIRST. */
20365 AND_COMPL_HARD_REG_SET (accessible_reg_set, 20497 accessible_reg_set &= ~reg_class_contents[ST_REGS];
20366 reg_class_contents[(int) ST_REGS]);
20367 if (!ISA_HAS_CCF) 20498 if (!ISA_HAS_CCF)
20368 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM); 20499 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
20369 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1; 20500 fixed_regs[FPSW_REGNUM] = 1;
20370 } 20501 }
20371 if (TARGET_MIPS16) 20502 if (TARGET_MIPS16)
20372 { 20503 {
20373 /* In MIPS16 mode, we prohibit the unused $s registers, since they 20504 /* In MIPS16 mode, we prohibit the unused $s registers, since they
20374 are call-saved, and saving them via a MIPS16 register would 20505 are call-saved, and saving them via a MIPS16 register would
20379 code that is larger (but faster) then not using them. We do 20510 code that is larger (but faster) then not using them. We do
20380 allow $24 (t8) because it is used in CMP and CMPI instructions 20511 allow $24 (t8) because it is used in CMP and CMPI instructions
20381 and $25 (t9) because it is used as the function call address in 20512 and $25 (t9) because it is used as the function call address in
20382 SVR4 PIC code. */ 20513 SVR4 PIC code. */
20383 20514
20384 fixed_regs[18] = call_used_regs[18] = 1; 20515 fixed_regs[18] = 1;
20385 fixed_regs[19] = call_used_regs[19] = 1; 20516 fixed_regs[19] = 1;
20386 fixed_regs[20] = call_used_regs[20] = 1; 20517 fixed_regs[20] = 1;
20387 fixed_regs[21] = call_used_regs[21] = 1; 20518 fixed_regs[21] = 1;
20388 fixed_regs[22] = call_used_regs[22] = 1; 20519 fixed_regs[22] = 1;
20389 fixed_regs[23] = call_used_regs[23] = 1; 20520 fixed_regs[23] = 1;
20390 fixed_regs[26] = call_used_regs[26] = 1; 20521 fixed_regs[26] = 1;
20391 fixed_regs[27] = call_used_regs[27] = 1; 20522 fixed_regs[27] = 1;
20392 fixed_regs[30] = call_used_regs[30] = 1; 20523 fixed_regs[30] = 1;
20393 if (optimize_size) 20524 if (optimize_size)
20394 { 20525 {
20395 fixed_regs[8] = call_used_regs[8] = 1; 20526 fixed_regs[8] = 1;
20396 fixed_regs[9] = call_used_regs[9] = 1; 20527 fixed_regs[9] = 1;
20397 fixed_regs[10] = call_used_regs[10] = 1; 20528 fixed_regs[10] = 1;
20398 fixed_regs[11] = call_used_regs[11] = 1; 20529 fixed_regs[11] = 1;
20399 fixed_regs[12] = call_used_regs[12] = 1; 20530 fixed_regs[12] = 1;
20400 fixed_regs[13] = call_used_regs[13] = 1; 20531 fixed_regs[13] = 1;
20401 fixed_regs[14] = call_used_regs[14] = 1; 20532 fixed_regs[14] = 1;
20402 fixed_regs[15] = call_used_regs[15] = 1; 20533 fixed_regs[15] = 1;
20403 } 20534 }
20404 20535
20405 /* Do not allow HI and LO to be treated as register operands. 20536 /* Do not allow HI and LO to be treated as register operands.
20406 There are no MTHI or MTLO instructions (or any real need 20537 There are no MTHI or MTLO instructions (or any real need
20407 for them) and one-way registers cannot easily be reloaded. */ 20538 for them) and one-way registers cannot easily be reloaded. */
20408 AND_COMPL_HARD_REG_SET (operand_reg_set, 20539 operand_reg_set &= ~reg_class_contents[MD_REGS];
20409 reg_class_contents[(int) MD_REGS]);
20410 } 20540 }
20411 /* $f20-$f23 are call-clobbered for n64. */ 20541 /* $f20-$f23 are call-clobbered for n64. */
20412 if (mips_abi == ABI_64) 20542 if (mips_abi == ABI_64)
20413 { 20543 {
20414 int regno; 20544 int regno;
20415 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++) 20545 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
20416 call_really_used_regs[regno] = call_used_regs[regno] = 1; 20546 call_used_regs[regno] = 1;
20417 } 20547 }
20418 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered 20548 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
20419 for n32 and o32 FP64. */ 20549 for n32 and o32 FP64. */
20420 if (mips_abi == ABI_N32 20550 if (mips_abi == ABI_N32
20421 || (mips_abi == ABI_32 20551 || (mips_abi == ABI_32
20422 && TARGET_FLOAT64)) 20552 && TARGET_FLOAT64))
20423 { 20553 {
20424 int regno; 20554 int regno;
20425 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2) 20555 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
20426 call_really_used_regs[regno] = call_used_regs[regno] = 1; 20556 call_used_regs[regno] = 1;
20427 } 20557 }
20428 /* Make sure that double-register accumulator values are correctly 20558 /* Make sure that double-register accumulator values are correctly
20429 ordered for the current endianness. */ 20559 ordered for the current endianness. */
20430 if (TARGET_LITTLE_ENDIAN) 20560 if (TARGET_LITTLE_ENDIAN)
20431 { 20561 {
20539 mips_pop_asm_switch (&mips_noat); 20669 mips_pop_asm_switch (&mips_noat);
20540 20670
20541 if (INSN_P (insn) 20671 if (INSN_P (insn)
20542 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE 20672 && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
20543 && XINT (PATTERN (insn), 1) == UNSPEC_CONSTTABLE_END) 20673 && XINT (PATTERN (insn), 1) == UNSPEC_CONSTTABLE_END)
20544 mips_set_text_contents_type (asm_out_file, "__pend_", 20674 {
20545 INTVAL (XVECEXP (PATTERN (insn), 0, 0)), 20675 rtx_insn *next_insn = next_real_nondebug_insn (insn);
20546 TRUE); 20676 bool code_p = (next_insn != NULL
20677 && INSN_P (next_insn)
20678 && (GET_CODE (PATTERN (next_insn)) != UNSPEC_VOLATILE
20679 || XINT (PATTERN (next_insn), 1) != UNSPEC_CONSTTABLE));
20680
20681 /* Switch content type depending on whether there is code beyond
20682 the constant pool. */
20683 mips_set_text_contents_type (asm_out_file, "__pend_",
20684 INTVAL (XVECEXP (PATTERN (insn), 0, 0)),
20685 code_p);
20686 }
20547 } 20687 }
20548 20688
20549 /* Return the function that is used to expand the <u>mulsidi3 pattern. 20689 /* Return the function that is used to expand the <u>mulsidi3 pattern.
20550 EXT_CODE is the code of the extension used. Return NULL if widening 20690 EXT_CODE is the code of the extension used. Return NULL if widening
20551 multiplication shouldn't be used. */ 20691 multiplication shouldn't be used. */
21147 reg_names[2]); 21287 reg_names[2]);
21148 } 21288 }
21149 21289
21150 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default 21290 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
21151 behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even 21291 behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
21152 when TARGET_LOONGSON_VECTORS is true. */ 21292 when TARGET_LOONGSON_MMI is true. */
21153 21293
21154 static unsigned HOST_WIDE_INT 21294 static unsigned HOST_WIDE_INT
21155 mips_shift_truncation_mask (machine_mode mode) 21295 mips_shift_truncation_mask (machine_mode mode)
21156 { 21296 {
21157 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode)) 21297 if (TARGET_LOONGSON_MMI && VECTOR_MODE_P (mode))
21158 return 0; 21298 return 0;
21159 21299
21160 return GET_MODE_BITSIZE (mode) - 1; 21300 return GET_MODE_BITSIZE (mode) - 1;
21161 } 21301 }
21162 21302
21253 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d) 21393 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
21254 { 21394 {
21255 unsigned i, odd, nelt = d->nelt; 21395 unsigned i, odd, nelt = d->nelt;
21256 rtx t0, t1, t2, t3; 21396 rtx t0, t1, t2, t3;
21257 21397
21258 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) 21398 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI))
21259 return false; 21399 return false;
21260 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */ 21400 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
21261 if (nelt < 4) 21401 if (nelt < 4)
21262 return false; 21402 return false;
21263 21403
21310 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d) 21450 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
21311 { 21451 {
21312 unsigned i, mask; 21452 unsigned i, mask;
21313 rtx rmask; 21453 rtx rmask;
21314 21454
21315 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) 21455 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI))
21316 return false; 21456 return false;
21317 if (d->vmode != V4HImode) 21457 if (d->vmode != V4HImode)
21318 return false; 21458 return false;
21319 if (d->testing_p) 21459 if (d->testing_p)
21320 return true; 21460 return true;
21362 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d) 21502 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
21363 { 21503 {
21364 unsigned i, elt; 21504 unsigned i, elt;
21365 rtx t0, t1; 21505 rtx t0, t1;
21366 21506
21367 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS)) 21507 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI))
21368 return false; 21508 return false;
21369 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */ 21509 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
21370 if (d->vmode != V8QImode) 21510 if (d->vmode != V8QImode)
21371 return false; 21511 return false;
21372 if (!d->one_vector_p) 21512 if (!d->one_vector_p)
21956 emit_insn (gen_rtx_SET (target, x)); 22096 emit_insn (gen_rtx_SET (target, x));
21957 return; 22097 return;
21958 } 22098 }
21959 22099
21960 /* Loongson is the only cpu with vectors with more elements. */ 22100 /* Loongson is the only cpu with vectors with more elements. */
21961 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS); 22101 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_MMI);
21962 22102
21963 /* If all values are identical, broadcast the value. */ 22103 /* If all values are identical, broadcast the value. */
21964 if (all_same) 22104 if (all_same)
21965 { 22105 {
21966 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0)); 22106 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
22083 machine_mode mode) 22223 machine_mode mode)
22084 { 22224 {
22085 /* For performance, avoid saving/restoring upper parts of a register 22225 /* For performance, avoid saving/restoring upper parts of a register
22086 by returning MODE as save mode when the mode is known. */ 22226 by returning MODE as save mode when the mode is known. */
22087 if (mode == VOIDmode) 22227 if (mode == VOIDmode)
22088 return choose_hard_reg_mode (regno, nregs, false); 22228 return choose_hard_reg_mode (regno, nregs, NULL);
22089 else 22229 else
22090 return mode; 22230 return mode;
22091 } 22231 }
22092 22232
22093 /* Generate RTL for comparing CMP_OP0 and CMP_OP1 using condition COND and 22233 /* Generate RTL for comparing CMP_OP0 and CMP_OP1 using condition COND and
22211 { 22351 {
22212 rtx xop1 = operands[1]; 22352 rtx xop1 = operands[1];
22213 if (mode != vimode) 22353 if (mode != vimode)
22214 { 22354 {
22215 xop1 = gen_reg_rtx (vimode); 22355 xop1 = gen_reg_rtx (vimode);
22216 emit_move_insn (xop1, gen_rtx_SUBREG (vimode, operands[1], 0)); 22356 emit_move_insn (xop1, gen_lowpart (vimode, operands[1]));
22217 } 22357 }
22218 emit_move_insn (src1, xop1); 22358 emit_move_insn (src1, xop1);
22219 } 22359 }
22220 else 22360 else
22221 { 22361 {
22228 { 22368 {
22229 rtx xop2 = operands[2]; 22369 rtx xop2 = operands[2];
22230 if (mode != vimode) 22370 if (mode != vimode)
22231 { 22371 {
22232 xop2 = gen_reg_rtx (vimode); 22372 xop2 = gen_reg_rtx (vimode);
22233 emit_move_insn (xop2, gen_rtx_SUBREG (vimode, operands[2], 0)); 22373 emit_move_insn (xop2, gen_lowpart (vimode, operands[2]));
22234 } 22374 }
22235 emit_move_insn (src2, xop2); 22375 emit_move_insn (src2, xop2);
22236 } 22376 }
22237 else 22377 else
22238 { 22378 {
22414 mips_starting_frame_offset (void) 22554 mips_starting_frame_offset (void)
22415 { 22555 {
22416 if (FRAME_GROWS_DOWNWARD) 22556 if (FRAME_GROWS_DOWNWARD)
22417 return 0; 22557 return 0;
22418 return crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE; 22558 return crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE;
22559 }
22560
22561 static void
22562 mips_asm_file_end (void)
22563 {
22564 if (NEED_INDICATE_EXEC_STACK)
22565 file_end_indicate_exec_stack ();
22419 } 22566 }
22420 22567
22421 /* Initialize the GCC target structure. */ 22568 /* Initialize the GCC target structure. */
22422 #undef TARGET_ASM_ALIGNED_HI_OP 22569 #undef TARGET_ASM_ALIGNED_HI_OP
22423 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 22570 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
22582 #undef TARGET_SCALAR_MODE_SUPPORTED_P 22729 #undef TARGET_SCALAR_MODE_SUPPORTED_P
22583 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p 22730 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
22584 22731
22585 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE 22732 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
22586 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode 22733 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
22587 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES 22734 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES
22588 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \ 22735 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES \
22589 mips_autovectorize_vector_sizes 22736 mips_autovectorize_vector_modes
22590 22737
22591 #undef TARGET_INIT_BUILTINS 22738 #undef TARGET_INIT_BUILTINS
22592 #define TARGET_INIT_BUILTINS mips_init_builtins 22739 #define TARGET_INIT_BUILTINS mips_init_builtins
22593 #undef TARGET_BUILTIN_DECL 22740 #undef TARGET_BUILTIN_DECL
22594 #define TARGET_BUILTIN_DECL mips_builtin_decl 22741 #define TARGET_BUILTIN_DECL mips_builtin_decl
22722 #define TARGET_ASAN_SHADOW_OFFSET mips_asan_shadow_offset 22869 #define TARGET_ASAN_SHADOW_OFFSET mips_asan_shadow_offset
22723 22870
22724 #undef TARGET_STARTING_FRAME_OFFSET 22871 #undef TARGET_STARTING_FRAME_OFFSET
22725 #define TARGET_STARTING_FRAME_OFFSET mips_starting_frame_offset 22872 #define TARGET_STARTING_FRAME_OFFSET mips_starting_frame_offset
22726 22873
22874 #undef TARGET_ASM_FILE_END
22875 #define TARGET_ASM_FILE_END mips_asm_file_end
22876
22877
22727 struct gcc_target targetm = TARGET_INITIALIZER; 22878 struct gcc_target targetm = TARGET_INITIALIZER;
22728 22879
22729 #include "gt-mips.h" 22880 #include "gt-mips.h"