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comparison gcc/config/mips/sb1.md @ 145:1830386684a0

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gcc-9.2.0
author anatofuz
date Thu, 13 Feb 2020 11:34:05 +0900
parents 84e7813d76e9
children
comparison
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131:84e7813d76e9 145:1830386684a0
1 ;; Copyright (C) 2004-2018 Free Software Foundation, Inc. 1 ;; Copyright (C) 2004-2020 Free Software Foundation, Inc.
2 ;; 2 ;;
3 ;; This file is part of GCC. 3 ;; This file is part of GCC.
4 ;; 4 ;;
5 ;; GCC is free software; you can redistribute it and/or modify 5 ;; GCC is free software; you can redistribute it and/or modify
6 ;; it under the terms of the GNU General Public License as published by 6 ;; it under the terms of the GNU General Public License as published by
125 125
126 ;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data 126 ;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data
127 ;; register as destination. 127 ;; register as destination.
128 128
129 ;; ??? SB-1 can co-issue a load with a dependent arith insn if it executes on 129 ;; ??? SB-1 can co-issue a load with a dependent arith insn if it executes on
130 ;; an EX unit. Can not co-issue if the dependent insn executes on an LS unit. 130 ;; an EX unit. Cannot co-issue if the dependent insn executes on an LS unit.
131 ;; SB-1A can always co-issue here. 131 ;; SB-1A can always co-issue here.
132 132
133 ;; A load normally has a latency of zero cycles. In some cases, dependent 133 ;; A load normally has a latency of zero cycles. In some cases, dependent
134 ;; insns can be issued in the same cycle. However, a value of 1 gives 134 ;; insns can be issued in the same cycle. However, a value of 1 gives
135 ;; better performance in empirical testing. 135 ;; better performance in empirical testing.
142 (define_insn_reservation "ir_sb1a_load" 0 142 (define_insn_reservation "ir_sb1a_load" 0
143 (and (eq_attr "cpu" "sb1a") 143 (and (eq_attr "cpu" "sb1a")
144 (eq_attr "type" "load,prefetch")) 144 (eq_attr "type" "load,prefetch"))
145 "sb1_ls0 | sb1_ls1") 145 "sb1_ls0 | sb1_ls1")
146 146
147 ;; Can not co-issue fpload with fp exe when in 32-bit mode. 147 ;; Cannot co-issue fpload with fp exe when in 32-bit mode.
148 148
149 (define_insn_reservation "ir_sb1_fpload" 0 149 (define_insn_reservation "ir_sb1_fpload" 0
150 (and (eq_attr "cpu" "sb1,sb1a") 150 (and (eq_attr "cpu" "sb1,sb1a")
151 (and (eq_attr "type" "fpload") 151 (and (eq_attr "type" "fpload")
152 (match_test "TARGET_FLOAT64"))) 152 (match_test "TARGET_FLOAT64")))
250 (define_insn_reservation "ir_sb1_simple_alu" 2 250 (define_insn_reservation "ir_sb1_simple_alu" 2
251 (and (eq_attr "cpu" "sb1") 251 (and (eq_attr "cpu" "sb1")
252 (eq_attr "type" "const,arith,logical,move,signext")) 252 (eq_attr "type" "const,arith,logical,move,signext"))
253 "sb1_ls1 | sb1_ex1 | sb1_ex0") 253 "sb1_ls1 | sb1_ex1 | sb1_ex0")
254 254
255 ;; On SB-1A, simple alu instructions can not execute on the LS1 unit, and we 255 ;; On SB-1A, simple alu instructions cannot execute on the LS1 unit, and we
256 ;; have none of the above problems. 256 ;; have none of the above problems.
257 257
258 (define_insn_reservation "ir_sb1a_simple_alu" 1 258 (define_insn_reservation "ir_sb1a_simple_alu" 1
259 (and (eq_attr "cpu" "sb1a") 259 (and (eq_attr "cpu" "sb1a")
260 (eq_attr "type" "const,arith,logical,move,signext")) 260 (eq_attr "type" "const,arith,logical,move,signext"))