Mercurial > hg > CbC > CbC_gcc
comparison gcc/config/rs6000/dfp.md @ 145:1830386684a0
gcc-9.2.0
author | anatofuz |
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date | Thu, 13 Feb 2020 11:34:05 +0900 |
parents | 84e7813d76e9 |
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131:84e7813d76e9 | 145:1830386684a0 |
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1 ;; Decimal Floating Point (DFP) patterns. | 1 ;; Decimal Floating Point (DFP) patterns. |
2 ;; Copyright (C) 2007-2018 Free Software Foundation, Inc. | 2 ;; Copyright (C) 2007-2020 Free Software Foundation, Inc. |
3 ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner | 3 ;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner |
4 ;; (bergner@vnet.ibm.com). | 4 ;; (bergner@vnet.ibm.com). |
5 | 5 |
6 ;; This file is part of GCC. | 6 ;; This file is part of GCC. |
7 | 7 |
25 | 25 |
26 (define_c_enum "unspec" | 26 (define_c_enum "unspec" |
27 [UNSPEC_MOVSD_LOAD | 27 [UNSPEC_MOVSD_LOAD |
28 UNSPEC_MOVSD_STORE | 28 UNSPEC_MOVSD_STORE |
29 ]) | 29 ]) |
30 | |
31 ; Either of the two decimal modes. | |
32 (define_mode_iterator DDTD [DD TD]) | |
33 | |
34 (define_mode_attr q [(DD "") (TD "q")]) | |
30 | 35 |
31 | 36 |
32 (define_insn "movsd_store" | 37 (define_insn "movsd_store" |
33 [(set (match_operand:DD 0 "nonimmediate_operand" "=m") | 38 [(set (match_operand:DD 0 "nonimmediate_operand" "=m") |
34 (unspec:DD [(match_operand:SD 1 "input_operand" "d")] | 39 (unspec:DD [(match_operand:SD 1 "input_operand" "d")] |
148 "TARGET_DFP" | 153 "TARGET_DFP" |
149 "drdpq %2,%1\;fmr %0,%2" | 154 "drdpq %2,%1\;fmr %0,%2" |
150 [(set_attr "type" "dfp") | 155 [(set_attr "type" "dfp") |
151 (set_attr "length" "8")]) | 156 (set_attr "length" "8")]) |
152 | 157 |
153 (define_insn "adddd3" | 158 (define_insn "add<mode>3" |
154 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") | 159 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") |
155 (plus:DD (match_operand:DD 1 "gpc_reg_operand" "%d") | 160 (plus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d") |
156 (match_operand:DD 2 "gpc_reg_operand" "d")))] | 161 (match_operand:DDTD 2 "gpc_reg_operand" "d")))] |
157 "TARGET_DFP" | 162 "TARGET_DFP" |
158 "dadd %0,%1,%2" | 163 "dadd<q> %0,%1,%2" |
159 [(set_attr "type" "dfp")]) | 164 [(set_attr "type" "dfp")]) |
160 | 165 |
161 (define_insn "addtd3" | 166 (define_insn "sub<mode>3" |
162 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") | 167 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") |
163 (plus:TD (match_operand:TD 1 "gpc_reg_operand" "%d") | 168 (minus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d") |
164 (match_operand:TD 2 "gpc_reg_operand" "d")))] | 169 (match_operand:DDTD 2 "gpc_reg_operand" "d")))] |
165 "TARGET_DFP" | 170 "TARGET_DFP" |
166 "daddq %0,%1,%2" | 171 "dsub<q> %0,%1,%2" |
167 [(set_attr "type" "dfp")]) | 172 [(set_attr "type" "dfp")]) |
168 | 173 |
169 (define_insn "subdd3" | 174 (define_insn "mul<mode>3" |
170 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") | 175 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") |
171 (minus:DD (match_operand:DD 1 "gpc_reg_operand" "d") | 176 (mult:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d") |
172 (match_operand:DD 2 "gpc_reg_operand" "d")))] | 177 (match_operand:DDTD 2 "gpc_reg_operand" "d")))] |
173 "TARGET_DFP" | 178 "TARGET_DFP" |
174 "dsub %0,%1,%2" | 179 "dmul<q> %0,%1,%2" |
175 [(set_attr "type" "dfp")]) | 180 [(set_attr "type" "dfp")]) |
176 | 181 |
177 (define_insn "subtd3" | 182 (define_insn "div<mode>3" |
178 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") | 183 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") |
179 (minus:TD (match_operand:TD 1 "gpc_reg_operand" "d") | 184 (div:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d") |
180 (match_operand:TD 2 "gpc_reg_operand" "d")))] | 185 (match_operand:DDTD 2 "gpc_reg_operand" "d")))] |
181 "TARGET_DFP" | 186 "TARGET_DFP" |
182 "dsubq %0,%1,%2" | 187 "ddiv<q> %0,%1,%2" |
183 [(set_attr "type" "dfp")]) | 188 [(set_attr "type" "dfp")]) |
184 | 189 |
185 (define_insn "muldd3" | 190 (define_insn "*cmp<mode>_internal1" |
186 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") | |
187 (mult:DD (match_operand:DD 1 "gpc_reg_operand" "%d") | |
188 (match_operand:DD 2 "gpc_reg_operand" "d")))] | |
189 "TARGET_DFP" | |
190 "dmul %0,%1,%2" | |
191 [(set_attr "type" "dfp")]) | |
192 | |
193 (define_insn "multd3" | |
194 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") | |
195 (mult:TD (match_operand:TD 1 "gpc_reg_operand" "%d") | |
196 (match_operand:TD 2 "gpc_reg_operand" "d")))] | |
197 "TARGET_DFP" | |
198 "dmulq %0,%1,%2" | |
199 [(set_attr "type" "dfp")]) | |
200 | |
201 (define_insn "divdd3" | |
202 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") | |
203 (div:DD (match_operand:DD 1 "gpc_reg_operand" "d") | |
204 (match_operand:DD 2 "gpc_reg_operand" "d")))] | |
205 "TARGET_DFP" | |
206 "ddiv %0,%1,%2" | |
207 [(set_attr "type" "dfp")]) | |
208 | |
209 (define_insn "divtd3" | |
210 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") | |
211 (div:TD (match_operand:TD 1 "gpc_reg_operand" "d") | |
212 (match_operand:TD 2 "gpc_reg_operand" "d")))] | |
213 "TARGET_DFP" | |
214 "ddivq %0,%1,%2" | |
215 [(set_attr "type" "dfp")]) | |
216 | |
217 (define_insn "*cmpdd_internal1" | |
218 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | 191 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
219 (compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "d") | 192 (compare:CCFP (match_operand:DDTD 1 "gpc_reg_operand" "d") |
220 (match_operand:DD 2 "gpc_reg_operand" "d")))] | 193 (match_operand:DDTD 2 "gpc_reg_operand" "d")))] |
221 "TARGET_DFP" | 194 "TARGET_DFP" |
222 "dcmpu %0,%1,%2" | 195 "dcmpu<q> %0,%1,%2" |
223 [(set_attr "type" "dfp")]) | |
224 | |
225 (define_insn "*cmptd_internal1" | |
226 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
227 (compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "d") | |
228 (match_operand:TD 2 "gpc_reg_operand" "d")))] | |
229 "TARGET_DFP" | |
230 "dcmpuq %0,%1,%2" | |
231 [(set_attr "type" "dfp")]) | 196 [(set_attr "type" "dfp")]) |
232 | 197 |
233 (define_insn "floatdidd2" | 198 (define_insn "floatdidd2" |
234 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") | 199 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") |
235 (float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))] | 200 (float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))] |
242 (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))] | 207 (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))] |
243 "TARGET_DFP" | 208 "TARGET_DFP" |
244 "dcffixq %0,%1" | 209 "dcffixq %0,%1" |
245 [(set_attr "type" "dfp")]) | 210 [(set_attr "type" "dfp")]) |
246 | 211 |
247 ;; Convert a decimal64 to a decimal64 whose value is an integer. | 212 ;; Convert a decimal64/128 to a decimal64/128 whose value is an integer. |
248 ;; This is the first stage of converting it to an integer type. | 213 ;; This is the first stage of converting it to an integer type. |
249 | 214 |
250 (define_insn "ftruncdd2" | 215 (define_insn "ftrunc<mode>2" |
251 [(set (match_operand:DD 0 "gpc_reg_operand" "=d") | 216 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") |
252 (fix:DD (match_operand:DD 1 "gpc_reg_operand" "d")))] | 217 (fix:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")))] |
253 "TARGET_DFP" | 218 "TARGET_DFP" |
254 "drintn. 0,%0,%1,1" | 219 "drintn<q>. 0,%0,%1,1" |
255 [(set_attr "type" "dfp")]) | 220 [(set_attr "type" "dfp")]) |
256 | 221 |
257 ;; Convert a decimal64 whose value is an integer to an actual integer. | 222 ;; Convert a decimal64/128 whose value is an integer to an actual integer. |
258 ;; This is the second stage of converting decimal float to integer type. | 223 ;; This is the second stage of converting decimal float to integer type. |
259 | 224 |
260 (define_insn "fixdddi2" | 225 (define_insn "fix<mode>di2" |
261 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") | 226 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") |
262 (fix:DI (match_operand:DD 1 "gpc_reg_operand" "d")))] | 227 (fix:DI (match_operand:DDTD 1 "gpc_reg_operand" "d")))] |
263 "TARGET_DFP" | 228 "TARGET_DFP" |
264 "dctfix %0,%1" | 229 "dctfix<q> %0,%1" |
265 [(set_attr "type" "dfp")]) | 230 [(set_attr "type" "dfp")]) |
266 | |
267 ;; Convert a decimal128 to a decimal128 whose value is an integer. | |
268 ;; This is the first stage of converting it to an integer type. | |
269 | |
270 (define_insn "ftrunctd2" | |
271 [(set (match_operand:TD 0 "gpc_reg_operand" "=d") | |
272 (fix:TD (match_operand:TD 1 "gpc_reg_operand" "d")))] | |
273 "TARGET_DFP" | |
274 "drintnq. 0,%0,%1,1" | |
275 [(set_attr "type" "dfp")]) | |
276 | |
277 ;; Convert a decimal128 whose value is an integer to an actual integer. | |
278 ;; This is the second stage of converting decimal float to integer type. | |
279 | |
280 (define_insn "fixtddi2" | |
281 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") | |
282 (fix:DI (match_operand:TD 1 "gpc_reg_operand" "d")))] | |
283 "TARGET_DFP" | |
284 "dctfixq %0,%1" | |
285 [(set_attr "type" "dfp")]) | |
286 | |
287 | 231 |
288 ;; Decimal builtin support | 232 ;; Decimal builtin support |
289 | 233 |
290 (define_c_enum "unspec" | 234 (define_c_enum "unspec" |
291 [UNSPEC_DDEDPD | 235 [UNSPEC_DDEDPD |
296 UNSPEC_DTSTSFI | 240 UNSPEC_DTSTSFI |
297 UNSPEC_DSCRI]) | 241 UNSPEC_DSCRI]) |
298 | 242 |
299 (define_code_iterator DFP_TEST [eq lt gt unordered]) | 243 (define_code_iterator DFP_TEST [eq lt gt unordered]) |
300 | 244 |
301 (define_mode_iterator D64_D128 [DD TD]) | |
302 | |
303 (define_mode_attr dfp_suffix [(DD "") | |
304 (TD "q")]) | |
305 | |
306 (define_insn "dfp_ddedpd_<mode>" | 245 (define_insn "dfp_ddedpd_<mode>" |
307 [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") | 246 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") |
308 (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_3_operand" "i") | 247 (unspec:DDTD [(match_operand:QI 1 "const_0_to_3_operand" "i") |
309 (match_operand:D64_D128 2 "gpc_reg_operand" "d")] | 248 (match_operand:DDTD 2 "gpc_reg_operand" "d")] |
310 UNSPEC_DDEDPD))] | 249 UNSPEC_DDEDPD))] |
311 "TARGET_DFP" | 250 "TARGET_DFP" |
312 "ddedpd<dfp_suffix> %1,%0,%2" | 251 "ddedpd<q> %1,%0,%2" |
313 [(set_attr "type" "dfp")]) | 252 [(set_attr "type" "dfp")]) |
314 | 253 |
315 (define_insn "dfp_denbcd_<mode>" | 254 (define_insn "dfp_denbcd_<mode>" |
316 [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") | 255 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") |
317 (unspec:D64_D128 [(match_operand:QI 1 "const_0_to_1_operand" "i") | 256 (unspec:DDTD [(match_operand:QI 1 "const_0_to_1_operand" "i") |
318 (match_operand:D64_D128 2 "gpc_reg_operand" "d")] | 257 (match_operand:DDTD 2 "gpc_reg_operand" "d")] |
319 UNSPEC_DENBCD))] | 258 UNSPEC_DENBCD))] |
320 "TARGET_DFP" | 259 "TARGET_DFP" |
321 "denbcd<dfp_suffix> %1,%0,%2" | 260 "denbcd<q> %1,%0,%2" |
322 [(set_attr "type" "dfp")]) | 261 [(set_attr "type" "dfp")]) |
323 | 262 |
324 (define_insn "dfp_dxex_<mode>" | 263 (define_insn "dfp_dxex_<mode>" |
325 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") | 264 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") |
326 (unspec:DI [(match_operand:D64_D128 1 "gpc_reg_operand" "d")] | 265 (unspec:DI [(match_operand:DDTD 1 "gpc_reg_operand" "d")] |
327 UNSPEC_DXEX))] | 266 UNSPEC_DXEX))] |
328 "TARGET_DFP" | 267 "TARGET_DFP" |
329 "dxex<dfp_suffix> %0,%1" | 268 "dxex<q> %0,%1" |
330 [(set_attr "type" "dfp")]) | 269 [(set_attr "type" "dfp")]) |
331 | 270 |
332 (define_insn "dfp_diex_<mode>" | 271 (define_insn "dfp_diex_<mode>" |
333 [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") | 272 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") |
334 (unspec:D64_D128 [(match_operand:DI 1 "gpc_reg_operand" "d") | 273 (unspec:DDTD [(match_operand:DI 1 "gpc_reg_operand" "d") |
335 (match_operand:D64_D128 2 "gpc_reg_operand" "d")] | 274 (match_operand:DDTD 2 "gpc_reg_operand" "d")] |
336 UNSPEC_DXEX))] | 275 UNSPEC_DXEX))] |
337 "TARGET_DFP" | 276 "TARGET_DFP" |
338 "diex<dfp_suffix> %0,%1,%2" | 277 "diex<q> %0,%1,%2" |
339 [(set_attr "type" "dfp")]) | 278 [(set_attr "type" "dfp")]) |
340 | 279 |
341 (define_expand "dfptstsfi_<code>_<mode>" | 280 (define_expand "dfptstsfi_<code>_<mode>" |
342 [(set (match_dup 3) | 281 [(set (match_dup 3) |
343 (compare:CCFP | 282 (compare:CCFP (unspec:DDTD [(match_operand:SI 1 "const_int_operand") |
344 (unspec:D64_D128 | 283 (match_operand:DDTD 2 "gpc_reg_operand")] |
345 [(match_operand:SI 1 "const_int_operand") | 284 UNSPEC_DTSTSFI) |
346 (match_operand:D64_D128 2 "gpc_reg_operand")] | 285 (const_int 0))) |
347 UNSPEC_DTSTSFI) | |
348 (match_dup 4))) | |
349 (set (match_operand:SI 0 "register_operand") | 286 (set (match_operand:SI 0 "register_operand") |
350 (DFP_TEST:SI (match_dup 3) | 287 (DFP_TEST:SI (match_dup 3) |
351 (const_int 0))) | 288 (const_int 0))) |
352 ] | 289 ] |
353 "TARGET_P9_MISC" | 290 "TARGET_P9_MISC" |
354 { | 291 { |
292 if (<CODE> == UNORDERED && !HONOR_NANS (<MODE>mode)) | |
293 { | |
294 emit_move_insn (operands[0], const0_rtx); | |
295 DONE; | |
296 } | |
297 | |
355 operands[3] = gen_reg_rtx (CCFPmode); | 298 operands[3] = gen_reg_rtx (CCFPmode); |
356 operands[4] = const0_rtx; | |
357 }) | 299 }) |
358 | 300 |
359 (define_insn "*dfp_sgnfcnc_<mode>" | 301 (define_insn "*dfp_sgnfcnc_<mode>" |
360 [(set (match_operand:CCFP 0 "" "=y") | 302 [(set (match_operand:CCFP 0 "" "=y") |
361 (compare:CCFP | 303 (compare:CCFP |
362 (unspec:D64_D128 [(match_operand:SI 1 "const_int_operand" "n") | 304 (unspec:DDTD [(match_operand:SI 1 "const_int_operand" "n") |
363 (match_operand:D64_D128 2 "gpc_reg_operand" "d")] | 305 (match_operand:DDTD 2 "gpc_reg_operand" "d")] |
364 UNSPEC_DTSTSFI) | 306 UNSPEC_DTSTSFI) |
365 (match_operand:SI 3 "zero_constant" "j")))] | 307 (match_operand:SI 3 "zero_constant" "j")))] |
366 "TARGET_P9_MISC" | 308 "TARGET_P9_MISC" |
367 { | 309 { |
368 /* If immediate operand is greater than 63, it will behave as if | 310 /* If immediate operand is greater than 63, it will behave as if |
369 the value had been 63. The code generator does not support | 311 the value had been 63. The code generator does not support |
370 immediate operand values greater than 63. */ | 312 immediate operand values greater than 63. */ |
371 if (!(IN_RANGE (INTVAL (operands[1]), 0, 63))) | 313 if (!(IN_RANGE (INTVAL (operands[1]), 0, 63))) |
372 operands[1] = GEN_INT (63); | 314 operands[1] = GEN_INT (63); |
373 return "dtstsfi<dfp_suffix> %0,%1,%2"; | 315 return "dtstsfi<q> %0,%1,%2"; |
374 } | 316 } |
375 [(set_attr "type" "fp")]) | 317 [(set_attr "type" "fp")]) |
376 | 318 |
377 (define_insn "dfp_dscli_<mode>" | 319 (define_insn "dfp_dscli_<mode>" |
378 [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") | 320 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") |
379 (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") | 321 (unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d") |
380 (match_operand:QI 2 "immediate_operand" "i")] | 322 (match_operand:QI 2 "immediate_operand" "i")] |
381 UNSPEC_DSCLI))] | 323 UNSPEC_DSCLI))] |
382 "TARGET_DFP" | 324 "TARGET_DFP" |
383 "dscli<dfp_suffix> %0,%1,%2" | 325 "dscli<q> %0,%1,%2" |
384 [(set_attr "type" "dfp")]) | 326 [(set_attr "type" "dfp")]) |
385 | 327 |
386 (define_insn "dfp_dscri_<mode>" | 328 (define_insn "dfp_dscri_<mode>" |
387 [(set (match_operand:D64_D128 0 "gpc_reg_operand" "=d") | 329 [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") |
388 (unspec:D64_D128 [(match_operand:D64_D128 1 "gpc_reg_operand" "d") | 330 (unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d") |
389 (match_operand:QI 2 "immediate_operand" "i")] | 331 (match_operand:QI 2 "immediate_operand" "i")] |
390 UNSPEC_DSCRI))] | 332 UNSPEC_DSCRI))] |
391 "TARGET_DFP" | 333 "TARGET_DFP" |
392 "dscri<dfp_suffix> %0,%1,%2" | 334 "dscri<q> %0,%1,%2" |
393 [(set_attr "type" "dfp")]) | 335 [(set_attr "type" "dfp")]) |