Mercurial > hg > CbC > CbC_gcc

comparison gcc/config/h8300/movepush.md @ 152:2b5abeee2509

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
update gcc11
author anatofuz
date Mon, 25 May 2020 07:50:57 +0900
parents
children
comparison
equal deleted inserted replaced
145:1830386684a0 152:2b5abeee2509
1 ;; ----------------------------------------------------------------------
2 ;; MOVE INSTRUCTIONS
3 ;; ----------------------------------------------------------------------
4
5 ;; movqi
6
7 (define_insn "*movqi_h8nosx"
8 [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
9 (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
10 "!TARGET_H8300SX
11 && h8300_move_ok (operands[0], operands[1])"
12 "@
13 sub.b %X0,%X0
14 mov.b %R1,%X0
15 mov.b %X1,%R0
16 mov.b %R1,%X0
17 mov.b %R1,%X0
18 mov.b %X1,%R0"
19 [(set (attr "length")
20 (symbol_ref "compute_mov_length (operands)"))
21 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
22
23 (define_insn "*movqi_h8sx"
24 [(set (match_operand:QI 0 "general_operand_dst" "=Z,rQ")
25 (match_operand:QI 1 "general_operand_src" "P4>X,rQi"))]
26 "TARGET_H8300SX"
27 "@
28 mov.b %X1:4,%X0
29 mov.b %X1,%X0"
30 [(set_attr "length_table" "mov_imm4,movb")
31 (set_attr "cc" "set_znv")])
32
33 (define_expand "mov<mode>"
34 [(set (match_operand:QHSIF 0 "general_operand_dst" "")
35 (match_operand:QHSIF 1 "general_operand_src" ""))]
36 ""
37 {
38 enum machine_mode mode = <MODE>mode;
39 if (!TARGET_H8300SX)
40 {
41 /* Other H8 chips, except the H8/SX family can only handle a
42 single memory operand, which is checked by h8300_move_ok.
43
44 We could perhaps have h8300_move_ok handle the H8/SX better
45 and just remove the !TARGET_H8300SX conditional. */
46 if (!h8300_move_ok (operands[0], operands[1]))
47 operands[1] = copy_to_mode_reg (mode, operand1);
48 }
49 })
50
51 (define_insn "movstrictqi"
52 [(set (strict_low_part (match_operand:QI 0 "general_operand_dst" "+r,r"))
53 (match_operand:QI 1 "general_operand_src" "I,rmi>"))]
54 ""
55 "@
56 sub.b %X0,%X0
57 mov.b %X1,%X0"
58 [(set_attr "length" "2,*")
59 (set_attr "length_table" "*,movb")
60 (set_attr "cc" "set_zn,set_znv")])
61
62 ;; movhi
63
64 (define_insn "*movhi_h8nosx"
65 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
66 (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
67 "!TARGET_H8300SX
68 && h8300_move_ok (operands[0], operands[1])"
69 "@
70 sub.w %T0,%T0
71 mov.w %T1,%T0
72 mov.w %T1,%T0
73 mov.w %T1,%T0
74 mov.w %T1,%T0
75 mov.w %T1,%T0"
76 [(set (attr "length")
77 (symbol_ref "compute_mov_length (operands)"))
78 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
79
80 (define_insn "*movhi_h8sx"
81 [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Z,Q,rQ")
82 (match_operand:HI 1 "general_operand_src" "I,P3>X,P4>X,IP8>X,rQi"))]
83 "TARGET_H8300SX"
84 "@
85 sub.w %T0,%T0
86 mov.w %T1:3,%T0
87 mov.w %T1:4,%T0
88 mov.w %T1,%T0
89 mov.w %T1,%T0"
90 [(set_attr "length_table" "*,*,mov_imm4,short_immediate,movw")
91 (set_attr "length" "2,2,*,*,*")
92 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv")])
93
94 (define_insn "movstricthi"
95 [(set (strict_low_part (match_operand:HI 0 "general_operand_dst" "+r,r,r"))
96 (match_operand:HI 1 "general_operand_src" "I,P3>X,rmi"))]
97 ""
98 "@
99 sub.w %T0,%T0
100 mov.w %T1,%T0
101 mov.w %T1,%T0"
102 [(set_attr "length" "2,2,*")
103 (set_attr "length_table" "*,*,movw")
104 (set_attr "cc" "set_zn,set_znv,set_znv")])
105
106 ;; movsi
107 (define_insn "*movsi_h8300hs"
108 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
109 (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
110 "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
111 && h8300_move_ok (operands[0], operands[1])"
112 {
113 switch (which_alternative)
114 {
115 case 0:
116 return "sub.l %S0,%S0";
117 case 7:
118 return "clrmac";
119 case 8:
120 return "clrmac\;ldmac %1,macl";
121 case 9:
122 return "stmac macl,%0";
123 default:
124 if (GET_CODE (operands[1]) == CONST_INT)
125 {
126 int val = INTVAL (operands[1]);
127
128 /* Look for constants which can be made by adding an 8-bit
129 number to zero in one of the two low bytes. */
130 if (val == (val & 0xff))
131 {
132 operands[1] = GEN_INT ((char) val & 0xff);
133 return "sub.l\\t%S0,%S0\;add.b\\t%1,%w0";
134 }
135
136 if (val == (val & 0xff00))
137 {
138 operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
139 return "sub.l\\t%S0,%S0\;add.b\\t%1,%x0";
140 }
141
142 /* Look for constants that can be obtained by subs, inc, and
143 dec to 0. */
144 switch (val & 0xffffffff)
145 {
146 case 0xffffffff:
147 return "sub.l\\t%S0,%S0\;subs\\t#1,%S0";
148 case 0xfffffffe:
149 return "sub.l\\t%S0,%S0\;subs\\t#2,%S0";
150 case 0xfffffffc:
151 return "sub.l\\t%S0,%S0\;subs\\t#4,%S0";
152
153 case 0x0000ffff:
154 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%f0";
155 case 0x0000fffe:
156 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%f0";
157
158 case 0xffff0000:
159 return "sub.l\\t%S0,%S0\;dec.w\\t#1,%e0";
160 case 0xfffe0000:
161 return "sub.l\\t%S0,%S0\;dec.w\\t#2,%e0";
162
163 case 0x00010000:
164 return "sub.l\\t%S0,%S0\;inc.w\\t#1,%e0";
165 case 0x00020000:
166 return "sub.l\\t%S0,%S0\;inc.w\\t#2,%e0";
167 }
168 }
169 }
170 return "mov.l %S1,%S0";
171 }
172 [(set (attr "length")
173 (symbol_ref "compute_mov_length (operands)"))
174 (set_attr "cc" "set_zn,set_znv,clobber,set_znv,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
175
176 (define_insn "*movsi_h8sx"
177 [(set (match_operand:SI 0 "general_operand_dst" "=r,r,Q,rQ,*a,*a,r")
178 (match_operand:SI 1 "general_operand_src" "I,P3>X,IP8>X,rQi,I,r,*a"))]
179 "TARGET_H8300SX"
180 "@
181 sub.l %S0,%S0
182 mov.l %S1:3,%S0
183 mov.l %S1,%S0
184 mov.l %S1,%S0
185 clrmac
186 clrmac\;ldmac %1,macl
187 stmac macl,%0"
188 [(set_attr "length_table" "*,*,short_immediate,movl,*,*,*")
189 (set_attr "length" "2,2,*,*,2,6,4")
190 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,none_0hit,none_0hit,set_znv")])
191
192 (define_insn "*movsf_h8sx"
193 [(set (match_operand:SF 0 "general_operand_dst" "=r,rQ")
194 (match_operand:SF 1 "general_operand_src" "G,rQi"))]
195 "TARGET_H8300SX"
196 "@
197 sub.l %S0,%S0
198 mov.l %S1,%S0"
199 [(set_attr "length" "2,*")
200 (set_attr "length_table" "*,movl")
201 (set_attr "cc" "set_zn,set_znv")])
202
203 (define_insn "*movsf_h8300hs"
204 [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
205 (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
206 "!TARGET_H8300SX
207 && (register_operand (operands[0], SFmode)
208 || register_operand (operands[1], SFmode))"
209 "@
210 sub.l %S0,%S0
211 mov.l %S1,%S0
212 mov.l %S1,%S0
213 mov.l %S1,%S0
214 mov.l %S1,%S0
215 mov.l %S1,%S0"
216 [(set (attr "length")
217 (symbol_ref "compute_mov_length (operands)"))
218 (set_attr "cc" "set_zn,set_znv,set_znv,set_znv,set_znv,set_znv")])
219
220 ;; ----------------------------------------------------------------------
221 ;; PUSH INSTRUCTIONS
222 ;; ----------------------------------------------------------------------
223
224 (define_insn "*push1_h8300hs_<QHI:mode>"
225 [(set (mem:QHI
226 (pre_modify:P
227 (reg:P SP_REG)
228 (plus:P (reg:P SP_REG) (const_int -4))))
229 (match_operand:QHI 0 "register_no_sp_elim_operand" "r"))]
230 ""
231 "mov.l\\t%S0,@-er7"
232 [(set_attr "length" "4")])
233