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comparison gcc/config/rs6000/rs6000.md @ 57:326d9e06c2e3

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modify c-parser.c
author ryoma <e075725@ie.u-ryukyu.ac.jp>
date Mon, 15 Feb 2010 00:54:17 +0900
parents 27e6f95b2c21 77e2b8dfacca
children 1b10fe6932e1
comparison
equal deleted inserted replaced
54:f62c169bbc24 57:326d9e06c2e3
53 ;; UNSPEC usage 53 ;; UNSPEC usage
54 ;; 54 ;;
55 55
56 (define_constants 56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines 57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_PROBE_STACK 4) ; probe stack memory reference
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer 59 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC 60 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less) 61 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8) 62 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit 63 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
99 (UNSPEC_DLMZB_CR 46) 100 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47) 101 (UNSPEC_DLMZB_STRLEN 47)
101 (UNSPEC_RSQRT 48) 102 (UNSPEC_RSQRT 48)
102 (UNSPEC_TOCREL 49) 103 (UNSPEC_TOCREL 49)
103 (UNSPEC_MACHOPIC_OFFSET 50) 104 (UNSPEC_MACHOPIC_OFFSET 50)
105 (UNSPEC_BPERM 51)
104 ]) 106 ])
105 107
106 ;; 108 ;;
107 ;; UNSPEC_VOLATILE usage 109 ;; UNSPEC_VOLATILE usage
108 ;; 110 ;;
114 (UNSPECV_EH_RR 9) ; eh_reg_restore 116 (UNSPECV_EH_RR 9) ; eh_reg_restore
115 ]) 117 ])
116 118
117 ;; Define an insn type attribute. This is used in function unit delay 119 ;; Define an insn type attribute. This is used in function unit delay
118 ;; computations. 120 ;; computations.
119 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr" 121 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
120 (const_string "integer")) 122 (const_string "integer"))
121 123
122 ;; Define floating point instruction sub-types for use with Xfpu.md 124 ;; Define floating point instruction sub-types for use with Xfpu.md
123 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default")) 125 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
124 126
136 (const_int 4))) 138 (const_int 4)))
137 139
138 ;; Processor type -- this attribute must exactly match the processor_type 140 ;; Processor type -- this attribute must exactly match the processor_type
139 ;; enumeration in rs6000.h. 141 ;; enumeration in rs6000.h.
140 142
141 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,cell" 143 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2"
142 (const (symbol_ref "rs6000_cpu_attr"))) 144 (const (symbol_ref "rs6000_cpu_attr")))
143 145
144 146
145 ;; If this instruction is microcoded on the CELL processor 147 ;; If this instruction is microcoded on the CELL processor
146 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded 148 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
155 (include "rios2.md") 157 (include "rios2.md")
156 (include "rs64.md") 158 (include "rs64.md")
157 (include "mpc.md") 159 (include "mpc.md")
158 (include "40x.md") 160 (include "40x.md")
159 (include "440.md") 161 (include "440.md")
162 (include "476.md")
160 (include "603.md") 163 (include "603.md")
161 (include "6xx.md") 164 (include "6xx.md")
162 (include "7xx.md") 165 (include "7xx.md")
163 (include "7450.md") 166 (include "7450.md")
164 (include "8540.md") 167 (include "8540.md")
165 (include "e300c2c3.md") 168 (include "e300c2c3.md")
166 (include "e500mc.md") 169 (include "e500mc.md")
170 (include "e500mc64.md")
167 (include "power4.md") 171 (include "power4.md")
168 (include "power5.md") 172 (include "power5.md")
169 (include "power6.md") 173 (include "power6.md")
174 (include "power7.md")
170 (include "cell.md") 175 (include "cell.md")
171 (include "xfpu.md") 176 (include "xfpu.md")
177 (include "a2.md")
172 178
173 (include "predicates.md") 179 (include "predicates.md")
174 (include "constraints.md") 180 (include "constraints.md")
175 181
176 (include "darwin.md") 182 (include "darwin.md")
216 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")]) 222 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
217 223
218 ; DImode bits 224 ; DImode bits
219 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")]) 225 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
220 226
227 ;; ISEL/ISEL64 target selection
228 (define_mode_attr sel [(SI "") (DI "64")])
229
230 ;; Suffix for reload patterns
231 (define_mode_attr ptrsize [(SI "32bit")
232 (DI "64bit")])
233
234 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
235 (DI "TARGET_64BIT")])
236
237 (define_mode_attr mptrsize [(SI "si")
238 (DI "di")])
239
221 240
222 ;; Start with fixed-point load and store insns. Here we put only the more 241 ;; Start with fixed-point load and store insns. Here we put only the more
223 ;; complex forms. Basic data transfer is done later. 242 ;; complex forms. Basic data transfer is done later.
224 243
225 (define_expand "zero_extend<mode>di2" 244 (define_expand "zero_extend<mode>di2"
518 (clobber (match_scratch:SI 2 "=r,r"))] 537 (clobber (match_scratch:SI 2 "=r,r"))]
519 "" 538 ""
520 "@ 539 "@
521 {andil.|andi.} %2,%1,0xff 540 {andil.|andi.} %2,%1,0xff
522 #" 541 #"
523 [(set_attr "type" "compare") 542 [(set_attr "type" "fast_compare,compare")
524 (set_attr "length" "4,8")]) 543 (set_attr "length" "4,8")])
525 544
526 (define_split 545 (define_split
527 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 546 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
528 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 547 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
544 (zero_extend:SI (match_dup 1)))] 563 (zero_extend:SI (match_dup 1)))]
545 "" 564 ""
546 "@ 565 "@
547 {andil.|andi.} %0,%1,0xff 566 {andil.|andi.} %0,%1,0xff
548 #" 567 #"
549 [(set_attr "type" "compare") 568 [(set_attr "type" "fast_compare,compare")
550 (set_attr "length" "4,8")]) 569 (set_attr "length" "4,8")])
551 570
552 (define_split 571 (define_split
553 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 572 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
554 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 573 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
685 (clobber (match_scratch:HI 2 "=r,r"))] 704 (clobber (match_scratch:HI 2 "=r,r"))]
686 "" 705 ""
687 "@ 706 "@
688 {andil.|andi.} %2,%1,0xff 707 {andil.|andi.} %2,%1,0xff
689 #" 708 #"
690 [(set_attr "type" "compare") 709 [(set_attr "type" "fast_compare,compare")
691 (set_attr "length" "4,8")]) 710 (set_attr "length" "4,8")])
692 711
693 (define_split 712 (define_split
694 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 713 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
695 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 714 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
711 (zero_extend:HI (match_dup 1)))] 730 (zero_extend:HI (match_dup 1)))]
712 "" 731 ""
713 "@ 732 "@
714 {andil.|andi.} %0,%1,0xff 733 {andil.|andi.} %0,%1,0xff
715 #" 734 #"
716 [(set_attr "type" "compare") 735 [(set_attr "type" "fast_compare,compare")
717 (set_attr "length" "4,8")]) 736 (set_attr "length" "4,8")])
718 737
719 (define_split 738 (define_split
720 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 739 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
721 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 740 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
854 (clobber (match_scratch:SI 2 "=r,r"))] 873 (clobber (match_scratch:SI 2 "=r,r"))]
855 "" 874 ""
856 "@ 875 "@
857 {andil.|andi.} %2,%1,0xffff 876 {andil.|andi.} %2,%1,0xffff
858 #" 877 #"
859 [(set_attr "type" "compare") 878 [(set_attr "type" "fast_compare,compare")
860 (set_attr "length" "4,8")]) 879 (set_attr "length" "4,8")])
861 880
862 (define_split 881 (define_split
863 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 882 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
864 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 883 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
880 (zero_extend:SI (match_dup 1)))] 899 (zero_extend:SI (match_dup 1)))]
881 "" 900 ""
882 "@ 901 "@
883 {andil.|andi.} %0,%1,0xffff 902 {andil.|andi.} %0,%1,0xffff
884 #" 903 #"
885 [(set_attr "type" "compare") 904 [(set_attr "type" "fast_compare,compare")
886 (set_attr "length" "4,8")]) 905 (set_attr "length" "4,8")])
887 906
888 (define_split 907 (define_split
889 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 908 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 909 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
957 {exts.|extsh.} %0,%1 976 {exts.|extsh.} %0,%1
958 #" 977 #"
959 [(set_attr "type" "compare") 978 [(set_attr "type" "compare")
960 (set_attr "length" "4,8")]) 979 (set_attr "length" "4,8")])
961 980
962 ;; IBM 405, 440 and 464 half-word multiplication operations. 981 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
963 982
964 (define_insn "*macchwc" 983 (define_insn "*macchwc"
965 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 984 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
966 (compare:CC (plus:SI (mult:SI (ashiftrt:SI 985 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
967 (match_operand:SI 2 "gpc_reg_operand" "r") 986 (match_operand:SI 2 "gpc_reg_operand" "r")
1421 (match_operand:HI 2 "gpc_reg_operand" "r"))))] 1440 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1422 "TARGET_MULHW" 1441 "TARGET_MULHW"
1423 "mullhwu %0, %1, %2" 1442 "mullhwu %0, %1, %2"
1424 [(set_attr "type" "imul3")]) 1443 [(set_attr "type" "imul3")])
1425 1444
1426 ;; IBM 405, 440 and 464 string-search dlmzb instruction support. 1445 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1427 (define_insn "dlmzb" 1446 (define_insn "dlmzb"
1428 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1447 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1429 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") 1448 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1430 (match_operand:SI 2 "gpc_reg_operand" "r")] 1449 (match_operand:SI 2 "gpc_reg_operand" "r")]
1431 UNSPEC_DLMZB_CR)) 1450 UNSPEC_DLMZB_CR))
1668 (clobber (match_scratch:P 2 "=r,r"))] 1687 (clobber (match_scratch:P 2 "=r,r"))]
1669 "" 1688 ""
1670 "@ 1689 "@
1671 nor. %2,%1,%1 1690 nor. %2,%1,%1
1672 #" 1691 #"
1673 [(set_attr "type" "compare") 1692 [(set_attr "type" "fast_compare,compare")
1674 (set_attr "length" "4,8")]) 1693 (set_attr "length" "4,8")])
1675 1694
1676 (define_split 1695 (define_split
1677 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 1696 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1678 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) 1697 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1694 (not:P (match_dup 1)))] 1713 (not:P (match_dup 1)))]
1695 "" 1714 ""
1696 "@ 1715 "@
1697 nor. %0,%1,%1 1716 nor. %0,%1,%1
1698 #" 1717 #"
1699 [(set_attr "type" "compare") 1718 [(set_attr "type" "fast_compare,compare")
1700 (set_attr "length" "4,8")]) 1719 (set_attr "length" "4,8")])
1701 1720
1702 (define_split 1721 (define_split
1703 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 1722 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1704 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) 1723 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
2058 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2059 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] 2078 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2060 "TARGET_POWER" 2079 "TARGET_POWER"
2061 "abs %0,%1") 2080 "abs %0,%1")
2062 2081
2063 (define_insn_and_split "abssi2_isel" 2082 (define_insn_and_split "abs<mode>2_isel"
2064 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2083 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2065 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 2084 (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
2066 (clobber (match_scratch:SI 2 "=&b")) 2085 (clobber (match_scratch:GPR 2 "=&b"))
2067 (clobber (match_scratch:CC 3 "=y"))] 2086 (clobber (match_scratch:CC 3 "=y"))]
2068 "TARGET_ISEL" 2087 "TARGET_ISEL"
2069 "#" 2088 "#"
2070 "&& reload_completed" 2089 "&& reload_completed"
2071 [(set (match_dup 2) (neg:SI (match_dup 1))) 2090 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2072 (set (match_dup 3) 2091 (set (match_dup 3)
2073 (compare:CC (match_dup 1) 2092 (compare:CC (match_dup 1)
2074 (const_int 0))) 2093 (const_int 0)))
2075 (set (match_dup 0) 2094 (set (match_dup 0)
2076 (if_then_else:SI (ge (match_dup 3) 2095 (if_then_else:GPR (ge (match_dup 3)
2077 (const_int 0)) 2096 (const_int 0))
2078 (match_dup 1) 2097 (match_dup 1)
2079 (match_dup 2)))] 2098 (match_dup 2)))]
2099 "")
2100
2101 (define_insn_and_split "nabs<mode>2_isel"
2102 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2103 (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
2104 (clobber (match_scratch:GPR 2 "=&b"))
2105 (clobber (match_scratch:CC 3 "=y"))]
2106 "TARGET_ISEL"
2107 "#"
2108 "&& reload_completed"
2109 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2110 (set (match_dup 3)
2111 (compare:CC (match_dup 1)
2112 (const_int 0)))
2113 (set (match_dup 0)
2114 (if_then_else:GPR (ge (match_dup 3)
2115 (const_int 0))
2116 (match_dup 2)
2117 (match_dup 1)))]
2080 "") 2118 "")
2081 2119
2082 (define_insn_and_split "abssi2_nopower" 2120 (define_insn_and_split "abssi2_nopower"
2083 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") 2121 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2084 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) 2122 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2219 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] 2257 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2220 UNSPEC_POPCNTB))] 2258 UNSPEC_POPCNTB))]
2221 "TARGET_POPCNTB" 2259 "TARGET_POPCNTB"
2222 "popcntb %0,%1") 2260 "popcntb %0,%1")
2223 2261
2262 (define_insn "popcntwsi2"
2263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2264 (popcount:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2265 "TARGET_POPCNTD"
2266 "popcntw %0,%1")
2267
2268 (define_insn "popcntddi2"
2269 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2270 (popcount:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
2271 "TARGET_POPCNTD && TARGET_POWERPC64"
2272 "popcntd %0,%1")
2273
2224 (define_expand "popcount<mode>2" 2274 (define_expand "popcount<mode>2"
2225 [(set (match_operand:GPR 0 "gpc_reg_operand" "") 2275 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2226 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))] 2276 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2227 "TARGET_POPCNTB" 2277 "TARGET_POPCNTB || TARGET_POPCNTD"
2228 { 2278 {
2229 rs6000_emit_popcount (operands[0], operands[1]); 2279 rs6000_emit_popcount (operands[0], operands[1]);
2230 DONE; 2280 DONE;
2231 }) 2281 })
2232 2282
2237 { 2287 {
2238 rs6000_emit_parity (operands[0], operands[1]); 2288 rs6000_emit_parity (operands[0], operands[1]);
2239 DONE; 2289 DONE;
2240 }) 2290 })
2241 2291
2242 (define_insn "bswapsi2" 2292 ;; Since the hardware zeros the upper part of the register, save generating the
2293 ;; AND immediate if we are converting to unsigned
2294 (define_insn "*bswaphi2_extenddi"
2295 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2296 (zero_extend:DI
2297 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2298 "TARGET_POWERPC64"
2299 "lhbrx %0,%y1"
2300 [(set_attr "length" "4")
2301 (set_attr "type" "load")])
2302
2303 (define_insn "*bswaphi2_extendsi"
2304 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2305 (zero_extend:SI
2306 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2307 "TARGET_POWERPC"
2308 "lhbrx %0,%y1"
2309 [(set_attr "length" "4")
2310 (set_attr "type" "load")])
2311
2312 (define_expand "bswaphi2"
2313 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2314 (bswap:HI
2315 (match_operand:HI 1 "reg_or_mem_operand" "")))
2316 (clobber (match_scratch:SI 2 ""))])]
2317 ""
2318 {
2319 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2320 operands[1] = force_reg (HImode, operands[1]);
2321 })
2322
2323 (define_insn "bswaphi2_internal"
2324 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2325 (bswap:HI
2326 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2327 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2328 "TARGET_POWERPC"
2329 "@
2330 lhbrx %0,%y1
2331 sthbrx %1,%y0
2332 #"
2333 [(set_attr "length" "4,4,12")
2334 (set_attr "type" "load,store,*")])
2335
2336 (define_split
2337 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2338 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2339 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2340 "TARGET_POWERPC && reload_completed"
2341 [(set (match_dup 3)
2342 (zero_extract:SI (match_dup 4)
2343 (const_int 8)
2344 (const_int 16)))
2345 (set (match_dup 2)
2346 (and:SI (ashift:SI (match_dup 4)
2347 (const_int 8))
2348 (const_int 65280))) ;; 0xff00
2349 (set (match_dup 3)
2350 (ior:SI (match_dup 3)
2351 (match_dup 2)))]
2352 "
2353 {
2354 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2355 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2356 }")
2357
2358 (define_insn "*bswapsi2_extenddi"
2359 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2360 (zero_extend:DI
2361 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2362 "TARGET_POWERPC64"
2363 "lwbrx %0,%y1"
2364 [(set_attr "length" "4")
2365 (set_attr "type" "load")])
2366
2367 (define_expand "bswapsi2"
2368 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2369 (bswap:SI
2370 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2371 ""
2372 {
2373 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2374 operands[1] = force_reg (SImode, operands[1]);
2375 })
2376
2377 (define_insn "*bswapsi2_internal"
2243 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r") 2378 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2244 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))] 2379 (bswap:SI
2380 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2245 "" 2381 ""
2246 "@ 2382 "@
2247 {lbrx|lwbrx} %0,%y1 2383 {lbrx|lwbrx} %0,%y1
2248 {stbrx|stwbrx} %1,%y0 2384 {stbrx|stwbrx} %1,%y0
2249 #" 2385 #"
2250 [(set_attr "length" "4,4,12")]) 2386 [(set_attr "length" "4,4,12")
2387 (set_attr "type" "load,store,*")])
2251 2388
2252 (define_split 2389 (define_split
2253 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2390 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2254 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))] 2391 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2255 "reload_completed" 2392 "reload_completed"
2263 (const_int 8) 2400 (const_int 8)
2264 (const_int 16)) 2401 (const_int 16))
2265 (rotate:SI (match_dup 1) 2402 (rotate:SI (match_dup 1)
2266 (const_int 16)))] 2403 (const_int 16)))]
2267 "") 2404 "")
2405
2406 (define_expand "bswapdi2"
2407 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2408 (bswap:DI
2409 (match_operand:DI 1 "reg_or_mem_operand" "")))
2410 (clobber (match_scratch:DI 2 ""))
2411 (clobber (match_scratch:DI 3 ""))
2412 (clobber (match_scratch:DI 4 ""))])]
2413 ""
2414 {
2415 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2416 operands[1] = force_reg (DImode, operands[1]);
2417
2418 if (!TARGET_POWERPC64)
2419 {
2420 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2421 that uses 64-bit registers needs the same scratch registers as 64-bit
2422 mode. */
2423 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2424 DONE;
2425 }
2426 })
2427
2428 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2429 (define_insn "*bswapdi2_ldbrx"
2430 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2431 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2432 (clobber (match_scratch:DI 2 "=X,X,&r"))
2433 (clobber (match_scratch:DI 3 "=X,X,&r"))
2434 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2435 "TARGET_POWERPC64 && TARGET_LDBRX
2436 && (REG_P (operands[0]) || REG_P (operands[1]))"
2437 "@
2438 ldbrx %0,%y1
2439 stdbrx %1,%y0
2440 #"
2441 [(set_attr "length" "4,4,36")
2442 (set_attr "type" "load,store,*")])
2443
2444 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2445 (define_insn "*bswapdi2_64bit"
2446 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2447 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2448 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2449 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2450 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2451 "TARGET_POWERPC64 && !TARGET_LDBRX
2452 && (REG_P (operands[0]) || REG_P (operands[1]))"
2453 "#"
2454 [(set_attr "length" "16,12,36")])
2455
2456 (define_split
2457 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2458 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2459 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2460 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2461 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2462 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2463 [(const_int 0)]
2464 "
2465 {
2466 rtx dest = operands[0];
2467 rtx src = operands[1];
2468 rtx op2 = operands[2];
2469 rtx op3 = operands[3];
2470 rtx op4 = operands[4];
2471 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2472 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2473 rtx addr1;
2474 rtx addr2;
2475 rtx word_high;
2476 rtx word_low;
2477
2478 addr1 = XEXP (src, 0);
2479 if (GET_CODE (addr1) == PLUS)
2480 {
2481 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2482 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2483 }
2484 else
2485 {
2486 emit_move_insn (op2, GEN_INT (4));
2487 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2488 }
2489
2490 if (BYTES_BIG_ENDIAN)
2491 {
2492 word_high = change_address (src, SImode, addr1);
2493 word_low = change_address (src, SImode, addr2);
2494 }
2495 else
2496 {
2497 word_high = change_address (src, SImode, addr2);
2498 word_low = change_address (src, SImode, addr1);
2499 }
2500
2501 emit_insn (gen_bswapsi2 (op3_32, word_low));
2502 emit_insn (gen_bswapsi2 (op4_32, word_high));
2503 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2504 emit_insn (gen_iordi3 (dest, dest, op4));
2505 }")
2506
2507 (define_split
2508 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2509 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2510 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2511 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2512 (clobber (match_operand:DI 4 "" ""))]
2513 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2514 [(const_int 0)]
2515 "
2516 {
2517 rtx dest = operands[0];
2518 rtx src = operands[1];
2519 rtx op2 = operands[2];
2520 rtx op3 = operands[3];
2521 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2522 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2523 rtx addr1;
2524 rtx addr2;
2525 rtx word_high;
2526 rtx word_low;
2527
2528 addr1 = XEXP (dest, 0);
2529 if (GET_CODE (addr1) == PLUS)
2530 {
2531 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2532 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2533 }
2534 else
2535 {
2536 emit_move_insn (op2, GEN_INT (4));
2537 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2538 }
2539
2540 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2541 if (BYTES_BIG_ENDIAN)
2542 {
2543 word_high = change_address (dest, SImode, addr1);
2544 word_low = change_address (dest, SImode, addr2);
2545 emit_insn (gen_bswapsi2 (word_high, src_si));
2546 emit_insn (gen_bswapsi2 (word_low, op3_si));
2547 }
2548 else
2549 {
2550 word_high = change_address (dest, SImode, addr2);
2551 word_low = change_address (dest, SImode, addr1);
2552 emit_insn (gen_bswapsi2 (word_low, src_si));
2553 emit_insn (gen_bswapsi2 (word_high, op3_si));
2554 }
2555 }")
2556
2557 (define_split
2558 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2559 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2560 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2561 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2562 (clobber (match_operand:DI 4 "" ""))]
2563 "TARGET_POWERPC64 && reload_completed"
2564 [(const_int 0)]
2565 "
2566 {
2567 rtx dest = operands[0];
2568 rtx src = operands[1];
2569 rtx op2 = operands[2];
2570 rtx op3 = operands[3];
2571 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2572 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2573 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2574 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2575
2576 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2577 emit_insn (gen_bswapsi2 (dest_si, src_si));
2578 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2579 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2580 emit_insn (gen_iordi3 (dest, dest, op3));
2581 }")
2582
2583 (define_insn "bswapdi2_32bit"
2584 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2585 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2586 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2587 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2588 "#"
2589 [(set_attr "length" "16,12,36")])
2590
2591 (define_split
2592 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2593 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2594 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2595 "!TARGET_POWERPC64 && reload_completed"
2596 [(const_int 0)]
2597 "
2598 {
2599 rtx dest = operands[0];
2600 rtx src = operands[1];
2601 rtx op2 = operands[2];
2602 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2603 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2604 rtx addr1;
2605 rtx addr2;
2606 rtx word_high;
2607 rtx word_low;
2608
2609 addr1 = XEXP (src, 0);
2610 if (GET_CODE (addr1) == PLUS)
2611 {
2612 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2613 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2614 }
2615 else
2616 {
2617 emit_move_insn (op2, GEN_INT (4));
2618 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2619 }
2620
2621 if (BYTES_BIG_ENDIAN)
2622 {
2623 word_high = change_address (src, SImode, addr1);
2624 word_low = change_address (src, SImode, addr2);
2625 }
2626 else
2627 {
2628 word_high = change_address (src, SImode, addr2);
2629 word_low = change_address (src, SImode, addr1);
2630 }
2631
2632 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2633 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2634 }")
2635
2636 (define_split
2637 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2638 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2639 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2640 "!TARGET_POWERPC64 && reload_completed"
2641 [(const_int 0)]
2642 "
2643 {
2644 rtx dest = operands[0];
2645 rtx src = operands[1];
2646 rtx op2 = operands[2];
2647 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2648 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2649 rtx addr1;
2650 rtx addr2;
2651 rtx word_high;
2652 rtx word_low;
2653
2654 addr1 = XEXP (dest, 0);
2655 if (GET_CODE (addr1) == PLUS)
2656 {
2657 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2658 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2659 }
2660 else
2661 {
2662 emit_move_insn (op2, GEN_INT (4));
2663 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2664 }
2665
2666 if (BYTES_BIG_ENDIAN)
2667 {
2668 word_high = change_address (dest, SImode, addr1);
2669 word_low = change_address (dest, SImode, addr2);
2670 }
2671 else
2672 {
2673 word_high = change_address (dest, SImode, addr2);
2674 word_low = change_address (dest, SImode, addr1);
2675 }
2676
2677 emit_insn (gen_bswapsi2 (word_high, src_low));
2678 emit_insn (gen_bswapsi2 (word_low, src_high));
2679 }")
2680
2681 (define_split
2682 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2683 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2684 (clobber (match_operand:SI 2 "" ""))]
2685 "!TARGET_POWERPC64 && reload_completed"
2686 [(const_int 0)]
2687 "
2688 {
2689 rtx dest = operands[0];
2690 rtx src = operands[1];
2691 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2692 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2693 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2694 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2695
2696 emit_insn (gen_bswapsi2 (dest_high, src_low));
2697 emit_insn (gen_bswapsi2 (dest_low, src_high));
2698 }")
2268 2699
2269 (define_expand "mulsi3" 2700 (define_expand "mulsi3"
2270 [(use (match_operand:SI 0 "gpc_reg_operand" "")) 2701 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2271 (use (match_operand:SI 1 "gpc_reg_operand" "")) 2702 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2272 (use (match_operand:SI 2 "reg_or_short_operand" ""))] 2703 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2850 "@ 3281 "@
2851 and %0,%1,%2 3282 and %0,%1,%2
2852 {rlinm|rlwinm} %0,%1,0,%m2,%M2 3283 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2853 {andil.|andi.} %0,%1,%b2 3284 {andil.|andi.} %0,%1,%b2
2854 {andiu.|andis.} %0,%1,%u2" 3285 {andiu.|andis.} %0,%1,%u2"
2855 [(set_attr "type" "*,*,compare,compare")]) 3286 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2856 3287
2857 (define_insn "andsi3_nomc" 3288 (define_insn "andsi3_nomc"
2858 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3289 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2859 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 3290 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2860 (match_operand:SI 2 "and_operand" "?r,T"))) 3291 (match_operand:SI 2 "and_operand" "?r,T")))
2893 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 3324 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2894 # 3325 #
2895 # 3326 #
2896 # 3327 #
2897 #" 3328 #"
2898 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 3329 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3330 compare,compare,compare,compare")
2899 (set_attr "length" "4,4,4,4,8,8,8,8")]) 3331 (set_attr "length" "4,4,4,4,8,8,8,8")])
2900 3332
2901 (define_insn "*andsi3_internal3_mc" 3333 (define_insn "*andsi3_internal3_mc"
2902 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 3334 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2903 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 3335 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2913 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 3345 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2914 # 3346 #
2915 # 3347 #
2916 # 3348 #
2917 #" 3349 #"
2918 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 3350 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3351 compare,compare,compare")
2919 (set_attr "length" "8,4,4,4,8,8,8,8")]) 3352 (set_attr "length" "8,4,4,4,8,8,8,8")])
2920 3353
2921 (define_split 3354 (define_split
2922 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 3355 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2923 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 3356 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2972 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 3405 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2973 # 3406 #
2974 # 3407 #
2975 # 3408 #
2976 #" 3409 #"
2977 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 3410 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3411 compare,compare,compare,compare")
2978 (set_attr "length" "4,4,4,4,8,8,8,8")]) 3412 (set_attr "length" "4,4,4,4,8,8,8,8")])
2979 3413
2980 (define_insn "*andsi3_internal5_mc" 3414 (define_insn "*andsi3_internal5_mc"
2981 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 3415 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2982 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 3416 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2994 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 3428 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2995 # 3429 #
2996 # 3430 #
2997 # 3431 #
2998 #" 3432 #"
2999 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") 3433 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3434 compare,compare,compare")
3000 (set_attr "length" "8,4,4,4,8,8,8,8")]) 3435 (set_attr "length" "8,4,4,4,8,8,8,8")])
3001 3436
3002 (define_split 3437 (define_split
3003 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 3438 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3004 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 3439 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3125 (clobber (match_scratch:SI 3 "=r,r"))] 3560 (clobber (match_scratch:SI 3 "=r,r"))]
3126 "TARGET_32BIT" 3561 "TARGET_32BIT"
3127 "@ 3562 "@
3128 %q4. %3,%1,%2 3563 %q4. %3,%1,%2
3129 #" 3564 #"
3130 [(set_attr "type" "compare") 3565 [(set_attr "type" "fast_compare,compare")
3131 (set_attr "length" "4,8")]) 3566 (set_attr "length" "4,8")])
3132 3567
3133 (define_split 3568 (define_split
3134 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 3569 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3135 (compare:CC (match_operator:SI 4 "boolean_operator" 3570 (compare:CC (match_operator:SI 4 "boolean_operator"
3154 (match_dup 4))] 3589 (match_dup 4))]
3155 "TARGET_32BIT" 3590 "TARGET_32BIT"
3156 "@ 3591 "@
3157 %q4. %0,%1,%2 3592 %q4. %0,%1,%2
3158 #" 3593 #"
3159 [(set_attr "type" "compare") 3594 [(set_attr "type" "fast_compare,compare")
3160 (set_attr "length" "4,8")]) 3595 (set_attr "length" "4,8")])
3161 3596
3162 (define_split 3597 (define_split
3163 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 3598 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3164 (compare:CC (match_operator:SI 4 "boolean_operator" 3599 (compare:CC (match_operator:SI 4 "boolean_operator"
3279 (clobber (match_scratch:SI 3 "=r,r"))] 3714 (clobber (match_scratch:SI 3 "=r,r"))]
3280 "TARGET_32BIT" 3715 "TARGET_32BIT"
3281 "@ 3716 "@
3282 %q4. %3,%1,%2 3717 %q4. %3,%1,%2
3283 #" 3718 #"
3284 [(set_attr "type" "compare") 3719 [(set_attr "type" "fast_compare,compare")
3285 (set_attr "length" "4,8")]) 3720 (set_attr "length" "4,8")])
3286 3721
3287 (define_split 3722 (define_split
3288 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 3723 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3289 (compare:CC (match_operator:SI 4 "boolean_operator" 3724 (compare:CC (match_operator:SI 4 "boolean_operator"
3308 (match_dup 4))] 3743 (match_dup 4))]
3309 "TARGET_32BIT" 3744 "TARGET_32BIT"
3310 "@ 3745 "@
3311 %q4. %0,%1,%2 3746 %q4. %0,%1,%2
3312 #" 3747 #"
3313 [(set_attr "type" "compare") 3748 [(set_attr "type" "fast_compare,compare")
3314 (set_attr "length" "4,8")]) 3749 (set_attr "length" "4,8")])
3315 3750
3316 (define_split 3751 (define_split
3317 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 3752 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3318 (compare:CC (match_operator:SI 4 "boolean_operator" 3753 (compare:CC (match_operator:SI 4 "boolean_operator"
3959 "@ 4394 "@
3960 {rlnm|rlwnm} %0,%1,%2,0xffffffff 4395 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3961 {rlinm|rlwinm} %0,%1,%h2,0xffffffff" 4396 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3962 [(set_attr "type" "var_shift_rotate,integer")]) 4397 [(set_attr "type" "var_shift_rotate,integer")])
3963 4398
4399 (define_insn "*rotlsi3_64"
4400 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4401 (zero_extend:DI
4402 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4403 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4404 "TARGET_64BIT"
4405 "@
4406 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4407 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4408 [(set_attr "type" "var_shift_rotate,integer")])
4409
3964 (define_insn "*rotlsi3_internal2" 4410 (define_insn "*rotlsi3_internal2"
3965 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4411 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3966 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4412 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3967 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4413 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3968 (const_int 0))) 4414 (const_int 0)))
4298 (define_insn "ashlsi3_no_power" 4744 (define_insn "ashlsi3_no_power"
4299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4745 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4300 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4746 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4301 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] 4747 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4302 "! TARGET_POWER" 4748 "! TARGET_POWER"
4749 "@
4750 {sl|slw} %0,%1,%2
4751 {sli|slwi} %0,%1,%h2"
4752 [(set_attr "type" "var_shift_rotate,shift")])
4753
4754 (define_insn "*ashlsi3_64"
4755 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4756 (zero_extend:DI
4757 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4758 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4759 "TARGET_POWERPC64"
4303 "@ 4760 "@
4304 {sl|slw} %0,%1,%2 4761 {sl|slw} %0,%1,%2
4305 {sli|slwi} %0,%1,%h2" 4762 {sli|slwi} %0,%1,%h2"
4306 [(set_attr "type" "var_shift_rotate,shift")]) 4763 [(set_attr "type" "var_shift_rotate,shift")])
4307 4764
4539 "@ 4996 "@
4540 mr %0,%1 4997 mr %0,%1
4541 {sr|srw} %0,%1,%2 4998 {sr|srw} %0,%1,%2
4542 {sri|srwi} %0,%1,%h2" 4999 {sri|srwi} %0,%1,%h2"
4543 [(set_attr "type" "integer,var_shift_rotate,shift")]) 5000 [(set_attr "type" "integer,var_shift_rotate,shift")])
5001
5002 (define_insn "*lshrsi3_64"
5003 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5004 (zero_extend:DI
5005 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5006 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5007 "TARGET_POWERPC64"
5008 "@
5009 {sr|srw} %0,%1,%2
5010 {sri|srwi} %0,%1,%h2"
5011 [(set_attr "type" "var_shift_rotate,shift")])
4544 5012
4545 (define_insn "" 5013 (define_insn ""
4546 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") 5014 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4547 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") 5015 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4548 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) 5016 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4968 "@ 5436 "@
4969 {sra|sraw} %0,%1,%2 5437 {sra|sraw} %0,%1,%2
4970 {srai|srawi} %0,%1,%h2" 5438 {srai|srawi} %0,%1,%h2"
4971 [(set_attr "type" "var_shift_rotate,shift")]) 5439 [(set_attr "type" "var_shift_rotate,shift")])
4972 5440
5441 (define_insn "*ashrsi3_64"
5442 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5443 (sign_extend:DI
5444 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5445 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5446 "TARGET_POWERPC64"
5447 "@
5448 {sra|sraw} %0,%1,%2
5449 {srai|srawi} %0,%1,%h2"
5450 [(set_attr "type" "var_shift_rotate,shift")])
5451
4973 (define_insn "" 5452 (define_insn ""
4974 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 5453 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4975 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 5454 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4976 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 5455 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4977 (const_int 0))) 5456 (const_int 0)))
5117 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))] 5596 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5118 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" 5597 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5119 "") 5598 "")
5120 5599
5121 (define_insn_and_split "*extendsfdf2_fpr" 5600 (define_insn_and_split "*extendsfdf2_fpr"
5122 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f") 5601 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5123 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))] 5602 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5124 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 5603 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5125 "@ 5604 "@
5126 # 5605 #
5127 fmr %0,%1 5606 fmr %0,%1
5140 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" 5619 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5141 "") 5620 "")
5142 5621
5143 (define_insn "*truncdfsf2_fpr" 5622 (define_insn "*truncdfsf2_fpr"
5144 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5623 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5145 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] 5624 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5146 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 5625 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5147 "frsp %0,%1" 5626 "frsp %0,%1"
5148 [(set_attr "type" "fp")]) 5627 [(set_attr "type" "fp")])
5149 5628
5150 (define_insn "aux_truncdfsf2" 5629 (define_insn "aux_truncdfsf2"
5301 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] 5780 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5302 "TARGET_PPC_GFXOPT && flag_finite_math_only" 5781 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5303 "fres %0,%1" 5782 "fres %0,%1"
5304 [(set_attr "type" "fp")]) 5783 [(set_attr "type" "fp")])
5305 5784
5306 (define_insn "" 5785 (define_insn "*fmaddsf4_powerpc"
5307 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5786 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5308 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5787 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5309 (match_operand:SF 2 "gpc_reg_operand" "f")) 5788 (match_operand:SF 2 "gpc_reg_operand" "f"))
5310 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5789 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5311 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS 5790 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5312 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD" 5791 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5313 "fmadds %0,%1,%2,%3" 5792 "fmadds %0,%1,%2,%3"
5314 [(set_attr "type" "fp") 5793 [(set_attr "type" "fp")
5315 (set_attr "fp_type" "fp_maddsub_s")]) 5794 (set_attr "fp_type" "fp_maddsub_s")])
5316 5795
5317 (define_insn "" 5796 (define_insn "*fmaddsf4_power"
5318 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5797 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5319 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5798 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5320 (match_operand:SF 2 "gpc_reg_operand" "f")) 5799 (match_operand:SF 2 "gpc_reg_operand" "f"))
5321 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5800 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5322 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 5801 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5323 "{fma|fmadd} %0,%1,%2,%3" 5802 "{fma|fmadd} %0,%1,%2,%3"
5324 [(set_attr "type" "dmul")]) 5803 [(set_attr "type" "dmul")])
5325 5804
5326 (define_insn "" 5805 (define_insn "*fmsubsf4_powerpc"
5327 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5806 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5328 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5807 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5329 (match_operand:SF 2 "gpc_reg_operand" "f")) 5808 (match_operand:SF 2 "gpc_reg_operand" "f"))
5330 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5809 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5331 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS 5810 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5332 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD" 5811 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5333 "fmsubs %0,%1,%2,%3" 5812 "fmsubs %0,%1,%2,%3"
5334 [(set_attr "type" "fp") 5813 [(set_attr "type" "fp")
5335 (set_attr "fp_type" "fp_maddsub_s")]) 5814 (set_attr "fp_type" "fp_maddsub_s")])
5336 5815
5337 (define_insn "" 5816 (define_insn "*fmsubsf4_power"
5338 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5817 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5339 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5818 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5340 (match_operand:SF 2 "gpc_reg_operand" "f")) 5819 (match_operand:SF 2 "gpc_reg_operand" "f"))
5341 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5820 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5342 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 5821 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5343 "{fms|fmsub} %0,%1,%2,%3" 5822 "{fms|fmsub} %0,%1,%2,%3"
5344 [(set_attr "type" "dmul")]) 5823 [(set_attr "type" "dmul")])
5345 5824
5346 (define_insn "" 5825 (define_insn "*fnmaddsf4_powerpc_1"
5347 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5826 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5348 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5827 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5349 (match_operand:SF 2 "gpc_reg_operand" "f")) 5828 (match_operand:SF 2 "gpc_reg_operand" "f"))
5350 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 5829 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5351 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5830 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5352 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)" 5831 && TARGET_SINGLE_FLOAT"
5353 "fnmadds %0,%1,%2,%3" 5832 "fnmadds %0,%1,%2,%3"
5354 [(set_attr "type" "fp") 5833 [(set_attr "type" "fp")
5355 (set_attr "fp_type" "fp_maddsub_s")]) 5834 (set_attr "fp_type" "fp_maddsub_s")])
5356 5835
5357 (define_insn "" 5836 (define_insn "*fnmaddsf4_powerpc_2"
5358 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5837 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5359 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) 5838 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5360 (match_operand:SF 2 "gpc_reg_operand" "f")) 5839 (match_operand:SF 2 "gpc_reg_operand" "f"))
5361 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5840 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5362 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5841 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5363 && ! HONOR_SIGNED_ZEROS (SFmode)" 5842 && ! HONOR_SIGNED_ZEROS (SFmode)"
5364 "fnmadds %0,%1,%2,%3" 5843 "fnmadds %0,%1,%2,%3"
5365 [(set_attr "type" "fp") 5844 [(set_attr "type" "fp")
5366 (set_attr "fp_type" "fp_maddsub_s")]) 5845 (set_attr "fp_type" "fp_maddsub_s")])
5367 5846
5368 (define_insn "" 5847 (define_insn "*fnmaddsf4_power_1"
5369 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5848 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5370 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5849 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5371 (match_operand:SF 2 "gpc_reg_operand" "f")) 5850 (match_operand:SF 2 "gpc_reg_operand" "f"))
5372 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 5851 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5373 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 5852 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5374 "{fnma|fnmadd} %0,%1,%2,%3" 5853 "{fnma|fnmadd} %0,%1,%2,%3"
5375 [(set_attr "type" "dmul")]) 5854 [(set_attr "type" "dmul")])
5376 5855
5377 (define_insn "" 5856 (define_insn "*fnmaddsf4_power_2"
5378 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5857 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5379 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) 5858 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5380 (match_operand:SF 2 "gpc_reg_operand" "f")) 5859 (match_operand:SF 2 "gpc_reg_operand" "f"))
5381 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5860 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5382 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5861 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5383 && ! HONOR_SIGNED_ZEROS (SFmode)" 5862 && ! HONOR_SIGNED_ZEROS (SFmode)"
5384 "{fnma|fnmadd} %0,%1,%2,%3" 5863 "{fnma|fnmadd} %0,%1,%2,%3"
5385 [(set_attr "type" "dmul")]) 5864 [(set_attr "type" "dmul")])
5386 5865
5387 (define_insn "" 5866 (define_insn "*fnmsubsf4_powerpc_1"
5388 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5867 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5389 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5868 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5390 (match_operand:SF 2 "gpc_reg_operand" "f")) 5869 (match_operand:SF 2 "gpc_reg_operand" "f"))
5391 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 5870 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5392 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5871 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5393 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)" 5872 && TARGET_SINGLE_FLOAT"
5394 "fnmsubs %0,%1,%2,%3" 5873 "fnmsubs %0,%1,%2,%3"
5395 [(set_attr "type" "fp") 5874 [(set_attr "type" "fp")
5396 (set_attr "fp_type" "fp_maddsub_s")]) 5875 (set_attr "fp_type" "fp_maddsub_s")])
5397 5876
5398 (define_insn "" 5877 (define_insn "*fnmsubsf4_powerpc_2"
5399 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5878 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5400 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") 5879 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5401 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5880 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5402 (match_operand:SF 2 "gpc_reg_operand" "f"))))] 5881 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5403 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5882 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5404 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)" 5883 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5405 "fnmsubs %0,%1,%2,%3" 5884 "fnmsubs %0,%1,%2,%3"
5406 [(set_attr "type" "fp") 5885 [(set_attr "type" "fp")
5407 (set_attr "fp_type" "fp_maddsub_s")]) 5886 (set_attr "fp_type" "fp_maddsub_s")])
5408 5887
5409 (define_insn "" 5888 (define_insn "*fnmsubsf4_power_1"
5410 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5889 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5411 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5890 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5412 (match_operand:SF 2 "gpc_reg_operand" "f")) 5891 (match_operand:SF 2 "gpc_reg_operand" "f"))
5413 (match_operand:SF 3 "gpc_reg_operand" "f"))))] 5892 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5414 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" 5893 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5415 "{fnms|fnmsub} %0,%1,%2,%3" 5894 "{fnms|fnmsub} %0,%1,%2,%3"
5416 [(set_attr "type" "dmul")]) 5895 [(set_attr "type" "dmul")])
5417 5896
5418 (define_insn "" 5897 (define_insn "*fnmsubsf4_power_2"
5419 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5898 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5420 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") 5899 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5421 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") 5900 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5422 (match_operand:SF 2 "gpc_reg_operand" "f"))))] 5901 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5423 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD 5902 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5494 (set (match_operand:DF 0 "gpc_reg_operand" "") 5973 (set (match_operand:DF 0 "gpc_reg_operand" "")
5495 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "") 5974 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5496 (match_dup 5)) 5975 (match_dup 5))
5497 (match_dup 3) 5976 (match_dup 3)
5498 (match_dup 4)))] 5977 (match_dup 4)))]
5499 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 5978 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5500 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)" 5979 && ((TARGET_PPC_GFXOPT
5980 && !HONOR_NANS (DFmode)
5981 && !HONOR_SIGNED_ZEROS (DFmode))
5982 || VECTOR_UNIT_VSX_P (DFmode))"
5501 { 5983 {
5984 if (VECTOR_UNIT_VSX_P (DFmode))
5985 {
5986 emit_insn (gen_vsx_copysigndf3 (operands[0], operands[1],
5987 operands[2], CONST0_RTX (DFmode)));
5988 DONE;
5989 }
5502 operands[3] = gen_reg_rtx (DFmode); 5990 operands[3] = gen_reg_rtx (DFmode);
5503 operands[4] = gen_reg_rtx (DFmode); 5991 operands[4] = gen_reg_rtx (DFmode);
5504 operands[5] = CONST0_RTX (DFmode); 5992 operands[5] = CONST0_RTX (DFmode);
5505 }) 5993 })
5506 5994
5540 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), 6028 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5541 operands[1], operands[2]); 6029 operands[1], operands[2]);
5542 DONE; 6030 DONE;
5543 }") 6031 }")
5544 6032
5545 (define_expand "movsicc" 6033 (define_expand "mov<mode>cc"
5546 [(set (match_operand:SI 0 "gpc_reg_operand" "") 6034 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5547 (if_then_else:SI (match_operand 1 "comparison_operator" "") 6035 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5548 (match_operand:SI 2 "gpc_reg_operand" "") 6036 (match_operand:GPR 2 "gpc_reg_operand" "")
5549 (match_operand:SI 3 "gpc_reg_operand" "")))] 6037 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5550 "TARGET_ISEL" 6038 "TARGET_ISEL<sel>"
5551 " 6039 "
5552 { 6040 {
5553 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) 6041 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5554 DONE; 6042 DONE;
5555 else 6043 else
5562 ;; 6050 ;;
5563 ;; We need 2 patterns: an unsigned and a signed pattern. We could 6051 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5564 ;; leave out the mode in operand 4 and use one pattern, but reload can 6052 ;; leave out the mode in operand 4 and use one pattern, but reload can
5565 ;; change the mode underneath our feet and then gets confused trying 6053 ;; change the mode underneath our feet and then gets confused trying
5566 ;; to reload the value. 6054 ;; to reload the value.
5567 (define_insn "isel_signed" 6055 (define_insn "isel_signed_<mode>"
5568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6056 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5569 (if_then_else:SI 6057 (if_then_else:GPR
5570 (match_operator 1 "comparison_operator" 6058 (match_operator 1 "comparison_operator"
5571 [(match_operand:CC 4 "cc_reg_operand" "y") 6059 [(match_operand:CC 4 "cc_reg_operand" "y")
5572 (const_int 0)]) 6060 (const_int 0)])
5573 (match_operand:SI 2 "gpc_reg_operand" "b") 6061 (match_operand:GPR 2 "gpc_reg_operand" "b")
5574 (match_operand:SI 3 "gpc_reg_operand" "b")))] 6062 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5575 "TARGET_ISEL" 6063 "TARGET_ISEL<sel>"
5576 "* 6064 "*
5577 { return output_isel (operands); }" 6065 { return output_isel (operands); }"
5578 [(set_attr "length" "4")]) 6066 [(set_attr "type" "isel")
5579 6067 (set_attr "length" "4")])
5580 (define_insn "isel_unsigned" 6068
5581 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6069 (define_insn "isel_unsigned_<mode>"
5582 (if_then_else:SI 6070 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6071 (if_then_else:GPR
5583 (match_operator 1 "comparison_operator" 6072 (match_operator 1 "comparison_operator"
5584 [(match_operand:CCUNS 4 "cc_reg_operand" "y") 6073 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5585 (const_int 0)]) 6074 (const_int 0)])
5586 (match_operand:SI 2 "gpc_reg_operand" "b") 6075 (match_operand:GPR 2 "gpc_reg_operand" "b")
5587 (match_operand:SI 3 "gpc_reg_operand" "b")))] 6076 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5588 "TARGET_ISEL" 6077 "TARGET_ISEL<sel>"
5589 "* 6078 "*
5590 { return output_isel (operands); }" 6079 { return output_isel (operands); }"
5591 [(set_attr "length" "4")]) 6080 [(set_attr "type" "isel")
6081 (set_attr "length" "4")])
5592 6082
5593 (define_expand "movsfcc" 6083 (define_expand "movsfcc"
5594 [(set (match_operand:SF 0 "gpc_reg_operand" "") 6084 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5595 (if_then_else:SF (match_operand 1 "comparison_operator" "") 6085 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5596 (match_operand:SF 2 "gpc_reg_operand" "") 6086 (match_operand:SF 2 "gpc_reg_operand" "")
5614 "fsel %0,%1,%2,%3" 6104 "fsel %0,%1,%2,%3"
5615 [(set_attr "type" "fp")]) 6105 [(set_attr "type" "fp")])
5616 6106
5617 (define_insn "*fseldfsf4" 6107 (define_insn "*fseldfsf4"
5618 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 6108 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5619 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") 6109 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5620 (match_operand:DF 4 "zero_fp_constant" "F")) 6110 (match_operand:DF 4 "zero_fp_constant" "F"))
5621 (match_operand:SF 2 "gpc_reg_operand" "f") 6111 (match_operand:SF 2 "gpc_reg_operand" "f")
5622 (match_operand:SF 3 "gpc_reg_operand" "f")))] 6112 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5623 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT" 6113 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5624 "fsel %0,%1,%2,%3" 6114 "fsel %0,%1,%2,%3"
5629 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))] 6119 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5630 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" 6120 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5631 "") 6121 "")
5632 6122
5633 (define_insn "*negdf2_fpr" 6123 (define_insn "*negdf2_fpr"
5634 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6124 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5635 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 6125 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5636 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6126 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6127 && !VECTOR_UNIT_VSX_P (DFmode)"
5637 "fneg %0,%1" 6128 "fneg %0,%1"
5638 [(set_attr "type" "fp")]) 6129 [(set_attr "type" "fp")])
5639 6130
5640 (define_expand "absdf2" 6131 (define_expand "absdf2"
5641 [(set (match_operand:DF 0 "gpc_reg_operand" "") 6132 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5642 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))] 6133 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5643 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" 6134 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5644 "") 6135 "")
5645 6136
5646 (define_insn "*absdf2_fpr" 6137 (define_insn "*absdf2_fpr"
5647 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6138 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5648 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 6139 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5649 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6140 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6141 && !VECTOR_UNIT_VSX_P (DFmode)"
5650 "fabs %0,%1" 6142 "fabs %0,%1"
5651 [(set_attr "type" "fp")]) 6143 [(set_attr "type" "fp")])
5652 6144
5653 (define_insn "*nabsdf2_fpr" 6145 (define_insn "*nabsdf2_fpr"
5654 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6146 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5655 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] 6147 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5656 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6148 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6149 && !VECTOR_UNIT_VSX_P (DFmode)"
5657 "fnabs %0,%1" 6150 "fnabs %0,%1"
5658 [(set_attr "type" "fp")]) 6151 [(set_attr "type" "fp")])
5659 6152
5660 (define_expand "adddf3" 6153 (define_expand "adddf3"
5661 [(set (match_operand:DF 0 "gpc_reg_operand" "") 6154 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5663 (match_operand:DF 2 "gpc_reg_operand" "")))] 6156 (match_operand:DF 2 "gpc_reg_operand" "")))]
5664 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" 6157 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5665 "") 6158 "")
5666 6159
5667 (define_insn "*adddf3_fpr" 6160 (define_insn "*adddf3_fpr"
5668 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6161 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5669 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 6162 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5670 (match_operand:DF 2 "gpc_reg_operand" "f")))] 6163 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5671 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6164 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6165 && !VECTOR_UNIT_VSX_P (DFmode)"
5672 "{fa|fadd} %0,%1,%2" 6166 "{fa|fadd} %0,%1,%2"
5673 [(set_attr "type" "fp") 6167 [(set_attr "type" "fp")
5674 (set_attr "fp_type" "fp_addsub_d")]) 6168 (set_attr "fp_type" "fp_addsub_d")])
5675 6169
5676 (define_expand "subdf3" 6170 (define_expand "subdf3"
5679 (match_operand:DF 2 "gpc_reg_operand" "")))] 6173 (match_operand:DF 2 "gpc_reg_operand" "")))]
5680 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" 6174 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5681 "") 6175 "")
5682 6176
5683 (define_insn "*subdf3_fpr" 6177 (define_insn "*subdf3_fpr"
5684 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6178 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5685 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") 6179 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5686 (match_operand:DF 2 "gpc_reg_operand" "f")))] 6180 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5687 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6181 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6182 && !VECTOR_UNIT_VSX_P (DFmode)"
5688 "{fs|fsub} %0,%1,%2" 6183 "{fs|fsub} %0,%1,%2"
5689 [(set_attr "type" "fp") 6184 [(set_attr "type" "fp")
5690 (set_attr "fp_type" "fp_addsub_d")]) 6185 (set_attr "fp_type" "fp_addsub_d")])
5691 6186
5692 (define_expand "muldf3" 6187 (define_expand "muldf3"
5695 (match_operand:DF 2 "gpc_reg_operand" "")))] 6190 (match_operand:DF 2 "gpc_reg_operand" "")))]
5696 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" 6191 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5697 "") 6192 "")
5698 6193
5699 (define_insn "*muldf3_fpr" 6194 (define_insn "*muldf3_fpr"
5700 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6195 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5701 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 6196 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5702 (match_operand:DF 2 "gpc_reg_operand" "f")))] 6197 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5703 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6198 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6199 && !VECTOR_UNIT_VSX_P (DFmode)"
5704 "{fm|fmul} %0,%1,%2" 6200 "{fm|fmul} %0,%1,%2"
5705 [(set_attr "type" "dmul") 6201 [(set_attr "type" "dmul")
5706 (set_attr "fp_type" "fp_mul_d")]) 6202 (set_attr "fp_type" "fp_mul_d")])
5707 6203
5708 (define_expand "divdf3" 6204 (define_expand "divdf3"
5713 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE) 6209 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
5714 && !TARGET_SIMPLE_FPU" 6210 && !TARGET_SIMPLE_FPU"
5715 "") 6211 "")
5716 6212
5717 (define_insn "*divdf3_fpr" 6213 (define_insn "*divdf3_fpr"
5718 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6214 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5719 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") 6215 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5720 (match_operand:DF 2 "gpc_reg_operand" "f")))] 6216 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5721 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU" 6217 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6218 && !VECTOR_UNIT_VSX_P (DFmode)"
5722 "{fd|fdiv} %0,%1,%2" 6219 "{fd|fdiv} %0,%1,%2"
5723 [(set_attr "type" "ddiv")]) 6220 [(set_attr "type" "ddiv")])
5724 6221
5725 (define_expand "recipdf3" 6222 (define_expand "recipdf3"
5726 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6223 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5727 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f") 6224 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")
5728 (match_operand:DF 2 "gpc_reg_operand" "f")] 6225 (match_operand:DF 2 "gpc_reg_operand" "d")]
5729 UNSPEC_FRES))] 6226 UNSPEC_FRES))]
5730 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size 6227 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5731 && flag_finite_math_only && !flag_trapping_math" 6228 && flag_finite_math_only && !flag_trapping_math"
5732 { 6229 {
5733 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]); 6230 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5734 DONE; 6231 DONE;
5735 }) 6232 })
5736 6233
5737 (define_insn "fred" 6234 (define_expand "fred"
6235 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6236 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRES))]
6237 "(TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)) && flag_finite_math_only"
6238 "")
6239
6240 (define_insn "*fred_fpr"
5738 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6241 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5739 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] 6242 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5740 "TARGET_POPCNTB && flag_finite_math_only" 6243 "TARGET_POPCNTB && flag_finite_math_only && !VECTOR_UNIT_VSX_P (DFmode)"
5741 "fre %0,%1" 6244 "fre %0,%1"
5742 [(set_attr "type" "fp")]) 6245 [(set_attr "type" "fp")])
5743 6246
5744 (define_insn "" 6247 (define_insn "*fmadddf4_fpr"
5745 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6248 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5746 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 6249 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5747 (match_operand:DF 2 "gpc_reg_operand" "f")) 6250 (match_operand:DF 2 "gpc_reg_operand" "d"))
5748 (match_operand:DF 3 "gpc_reg_operand" "f")))] 6251 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5749 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT" 6252 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6253 && VECTOR_UNIT_NONE_P (DFmode)"
5750 "{fma|fmadd} %0,%1,%2,%3" 6254 "{fma|fmadd} %0,%1,%2,%3"
5751 [(set_attr "type" "dmul") 6255 [(set_attr "type" "dmul")
5752 (set_attr "fp_type" "fp_maddsub_d")]) 6256 (set_attr "fp_type" "fp_maddsub_d")])
5753 6257
5754 (define_insn "" 6258 (define_insn "*fmsubdf4_fpr"
5755 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6259 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5756 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 6260 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5757 (match_operand:DF 2 "gpc_reg_operand" "f")) 6261 (match_operand:DF 2 "gpc_reg_operand" "d"))
5758 (match_operand:DF 3 "gpc_reg_operand" "f")))] 6262 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5759 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT" 6263 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6264 && VECTOR_UNIT_NONE_P (DFmode)"
5760 "{fms|fmsub} %0,%1,%2,%3" 6265 "{fms|fmsub} %0,%1,%2,%3"
5761 [(set_attr "type" "dmul") 6266 [(set_attr "type" "dmul")
5762 (set_attr "fp_type" "fp_maddsub_d")]) 6267 (set_attr "fp_type" "fp_maddsub_d")])
5763 6268
5764 (define_insn "" 6269 (define_insn "*fnmadddf4_fpr_1"
5765 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6270 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5766 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 6271 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5767 (match_operand:DF 2 "gpc_reg_operand" "f")) 6272 (match_operand:DF 2 "gpc_reg_operand" "d"))
5768 (match_operand:DF 3 "gpc_reg_operand" "f"))))] 6273 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
5769 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT 6274 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5770 && HONOR_SIGNED_ZEROS (DFmode)" 6275 && VECTOR_UNIT_NONE_P (DFmode)"
5771 "{fnma|fnmadd} %0,%1,%2,%3" 6276 "{fnma|fnmadd} %0,%1,%2,%3"
5772 [(set_attr "type" "dmul") 6277 [(set_attr "type" "dmul")
5773 (set_attr "fp_type" "fp_maddsub_d")]) 6278 (set_attr "fp_type" "fp_maddsub_d")])
5774 6279
5775 (define_insn "" 6280 (define_insn "*fnmadddf4_fpr_2"
5776 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6281 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5777 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) 6282 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
5778 (match_operand:DF 2 "gpc_reg_operand" "f")) 6283 (match_operand:DF 2 "gpc_reg_operand" "d"))
5779 (match_operand:DF 3 "gpc_reg_operand" "f")))] 6284 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5780 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT 6285 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5781 && ! HONOR_SIGNED_ZEROS (DFmode)" 6286 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
5782 "{fnma|fnmadd} %0,%1,%2,%3" 6287 "{fnma|fnmadd} %0,%1,%2,%3"
5783 [(set_attr "type" "dmul") 6288 [(set_attr "type" "dmul")
5784 (set_attr "fp_type" "fp_maddsub_d")]) 6289 (set_attr "fp_type" "fp_maddsub_d")])
5785 6290
5786 (define_insn "" 6291 (define_insn "*fnmsubdf4_fpr_1"
5787 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6292 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5788 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 6293 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5789 (match_operand:DF 2 "gpc_reg_operand" "f")) 6294 (match_operand:DF 2 "gpc_reg_operand" "d"))
5790 (match_operand:DF 3 "gpc_reg_operand" "f"))))] 6295 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
5791 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT 6296 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5792 && HONOR_SIGNED_ZEROS (DFmode)" 6297 && VECTOR_UNIT_NONE_P (DFmode)"
5793 "{fnms|fnmsub} %0,%1,%2,%3" 6298 "{fnms|fnmsub} %0,%1,%2,%3"
5794 [(set_attr "type" "dmul") 6299 [(set_attr "type" "dmul")
5795 (set_attr "fp_type" "fp_maddsub_d")]) 6300 (set_attr "fp_type" "fp_maddsub_d")])
5796 6301
5797 (define_insn "" 6302 (define_insn "*fnmsubdf4_fpr_2"
5798 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6303 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5799 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") 6304 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
5800 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") 6305 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5801 (match_operand:DF 2 "gpc_reg_operand" "f"))))] 6306 (match_operand:DF 2 "gpc_reg_operand" "d"))))]
5802 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT 6307 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
5803 && ! HONOR_SIGNED_ZEROS (DFmode)" 6308 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
5804 "{fnms|fnmsub} %0,%1,%2,%3" 6309 "{fnms|fnmsub} %0,%1,%2,%3"
5805 [(set_attr "type" "dmul") 6310 [(set_attr "type" "dmul")
5806 (set_attr "fp_type" "fp_maddsub_d")]) 6311 (set_attr "fp_type" "fp_maddsub_d")])
5807 6312
5808 (define_insn "sqrtdf2" 6313 (define_insn "sqrtdf2"
5809 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6314 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5810 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] 6315 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5811 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS 6316 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
5812 && TARGET_DOUBLE_FLOAT" 6317 && TARGET_DOUBLE_FLOAT
6318 && !VECTOR_UNIT_VSX_P (DFmode)"
5813 "fsqrt %0,%1" 6319 "fsqrt %0,%1"
5814 [(set_attr "type" "dsqrt")]) 6320 [(set_attr "type" "dsqrt")])
5815 6321
5816 ;; The conditional move instructions allow us to perform max and min 6322 ;; The conditional move instructions allow us to perform max and min
5817 ;; operations even when 6323 ;; operations even when
5863 else 6369 else
5864 FAIL; 6370 FAIL;
5865 }") 6371 }")
5866 6372
5867 (define_insn "*fseldfdf4" 6373 (define_insn "*fseldfdf4"
5868 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6374 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5869 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") 6375 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5870 (match_operand:DF 4 "zero_fp_constant" "F")) 6376 (match_operand:DF 4 "zero_fp_constant" "F"))
5871 (match_operand:DF 2 "gpc_reg_operand" "f") 6377 (match_operand:DF 2 "gpc_reg_operand" "d")
5872 (match_operand:DF 3 "gpc_reg_operand" "f")))] 6378 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5873 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6379 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5874 "fsel %0,%1,%2,%3" 6380 "fsel %0,%1,%2,%3"
5875 [(set_attr "type" "fp")]) 6381 [(set_attr "type" "fp")])
5876 6382
5877 (define_insn "*fselsfdf4" 6383 (define_insn "*fselsfdf4"
5878 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6384 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5879 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") 6385 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5880 (match_operand:SF 4 "zero_fp_constant" "F")) 6386 (match_operand:SF 4 "zero_fp_constant" "F"))
5881 (match_operand:DF 2 "gpc_reg_operand" "f") 6387 (match_operand:DF 2 "gpc_reg_operand" "d")
5882 (match_operand:DF 3 "gpc_reg_operand" "f")))] 6388 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5883 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT" 6389 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5884 "fsel %0,%1,%2,%3" 6390 "fsel %0,%1,%2,%3"
5885 [(set_attr "type" "fp")]) 6391 [(set_attr "type" "fp")])
5886 6392
5887 ;; Conversions to and from floating-point. 6393 ;; Conversions to and from floating-point.
5895 (define_expand "fix_truncsfsi2" 6401 (define_expand "fix_truncsfsi2"
5896 [(set (match_operand:SI 0 "gpc_reg_operand" "") 6402 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5897 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] 6403 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5898 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT" 6404 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5899 "") 6405 "")
6406
6407 (define_expand "fixuns_truncdfsi2"
6408 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6409 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
6410 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
6411 "")
6412
6413 (define_expand "fixuns_truncdfdi2"
6414 [(set (match_operand:DI 0 "register_operand" "")
6415 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
6416 "TARGET_HARD_FLOAT && TARGET_VSX"
6417 "")
5900 6418
5901 ; For each of these conversions, there is a define_expand, a define_insn 6419 ; For each of these conversions, there is a define_expand, a define_insn
5902 ; with a '#' template, and a define_split (with C code). The idea is 6420 ; with a '#' template, and a define_split (with C code). The idea is
5903 ; to allow constant folding with the template of the define_insn, 6421 ; to allow constant folding with the template of the define_insn,
5904 ; then to have the insns split later (between sched1 and final). 6422 ; then to have the insns split later (between sched1 and final).
5933 operands[5] = gen_reg_rtx (DFmode); 6451 operands[5] = gen_reg_rtx (DFmode);
5934 operands[6] = gen_reg_rtx (SImode); 6452 operands[6] = gen_reg_rtx (SImode);
5935 }") 6453 }")
5936 6454
5937 (define_insn_and_split "*floatsidf2_internal" 6455 (define_insn_and_split "*floatsidf2_internal"
5938 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") 6456 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5939 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 6457 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5940 (use (match_operand:SI 2 "gpc_reg_operand" "r")) 6458 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5941 (use (match_operand:DF 3 "gpc_reg_operand" "f")) 6459 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5942 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o")) 6460 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5943 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) 6461 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5944 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] 6462 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5945 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6463 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5946 "#" 6464 "#"
5947 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))" 6465 ""
5948 [(pc)] 6466 [(pc)]
5949 " 6467 "
5950 { 6468 {
5951 rtx lowword, highword; 6469 rtx lowword, highword;
5952 gcc_assert (MEM_P (operands[4])); 6470 gcc_assert (MEM_P (operands[4]));
6001 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); 6519 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6002 operands[5] = gen_reg_rtx (DFmode); 6520 operands[5] = gen_reg_rtx (DFmode);
6003 }") 6521 }")
6004 6522
6005 (define_insn_and_split "*floatunssidf2_internal" 6523 (define_insn_and_split "*floatunssidf2_internal"
6006 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") 6524 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6007 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 6525 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6008 (use (match_operand:SI 2 "gpc_reg_operand" "r")) 6526 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6009 (use (match_operand:DF 3 "gpc_reg_operand" "f")) 6527 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6010 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o")) 6528 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6011 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] 6529 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6012 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6530 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6013 "#" 6531 "#"
6014 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))" 6532 ""
6015 [(pc)] 6533 [(pc)]
6016 " 6534 "
6017 { 6535 {
6018 rtx lowword, highword; 6536 rtx lowword, highword;
6019 gcc_assert (MEM_P (operands[4])); 6537 gcc_assert (MEM_P (operands[4]));
6070 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 6588 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6071 }") 6589 }")
6072 6590
6073 (define_insn_and_split "*fix_truncdfsi2_internal" 6591 (define_insn_and_split "*fix_truncdfsi2_internal"
6074 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6592 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6075 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) 6593 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6076 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) 6594 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6077 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))] 6595 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6078 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS 6596 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6079 && TARGET_DOUBLE_FLOAT" 6597 && TARGET_DOUBLE_FLOAT"
6080 "#" 6598 "#"
6081 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))" 6599 ""
6082 [(pc)] 6600 [(pc)]
6083 " 6601 "
6084 { 6602 {
6085 rtx lowword; 6603 rtx lowword;
6086 gcc_assert (MEM_P (operands[3])); 6604 gcc_assert (MEM_P (operands[3]));
6093 }" 6611 }"
6094 [(set_attr "length" "16")]) 6612 [(set_attr "length" "16")])
6095 6613
6096 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt" 6614 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6097 [(set (match_operand:SI 0 "memory_operand" "=Z") 6615 [(set (match_operand:SI 0 "memory_operand" "=Z")
6098 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) 6616 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6099 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))] 6617 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
6100 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS 6618 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6101 && TARGET_DOUBLE_FLOAT 6619 && TARGET_DOUBLE_FLOAT
6102 && TARGET_PPC_GFXOPT" 6620 && TARGET_PPC_GFXOPT"
6103 "#" 6621 "#"
6104 "&& 1" 6622 "&& 1"
6111 }" 6629 }"
6112 [(set_attr "length" "16")]) 6630 [(set_attr "length" "16")])
6113 6631
6114 (define_insn_and_split "fix_truncdfsi2_mfpgpr" 6632 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6633 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6116 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) 6634 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6117 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) 6635 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6118 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))] 6636 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6119 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS 6637 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6120 && TARGET_DOUBLE_FLOAT" 6638 && TARGET_DOUBLE_FLOAT"
6121 "#" 6639 "#"
6122 "&& 1" 6640 "&& 1"
6129 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) 6647 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6130 ; rather than (set (subreg:SI (reg)) (fix:SI ...)) 6648 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6131 ; because the first makes it clear that operand 0 is not live 6649 ; because the first makes it clear that operand 0 is not live
6132 ; before the instruction. 6650 ; before the instruction.
6133 (define_insn "fctiwz" 6651 (define_insn "fctiwz"
6134 [(set (match_operand:DI 0 "gpc_reg_operand" "=f") 6652 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6135 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 6653 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
6136 UNSPEC_FCTIWZ))] 6654 UNSPEC_FCTIWZ))]
6137 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS 6655 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6138 && TARGET_DOUBLE_FLOAT" 6656 && TARGET_DOUBLE_FLOAT"
6139 "{fcirz|fctiwz} %0,%1" 6657 "{fcirz|fctiwz} %0,%1"
6140 [(set_attr "type" "fp")]) 6658 [(set_attr "type" "fp")])
6141 6659
6142 (define_insn "btruncdf2" 6660 (define_expand "btruncdf2"
6661 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6662 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))]
6663 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6664 "")
6665
6666 (define_insn "*btruncdf2_fpr"
6143 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6667 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6144 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))] 6668 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6145 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6669 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6670 && !VECTOR_UNIT_VSX_P (DFmode)"
6146 "friz %0,%1" 6671 "friz %0,%1"
6147 [(set_attr "type" "fp")]) 6672 [(set_attr "type" "fp")])
6148 6673
6149 (define_insn "btruncsf2" 6674 (define_insn "btruncsf2"
6150 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 6675 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6151 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))] 6676 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6152 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT " 6677 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6153 "friz %0,%1" 6678 "friz %0,%1"
6154 [(set_attr "type" "fp")]) 6679 [(set_attr "type" "fp")])
6155 6680
6156 (define_insn "ceildf2" 6681 (define_expand "ceildf2"
6157 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6682 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6158 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))] 6683 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIP))]
6159 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6684 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6685 "")
6686
6687 (define_insn "*ceildf2_fpr"
6688 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6689 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))]
6690 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6691 && !VECTOR_UNIT_VSX_P (DFmode)"
6160 "frip %0,%1" 6692 "frip %0,%1"
6161 [(set_attr "type" "fp")]) 6693 [(set_attr "type" "fp")])
6162 6694
6163 (define_insn "ceilsf2" 6695 (define_insn "ceilsf2"
6164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 6696 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6165 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))] 6697 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6166 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT " 6698 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6167 "frip %0,%1" 6699 "frip %0,%1"
6168 [(set_attr "type" "fp")]) 6700 [(set_attr "type" "fp")])
6169 6701
6170 (define_insn "floordf2" 6702 (define_expand "floordf2"
6171 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6703 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6172 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))] 6704 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIM))]
6173 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6705 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6706 "")
6707
6708 (define_insn "*floordf2_fpr"
6709 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6710 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))]
6711 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6712 && !VECTOR_UNIT_VSX_P (DFmode)"
6174 "frim %0,%1" 6713 "frim %0,%1"
6175 [(set_attr "type" "fp")]) 6714 [(set_attr "type" "fp")])
6176 6715
6177 (define_insn "floorsf2" 6716 (define_insn "floorsf2"
6178 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 6717 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6179 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))] 6718 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6180 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT " 6719 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6181 "frim %0,%1" 6720 "frim %0,%1"
6182 [(set_attr "type" "fp")]) 6721 [(set_attr "type" "fp")])
6183 6722
6723 ;; No VSX equivalent to frin
6184 (define_insn "rounddf2" 6724 (define_insn "rounddf2"
6185 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6725 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6186 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))] 6726 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))]
6187 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6727 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6188 "frin %0,%1" 6728 "frin %0,%1"
6189 [(set_attr "type" "fp")]) 6729 [(set_attr "type" "fp")])
6190 6730
6191 (define_insn "roundsf2" 6731 (define_insn "roundsf2"
6193 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))] 6733 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6194 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT " 6734 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6195 "frin %0,%1" 6735 "frin %0,%1"
6196 [(set_attr "type" "fp")]) 6736 [(set_attr "type" "fp")])
6197 6737
6738 (define_expand "ftruncdf2"
6739 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6740 (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6741 "VECTOR_UNIT_VSX_P (DFmode)"
6742 "")
6743
6198 ; An UNSPEC is used so we don't have to support SImode in FP registers. 6744 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6199 (define_insn "stfiwx" 6745 (define_insn "stfiwx"
6200 [(set (match_operand:SI 0 "memory_operand" "=Z") 6746 [(set (match_operand:SI 0 "memory_operand" "=Z")
6201 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")] 6747 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6202 UNSPEC_STFIWX))] 6748 UNSPEC_STFIWX))]
6203 "TARGET_PPC_GFXOPT" 6749 "TARGET_PPC_GFXOPT"
6204 "stfiwx %1,%y0" 6750 "stfiwx %1,%y0"
6205 [(set_attr "type" "fpstore")]) 6751 [(set_attr "type" "fpstore")])
6206 6752
6208 [(set (match_operand:SF 0 "gpc_reg_operand" "") 6754 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6209 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] 6755 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6210 "TARGET_HARD_FLOAT && !TARGET_FPRS" 6756 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6211 "") 6757 "")
6212 6758
6213 (define_insn "floatdidf2" 6759 (define_expand "floatdidf2"
6214 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 6760 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6215 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))] 6761 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6216 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS" 6762 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6763 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6764 "")
6765
6766 (define_insn "*floatdidf2_fpr"
6767 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6768 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
6769 "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6770 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6771 && !VECTOR_UNIT_VSX_P (DFmode)"
6217 "fcfid %0,%1" 6772 "fcfid %0,%1"
6218 [(set_attr "type" "fp")]) 6773 [(set_attr "type" "fp")])
6219 6774
6220 (define_insn "fix_truncdfdi2" 6775 (define_expand "floatunsdidf2"
6221 [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r") 6776 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6222 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] 6777 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6223 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS" 6778 "TARGET_VSX"
6779 "")
6780
6781 (define_expand "fix_truncdfdi2"
6782 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6783 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "")))]
6784 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6785 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6786 "")
6787
6788 (define_insn "*fix_truncdfdi2_fpr"
6789 [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
6790 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
6791 "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6792 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6793 && !VECTOR_UNIT_VSX_P (DFmode)"
6224 "fctidz %0,%1" 6794 "fctidz %0,%1"
6225 [(set_attr "type" "fp")]) 6795 [(set_attr "type" "fp")])
6226 6796
6227 (define_expand "floatdisf2" 6797 (define_expand "floatdisf2"
6228 [(set (match_operand:SF 0 "gpc_reg_operand" "") 6798 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6245 ;; This is not IEEE compliant if rounding mode is "round to nearest". 6815 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6246 ;; If the DI->DF conversion is inexact, then it's possible to suffer 6816 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6247 ;; from double rounding. 6817 ;; from double rounding.
6248 (define_insn_and_split "floatdisf2_internal1" 6818 (define_insn_and_split "floatdisf2_internal1"
6249 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 6819 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6250 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r"))) 6820 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
6251 (clobber (match_scratch:DF 2 "=f"))] 6821 (clobber (match_scratch:DF 2 "=d"))]
6252 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" 6822 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6253 "#" 6823 "#"
6254 "&& reload_completed" 6824 "&& reload_completed"
6255 [(set (match_dup 2) 6825 [(set (match_dup 2)
6256 (float:DF (match_dup 1))) 6826 (float:DF (match_dup 1)))
6647 [(set_attr "length" "4")]) 7217 [(set_attr "length" "4")])
6648 7218
6649 7219
6650 ;; PowerPC64 DImode operations. 7220 ;; PowerPC64 DImode operations.
6651 7221
6652 (define_insn_and_split "absdi2" 7222 (define_expand "absdi2"
7223 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7224 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
7225 "TARGET_POWERPC64"
7226 "
7227 {
7228 if (TARGET_ISEL)
7229 emit_insn (gen_absdi2_isel (operands[0], operands[1]));
7230 else
7231 emit_insn (gen_absdi2_internal (operands[0], operands[1]));
7232 DONE;
7233 }")
7234
7235 (define_insn_and_split "absdi2_internal"
6653 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 7236 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6654 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) 7237 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6655 (clobber (match_scratch:DI 2 "=&r,&r"))] 7238 (clobber (match_scratch:DI 2 "=&r,&r"))]
6656 "TARGET_POWERPC64" 7239 "TARGET_POWERPC64 && !TARGET_ISEL"
6657 "#" 7240 "#"
6658 "&& reload_completed" 7241 "&& reload_completed"
6659 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) 7242 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6660 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) 7243 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6661 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] 7244 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6663 7246
6664 (define_insn_and_split "*nabsdi2" 7247 (define_insn_and_split "*nabsdi2"
6665 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 7248 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6666 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) 7249 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6667 (clobber (match_scratch:DI 2 "=&r,&r"))] 7250 (clobber (match_scratch:DI 2 "=&r,&r"))]
6668 "TARGET_POWERPC64" 7251 "TARGET_POWERPC64 && !TARGET_ISEL"
6669 "#" 7252 "#"
6670 "&& reload_completed" 7253 "&& reload_completed"
6671 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) 7254 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6672 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) 7255 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6673 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] 7256 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7607 rldic%B2 %0,%1,0,%S2 8190 rldic%B2 %0,%1,0,%S2
7608 rlwinm %0,%1,0,%m2,%M2 8191 rlwinm %0,%1,0,%m2,%M2
7609 andi. %0,%1,%b2 8192 andi. %0,%1,%b2
7610 andis. %0,%1,%u2 8193 andis. %0,%1,%u2
7611 #" 8194 #"
7612 [(set_attr "type" "*,*,*,compare,compare,*") 8195 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7613 (set_attr "length" "4,4,4,4,4,8")]) 8196 (set_attr "length" "4,4,4,4,4,8")])
7614 8197
7615 (define_insn "anddi3_nomc" 8198 (define_insn "anddi3_nomc"
7616 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 8199 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7617 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") 8200 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7665 # 8248 #
7666 # 8249 #
7667 # 8250 #
7668 # 8251 #
7669 #" 8252 #"
7670 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare") 8253 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8254 fast_compare,compare,compare,compare,compare,compare,\
8255 compare,compare")
7671 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) 8256 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7672 8257
7673 (define_split 8258 (define_split
7674 [(set (match_operand:CC 0 "cc_reg_operand" "") 8259 [(set (match_operand:CC 0 "cc_reg_operand" "")
7675 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 8260 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7716 # 8301 #
7717 # 8302 #
7718 # 8303 #
7719 # 8304 #
7720 #" 8305 #"
7721 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare") 8306 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8307 fast_compare,compare,compare,compare,compare,compare,\
8308 compare,compare")
7722 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) 8309 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7723 8310
7724 (define_split 8311 (define_split
7725 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 8312 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7726 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 8313 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7856 (clobber (match_scratch:DI 3 "=r,r"))] 8443 (clobber (match_scratch:DI 3 "=r,r"))]
7857 "TARGET_64BIT" 8444 "TARGET_64BIT"
7858 "@ 8445 "@
7859 %q4. %3,%1,%2 8446 %q4. %3,%1,%2
7860 #" 8447 #"
7861 [(set_attr "type" "compare") 8448 [(set_attr "type" "fast_compare,compare")
7862 (set_attr "length" "4,8")]) 8449 (set_attr "length" "4,8")])
7863 8450
7864 (define_split 8451 (define_split
7865 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 8452 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7866 (compare:CC (match_operator:DI 4 "boolean_operator" 8453 (compare:CC (match_operator:DI 4 "boolean_operator"
7885 (match_dup 4))] 8472 (match_dup 4))]
7886 "TARGET_64BIT" 8473 "TARGET_64BIT"
7887 "@ 8474 "@
7888 %q4. %0,%1,%2 8475 %q4. %0,%1,%2
7889 #" 8476 #"
7890 [(set_attr "type" "compare") 8477 [(set_attr "type" "fast_compare,compare")
7891 (set_attr "length" "4,8")]) 8478 (set_attr "length" "4,8")])
7892 8479
7893 (define_split 8480 (define_split
7894 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 8481 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7895 (compare:CC (match_operator:DI 4 "boolean_operator" 8482 (compare:CC (match_operator:DI 4 "boolean_operator"
7956 (clobber (match_scratch:DI 3 "=r,r"))] 8543 (clobber (match_scratch:DI 3 "=r,r"))]
7957 "TARGET_64BIT" 8544 "TARGET_64BIT"
7958 "@ 8545 "@
7959 %q4. %3,%2,%1 8546 %q4. %3,%2,%1
7960 #" 8547 #"
7961 [(set_attr "type" "compare") 8548 [(set_attr "type" "fast_compare,compare")
7962 (set_attr "length" "4,8")]) 8549 (set_attr "length" "4,8")])
7963 8550
7964 (define_split 8551 (define_split
7965 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 8552 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7966 (compare:CC (match_operator:DI 4 "boolean_operator" 8553 (compare:CC (match_operator:DI 4 "boolean_operator"
7985 (match_dup 4))] 8572 (match_dup 4))]
7986 "TARGET_64BIT" 8573 "TARGET_64BIT"
7987 "@ 8574 "@
7988 %q4. %0,%2,%1 8575 %q4. %0,%2,%1
7989 #" 8576 #"
7990 [(set_attr "type" "compare") 8577 [(set_attr "type" "fast_compare,compare")
7991 (set_attr "length" "4,8")]) 8578 (set_attr "length" "4,8")])
7992 8579
7993 (define_split 8580 (define_split
7994 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 8581 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7995 (compare:CC (match_operator:DI 4 "boolean_operator" 8582 (compare:CC (match_operator:DI 4 "boolean_operator"
8022 (clobber (match_scratch:DI 3 "=r,r"))] 8609 (clobber (match_scratch:DI 3 "=r,r"))]
8023 "TARGET_64BIT" 8610 "TARGET_64BIT"
8024 "@ 8611 "@
8025 %q4. %3,%1,%2 8612 %q4. %3,%1,%2
8026 #" 8613 #"
8027 [(set_attr "type" "compare") 8614 [(set_attr "type" "fast_compare,compare")
8028 (set_attr "length" "4,8")]) 8615 (set_attr "length" "4,8")])
8029 8616
8030 (define_split 8617 (define_split
8031 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 8618 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8032 (compare:CC (match_operator:DI 4 "boolean_operator" 8619 (compare:CC (match_operator:DI 4 "boolean_operator"
8051 (match_dup 4))] 8638 (match_dup 4))]
8052 "TARGET_64BIT" 8639 "TARGET_64BIT"
8053 "@ 8640 "@
8054 %q4. %0,%1,%2 8641 %q4. %0,%1,%2
8055 #" 8642 #"
8056 [(set_attr "type" "compare") 8643 [(set_attr "type" "fast_compare,compare")
8057 (set_attr "length" "4,8")]) 8644 (set_attr "length" "4,8")])
8058 8645
8059 (define_split 8646 (define_split
8060 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 8647 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8061 (compare:CC (match_operator:DI 4 "boolean_operator" 8648 (compare:CC (match_operator:DI 4 "boolean_operator"
8068 [(set (match_dup 0) (match_dup 4)) 8655 [(set (match_dup 0) (match_dup 4))
8069 (set (match_dup 3) 8656 (set (match_dup 3)
8070 (compare:CC (match_dup 0) 8657 (compare:CC (match_dup 0)
8071 (const_int 0)))] 8658 (const_int 0)))]
8072 "") 8659 "")
8660
8661 (define_expand "smindi3"
8662 [(match_operand:DI 0 "gpc_reg_operand" "")
8663 (match_operand:DI 1 "gpc_reg_operand" "")
8664 (match_operand:DI 2 "gpc_reg_operand" "")]
8665 "TARGET_ISEL64"
8666 "
8667 {
8668 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
8669 DONE;
8670 }")
8671
8672 (define_expand "smaxdi3"
8673 [(match_operand:DI 0 "gpc_reg_operand" "")
8674 (match_operand:DI 1 "gpc_reg_operand" "")
8675 (match_operand:DI 2 "gpc_reg_operand" "")]
8676 "TARGET_ISEL64"
8677 "
8678 {
8679 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
8680 DONE;
8681 }")
8682
8683 (define_expand "umindi3"
8684 [(match_operand:DI 0 "gpc_reg_operand" "")
8685 (match_operand:DI 1 "gpc_reg_operand" "")
8686 (match_operand:DI 2 "gpc_reg_operand" "")]
8687 "TARGET_ISEL64"
8688 "
8689 {
8690 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
8691 DONE;
8692 }")
8693
8694 (define_expand "umaxdi3"
8695 [(match_operand:DI 0 "gpc_reg_operand" "")
8696 (match_operand:DI 1 "gpc_reg_operand" "")
8697 (match_operand:DI 2 "gpc_reg_operand" "")]
8698 "TARGET_ISEL64"
8699 "
8700 {
8701 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
8702 DONE;
8703 }")
8704
8073 8705
8074 ;; Now define ways of moving data around. 8706 ;; Now define ways of moving data around.
8075 8707
8076 ;; Set up a register with a value from the GOT table 8708 ;; Set up a register with a value from the GOT table
8077 8709
8141 (set_attr "length" "4")]) 8773 (set_attr "length" "4")])
8142 8774
8143 (define_insn "*movsi_internal1" 8775 (define_insn "*movsi_internal1"
8144 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") 8776 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8145 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] 8777 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8146 "gpc_reg_operand (operands[0], SImode) 8778 "!TARGET_SINGLE_FPU &&
8147 || gpc_reg_operand (operands[1], SImode)" 8779 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8148 "@ 8780 "@
8149 mr %0,%1 8781 mr %0,%1
8150 {cal|la} %0,%a1 8782 {cal|la} %0,%a1
8151 {l%U1%X1|lwz%U1%X1} %0,%1 8783 {l%U1%X1|lwz%U1%X1} %0,%1
8152 {st%U0%X0|stw%U0%X0} %1,%0 8784 {st%U0%X0|stw%U0%X0} %1,%0
8159 mt%0 %1 8791 mt%0 %1
8160 mt%0 %1 8792 mt%0 %1
8161 {cror 0,0,0|nop}" 8793 {cror 0,0,0|nop}"
8162 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") 8794 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8163 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) 8795 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8796
8797 (define_insn "*movsi_internal1_single"
8798 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8799 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8800 "TARGET_SINGLE_FPU &&
8801 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8802 "@
8803 mr %0,%1
8804 {cal|la} %0,%a1
8805 {l%U1%X1|lwz%U1%X1} %0,%1
8806 {st%U0%X0|stw%U0%X0} %1,%0
8807 {lil|li} %0,%1
8808 {liu|lis} %0,%v1
8809 #
8810 {cal|la} %0,%a1
8811 mf%1 %0
8812 mt%0 %1
8813 mt%0 %1
8814 mt%0 %1
8815 {cror 0,0,0|nop}
8816 stfs%U0%X0 %1, %0
8817 lfs%U1%X1 %0, %1"
8818 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8819 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8164 8820
8165 ;; Split a load of a large constant into the appropriate two-insn 8821 ;; Split a load of a large constant into the appropriate two-insn
8166 ;; sequence. 8822 ;; sequence.
8167 8823
8168 (define_split 8824 (define_split
8471 ;; a non-offsettable memref, but also it is less efficient than loading 9127 ;; a non-offsettable memref, but also it is less efficient than loading
8472 ;; the constant into an FP register, since it will probably be used there. 9128 ;; the constant into an FP register, since it will probably be used there.
8473 ;; The "??" is a kludge until we can figure out a more reasonable way 9129 ;; The "??" is a kludge until we can figure out a more reasonable way
8474 ;; of handling these non-offsettable values. 9130 ;; of handling these non-offsettable values.
8475 (define_insn "*movdf_hardfloat32" 9131 (define_insn "*movdf_hardfloat32"
8476 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") 9132 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
8477 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] 9133 (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
8478 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 9134 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8479 && (gpc_reg_operand (operands[0], DFmode) 9135 && (gpc_reg_operand (operands[0], DFmode)
8480 || gpc_reg_operand (operands[1], DFmode))" 9136 || gpc_reg_operand (operands[1], DFmode))"
8481 "* 9137 "*
8482 { 9138 {
8551 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands); 9207 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
8552 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); 9208 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8553 return \"\"; 9209 return \"\";
8554 } 9210 }
8555 case 3: 9211 case 3:
8556 return \"fmr %0,%1\";
8557 case 4: 9212 case 4:
8558 return \"lfd%U1%X1 %0,%1\"; 9213 return \"xxlor %x0,%x1,%x1\";
8559 case 5: 9214 case 5:
8560 return \"stfd%U0%X0 %1,%0\";
8561 case 6: 9215 case 6:
9216 return \"lxsd%U1x %x0,%y1\";
8562 case 7: 9217 case 7:
8563 case 8: 9218 case 8:
9219 return \"stxsd%U0x %x1,%y0\";
9220 case 9:
9221 return \"fmr %0,%1\";
9222 case 10:
9223 return \"lfd%U1%X1 %0,%1\";
9224 case 11:
9225 return \"stfd%U0%X0 %1,%0\";
9226 case 12:
9227 return \"xxlxor %x0,%x0,%x0\";
9228 case 13:
9229 case 14:
9230 case 15:
8564 return \"#\"; 9231 return \"#\";
8565 } 9232 }
8566 }" 9233 }"
8567 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*") 9234 [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
8568 (set_attr "length" "8,16,16,4,4,4,8,12,16")]) 9235 (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
8569 9236
8570 (define_insn "*movdf_softfloat32" 9237 (define_insn "*movdf_softfloat32"
8571 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") 9238 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8572 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] 9239 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8573 "! TARGET_POWERPC64 9240 "! TARGET_POWERPC64
8574 && ((TARGET_FPRS && !TARGET_DOUBLE_FLOAT) 9241 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8575 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) 9242 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8576 && (gpc_reg_operand (operands[0], DFmode) 9243 && (gpc_reg_operand (operands[0], DFmode)
8577 || gpc_reg_operand (operands[1], DFmode))" 9244 || gpc_reg_operand (operands[1], DFmode))"
8578 "* 9245 "*
8579 { 9246 {
8611 (set_attr "length" "8,8,8,8,12,16")]) 9278 (set_attr "length" "8,8,8,8,12,16")])
8612 9279
8613 ; ld/std require word-aligned displacements -> 'Y' constraint. 9280 ; ld/std require word-aligned displacements -> 'Y' constraint.
8614 ; List Y->r and r->Y before r->r for reload. 9281 ; List Y->r and r->Y before r->r for reload.
8615 (define_insn "*movdf_hardfloat64_mfpgpr" 9282 (define_insn "*movdf_hardfloat64_mfpgpr"
8616 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f") 9283 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
8617 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))] 9284 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
8618 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS 9285 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8619 && TARGET_DOUBLE_FLOAT 9286 && TARGET_DOUBLE_FLOAT
8620 && (gpc_reg_operand (operands[0], DFmode) 9287 && (gpc_reg_operand (operands[0], DFmode)
8621 || gpc_reg_operand (operands[1], DFmode))" 9288 || gpc_reg_operand (operands[1], DFmode))"
8622 "@ 9289 "@
8623 std%U0%X0 %1,%0 9290 std%U0%X0 %1,%0
8624 ld%U1%X1 %0,%1 9291 ld%U1%X1 %0,%1
8625 mr %0,%1 9292 mr %0,%1
9293 xxlor %x0,%x1,%x1
9294 xxlor %x0,%x1,%x1
9295 lxsd%U1x %x0,%y1
9296 lxsd%U1x %x0,%y1
9297 stxsd%U0x %x1,%y0
9298 stxsd%U0x %x1,%y0
8626 fmr %0,%1 9299 fmr %0,%1
8627 lfd%U1%X1 %0,%1 9300 lfd%U1%X1 %0,%1
8628 stfd%U0%X0 %1,%0 9301 stfd%U0%X0 %1,%0
9302 xxlxor %x0,%x0,%x0
8629 mt%0 %1 9303 mt%0 %1
8630 mf%1 %0 9304 mf%1 %0
8631 {cror 0,0,0|nop} 9305 {cror 0,0,0|nop}
8632 # 9306 #
8633 # 9307 #
8634 # 9308 #
8635 mftgpr %0,%1 9309 mftgpr %0,%1
8636 mffgpr %0,%1" 9310 mffgpr %0,%1"
8637 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr") 9311 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8638 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")]) 9312 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8639 9313
8640 ; ld/std require word-aligned displacements -> 'Y' constraint. 9314 ; ld/std require word-aligned displacements -> 'Y' constraint.
8641 ; List Y->r and r->Y before r->r for reload. 9315 ; List Y->r and r->Y before r->r for reload.
8642 (define_insn "*movdf_hardfloat64" 9316 (define_insn "*movdf_hardfloat64"
8643 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r") 9317 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
8644 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] 9318 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
8645 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS 9319 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8646 && TARGET_DOUBLE_FLOAT 9320 && TARGET_DOUBLE_FLOAT
8647 && (gpc_reg_operand (operands[0], DFmode) 9321 && (gpc_reg_operand (operands[0], DFmode)
8648 || gpc_reg_operand (operands[1], DFmode))" 9322 || gpc_reg_operand (operands[1], DFmode))"
8649 "@ 9323 "@
8650 std%U0%X0 %1,%0 9324 std%U0%X0 %1,%0
8651 ld%U1%X1 %0,%1 9325 ld%U1%X1 %0,%1
8652 mr %0,%1 9326 mr %0,%1
9327 xxlor %x0,%x1,%x1
9328 xxlor %x0,%x1,%x1
9329 lxsd%U1x %x0,%y1
9330 lxsd%U1x %x0,%y1
9331 stxsd%U0x %x1,%y0
9332 stxsd%U0x %x1,%y0
8653 fmr %0,%1 9333 fmr %0,%1
8654 lfd%U1%X1 %0,%1 9334 lfd%U1%X1 %0,%1
8655 stfd%U0%X0 %1,%0 9335 stfd%U0%X0 %1,%0
9336 xxlxor %x0,%x0,%x0
8656 mt%0 %1 9337 mt%0 %1
8657 mf%1 %0 9338 mf%1 %0
8658 {cror 0,0,0|nop} 9339 {cror 0,0,0|nop}
8659 # 9340 #
8660 # 9341 #
8661 #" 9342 #"
8662 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*") 9343 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
8663 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) 9344 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
8664 9345
8665 (define_insn "*movdf_softfloat64" 9346 (define_insn "*movdf_softfloat64"
8666 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") 9347 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8667 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] 9348 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8668 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) 9349 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8689 9370
8690 ; It's important to list the o->f and f->o moves before f->f because 9371 ; It's important to list the o->f and f->o moves before f->f because
8691 ; otherwise reload, given m->f, will try to pick f->f and reload it, 9372 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8692 ; which doesn't make progress. Likewise r->Y must be before r->r. 9373 ; which doesn't make progress. Likewise r->Y must be before r->r.
8693 (define_insn_and_split "*movtf_internal" 9374 (define_insn_and_split "*movtf_internal"
8694 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r") 9375 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
8695 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))] 9376 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
8696 "!TARGET_IEEEQUAD 9377 "!TARGET_IEEEQUAD
8697 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 9378 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8698 && (gpc_reg_operand (operands[0], TFmode) 9379 && (gpc_reg_operand (operands[0], TFmode)
8699 || gpc_reg_operand (operands[1], TFmode))" 9380 || gpc_reg_operand (operands[1], TFmode))"
8700 "#" 9381 "#"
8744 if (DEFAULT_ABI == ABI_V4 && flag_pic) 9425 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8745 operands[2] = validize_mem (force_const_mem (DFmode, operands[2])); 9426 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8746 }) 9427 })
8747 9428
8748 (define_insn_and_split "*extenddftf2_internal" 9429 (define_insn_and_split "*extenddftf2_internal"
8749 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") 9430 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
8750 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) 9431 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
8751 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))] 9432 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
8752 "!TARGET_IEEEQUAD 9433 "!TARGET_IEEEQUAD
8753 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 9434 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8754 && TARGET_LONG_DOUBLE_128" 9435 && TARGET_LONG_DOUBLE_128"
8755 "#" 9436 "#"
8756 "&& reload_completed" 9437 "&& reload_completed"
8787 && (TARGET_FPRS || TARGET_E500_DOUBLE) 9468 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8788 && TARGET_LONG_DOUBLE_128" 9469 && TARGET_LONG_DOUBLE_128"
8789 "") 9470 "")
8790 9471
8791 (define_insn_and_split "trunctfdf2_internal1" 9472 (define_insn_and_split "trunctfdf2_internal1"
8792 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") 9473 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8793 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))] 9474 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8794 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT 9475 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8795 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 9476 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8796 "@ 9477 "@
8797 # 9478 #
8798 fmr %0,%1" 9479 fmr %0,%1"
8803 DONE; 9484 DONE;
8804 } 9485 }
8805 [(set_attr "type" "fp")]) 9486 [(set_attr "type" "fp")])
8806 9487
8807 (define_insn "trunctfdf2_internal2" 9488 (define_insn "trunctfdf2_internal2"
8808 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 9489 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8809 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] 9490 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8810 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT 9491 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8811 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 9492 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8812 && TARGET_LONG_DOUBLE_128" 9493 && TARGET_LONG_DOUBLE_128"
8813 "fadd %0,%1,%L1" 9494 "fadd %0,%1,%L1"
8814 [(set_attr "type" "fp") 9495 [(set_attr "type" "fp")
8829 DONE; 9510 DONE;
8830 }) 9511 })
8831 9512
8832 (define_insn_and_split "trunctfsf2_fprs" 9513 (define_insn_and_split "trunctfsf2_fprs"
8833 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 9514 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8834 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) 9515 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8835 (clobber (match_scratch:DF 2 "=f"))] 9516 (clobber (match_scratch:DF 2 "=d"))]
8836 "!TARGET_IEEEQUAD 9517 "!TARGET_IEEEQUAD
8837 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT 9518 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8838 && TARGET_LONG_DOUBLE_128" 9519 && TARGET_LONG_DOUBLE_128"
8839 "#" 9520 "#"
8840 "&& reload_completed" 9521 "&& reload_completed"
8859 }) 9540 })
8860 9541
8861 ; fadd, but rounding towards zero. 9542 ; fadd, but rounding towards zero.
8862 ; This is probably not the optimal code sequence. 9543 ; This is probably not the optimal code sequence.
8863 (define_insn "fix_trunc_helper" 9544 (define_insn "fix_trunc_helper"
8864 [(set (match_operand:DF 0 "gpc_reg_operand" "=f") 9545 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8865 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] 9546 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8866 UNSPEC_FIX_TRUNC_TF)) 9547 UNSPEC_FIX_TRUNC_TF))
8867 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] 9548 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8868 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 9549 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8869 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" 9550 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8870 [(set_attr "type" "fp") 9551 [(set_attr "type" "fp")
8871 (set_attr "length" "20")]) 9552 (set_attr "length" "20")])
8872 9553
8903 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); 9584 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8904 }) 9585 })
8905 9586
8906 (define_insn_and_split "*fix_trunctfsi2_internal" 9587 (define_insn_and_split "*fix_trunctfsi2_internal"
8907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9588 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8908 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) 9589 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8909 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f")) 9590 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8910 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f")) 9591 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8911 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f")) 9592 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8912 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))] 9593 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8913 "!TARGET_IEEEQUAD 9594 "!TARGET_IEEEQUAD
8914 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 9595 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8915 "#" 9596 "#"
8916 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))" 9597 ""
8917 [(pc)] 9598 [(pc)]
8918 { 9599 {
8919 rtx lowword; 9600 rtx lowword;
8920 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); 9601 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8921 9602
8936 && (TARGET_FPRS || TARGET_E500_DOUBLE) 9617 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8937 && TARGET_LONG_DOUBLE_128" 9618 && TARGET_LONG_DOUBLE_128"
8938 "") 9619 "")
8939 9620
8940 (define_insn "negtf2_internal" 9621 (define_insn "negtf2_internal"
8941 [(set (match_operand:TF 0 "gpc_reg_operand" "=f") 9622 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
8942 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] 9623 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8943 "!TARGET_IEEEQUAD 9624 "!TARGET_IEEEQUAD
8944 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 9625 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8945 "* 9626 "*
8946 { 9627 {
8947 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 9628 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9002 ;; multiple insns. 9683 ;; multiple insns.
9003 9684
9004 ; List r->r after r->"o<>", otherwise reload will try to reload a 9685 ; List r->r after r->"o<>", otherwise reload will try to reload a
9005 ; non-offsettable address by using r->r which won't make progress. 9686 ; non-offsettable address by using r->r which won't make progress.
9006 (define_insn "*movdi_internal32" 9687 (define_insn "*movdi_internal32"
9007 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r") 9688 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
9008 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))] 9689 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
9009 "! TARGET_POWERPC64 9690 "! TARGET_POWERPC64
9010 && (gpc_reg_operand (operands[0], DImode) 9691 && (gpc_reg_operand (operands[0], DImode)
9011 || gpc_reg_operand (operands[1], DImode))" 9692 || gpc_reg_operand (operands[1], DImode))"
9012 "@ 9693 "@
9013 # 9694 #
9047 && gpr_or_gpr_p (operands[0], operands[1])" 9728 && gpr_or_gpr_p (operands[0], operands[1])"
9048 [(pc)] 9729 [(pc)]
9049 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) 9730 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9050 9731
9051 (define_insn "*movdi_mfpgpr" 9732 (define_insn "*movdi_mfpgpr"
9052 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f") 9733 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
9053 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))] 9734 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
9054 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS 9735 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9055 && (gpc_reg_operand (operands[0], DImode) 9736 && (gpc_reg_operand (operands[0], DImode)
9056 || gpc_reg_operand (operands[1], DImode))" 9737 || gpc_reg_operand (operands[1], DImode))"
9057 "@ 9738 "@
9058 mr %0,%1 9739 mr %0,%1
9072 mffgpr %0,%1" 9753 mffgpr %0,%1"
9073 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr") 9754 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9074 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")]) 9755 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9075 9756
9076 (define_insn "*movdi_internal64" 9757 (define_insn "*movdi_internal64"
9077 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h") 9758 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
9078 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] 9759 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
9079 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS) 9760 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9080 && (gpc_reg_operand (operands[0], DImode) 9761 && (gpc_reg_operand (operands[0], DImode)
9081 || gpc_reg_operand (operands[1], DImode))" 9762 || gpc_reg_operand (operands[1], DImode))"
9082 "@ 9763 "@
9083 mr %0,%1 9764 mr %0,%1
9235 (const_string "conditional")))]) 9916 (const_string "conditional")))])
9236 9917
9237 (define_insn "*movti_ppc64" 9918 (define_insn "*movti_ppc64"
9238 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r") 9919 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9239 (match_operand:TI 1 "input_operand" "r,r,m"))] 9920 (match_operand:TI 1 "input_operand" "r,r,m"))]
9240 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) 9921 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9241 || gpc_reg_operand (operands[1], TImode))" 9922 || gpc_reg_operand (operands[1], TImode)))
9923 && VECTOR_MEM_NONE_P (TImode)"
9242 "#" 9924 "#"
9243 [(set_attr "type" "*,load,store")]) 9925 [(set_attr "type" "*,store,load")])
9244 9926
9245 (define_split 9927 (define_split
9246 [(set (match_operand:TI 0 "gpc_reg_operand" "") 9928 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9247 (match_operand:TI 1 "const_double_operand" ""))] 9929 (match_operand:TI 1 "const_double_operand" ""))]
9248 "TARGET_POWERPC64" 9930 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
9249 [(set (match_dup 2) (match_dup 4)) 9931 [(set (match_dup 2) (match_dup 4))
9250 (set (match_dup 3) (match_dup 5))] 9932 (set (match_dup 3) (match_dup 5))]
9251 " 9933 "
9252 { 9934 {
9253 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, 9935 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9269 }") 9951 }")
9270 9952
9271 (define_split 9953 (define_split
9272 [(set (match_operand:TI 0 "nonimmediate_operand" "") 9954 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9273 (match_operand:TI 1 "input_operand" ""))] 9955 (match_operand:TI 1 "input_operand" ""))]
9274 "reload_completed 9956 "reload_completed && VECTOR_MEM_NONE_P (TImode)
9275 && gpr_or_gpr_p (operands[0], operands[1])" 9957 && gpr_or_gpr_p (operands[0], operands[1])"
9276 [(pc)] 9958 [(pc)]
9277 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) 9959 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9278 9960
9279 (define_expand "load_multiple" 9961 (define_expand "load_multiple"
10267 {stux|stwux} %3,%0,%2 10949 {stux|stwux} %3,%0,%2
10268 {stu|stwu} %3,%2(%0)" 10950 {stu|stwu} %3,%2(%0)"
10269 [(set_attr "type" "store_ux,store_u")]) 10951 [(set_attr "type" "store_ux,store_u")])
10270 10952
10271 (define_insn "*movdf_update1" 10953 (define_insn "*movdf_update1"
10272 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") 10954 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10273 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 10955 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10274 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 10956 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10275 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 10957 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10276 (plus:SI (match_dup 1) (match_dup 2)))] 10958 (plus:SI (match_dup 1) (match_dup 2)))]
10277 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE 10959 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10283 [(set_attr "type" "fpload_ux,fpload_u")]) 10965 [(set_attr "type" "fpload_ux,fpload_u")])
10284 10966
10285 (define_insn "*movdf_update2" 10967 (define_insn "*movdf_update2"
10286 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 10968 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10287 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 10969 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10288 (match_operand:DF 3 "gpc_reg_operand" "f,f")) 10970 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10289 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 10971 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10290 (plus:SI (match_dup 1) (match_dup 2)))] 10972 (plus:SI (match_dup 1) (match_dup 2)))]
10291 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE 10973 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10292 && (!avoiding_indexed_address_p (SImode) 10974 && (!avoiding_indexed_address_p (SImode)
10293 || !gpc_reg_operand (operands[2], SImode))" 10975 || !gpc_reg_operand (operands[2], SImode))"
10372 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")]) 11054 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10373 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")]) 11055 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10374 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")]) 11056 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10375 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")]) 11057 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10376 11058
10377 (define_insn "tls_gd_aix<TLSmode:tls_abi_suffix>" 11059 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10378 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11060 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10379 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s")) 11061 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10380 (match_operand 4 "" "g"))) 11062 (match_operand 4 "" "g")))
10381 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11063 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10382 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11064 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10383 UNSPEC_TLSGD) 11065 UNSPEC_TLSGD)
10384 (clobber (reg:SI LR_REGNO))] 11066 (clobber (reg:SI LR_REGNO))]
10385 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX" 11067 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10386 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%." 11068 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
11069 "&& TARGET_TLS_MARKERS"
11070 [(set (match_dup 0)
11071 (unspec:TLSmode [(match_dup 1)
11072 (match_dup 2)]
11073 UNSPEC_TLSGD))
11074 (parallel [(set (match_dup 0)
11075 (call (mem:TLSmode (match_dup 3))
11076 (match_dup 4)))
11077 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11078 (clobber (reg:SI LR_REGNO))])]
11079 ""
10387 [(set_attr "type" "two") 11080 [(set_attr "type" "two")
10388 (set_attr "length" "12")]) 11081 (set_attr "length" "12")])
10389 11082
10390 (define_insn "tls_gd_sysv<TLSmode:tls_sysv_suffix>" 11083 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10391 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11084 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10392 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s")) 11085 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10393 (match_operand 4 "" "g"))) 11086 (match_operand 4 "" "g")))
10394 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11087 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10395 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11088 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10405 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt"; 11098 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10406 } 11099 }
10407 else 11100 else
10408 return "addi %0,%1,%2@got@tlsgd\;bl %z3"; 11101 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10409 } 11102 }
11103 "&& TARGET_TLS_MARKERS"
11104 [(set (match_dup 0)
11105 (unspec:TLSmode [(match_dup 1)
11106 (match_dup 2)]
11107 UNSPEC_TLSGD))
11108 (parallel [(set (match_dup 0)
11109 (call (mem:TLSmode (match_dup 3))
11110 (match_dup 4)))
11111 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11112 (clobber (reg:SI LR_REGNO))])]
11113 ""
10410 [(set_attr "type" "two") 11114 [(set_attr "type" "two")
10411 (set_attr "length" "8")]) 11115 (set_attr "length" "8")])
10412 11116
10413 (define_insn "tls_ld_aix<TLSmode:tls_abi_suffix>" 11117 (define_insn "*tls_gd<TLSmode:tls_abi_suffix>"
11118 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11119 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11120 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11121 UNSPEC_TLSGD))]
11122 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11123 "addi %0,%1,%2@got@tlsgd"
11124 [(set_attr "length" "4")])
11125
11126 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11127 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11128 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11129 (match_operand 2 "" "g")))
11130 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11131 UNSPEC_TLSGD)
11132 (clobber (reg:SI LR_REGNO))]
11133 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11134 "bl %z1(%3@tlsgd)\;%."
11135 [(set_attr "type" "branch")
11136 (set_attr "length" "8")])
11137
11138 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11139 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11140 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11141 (match_operand 2 "" "g")))
11142 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11143 UNSPEC_TLSGD)
11144 (clobber (reg:SI LR_REGNO))]
11145 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11146 {
11147 if (flag_pic)
11148 {
11149 if (TARGET_SECURE_PLT && flag_pic == 2)
11150 return "bl %z1+32768(%3@tlsgd)@plt";
11151 return "bl %z1(%3@tlsgd)@plt";
11152 }
11153 return "bl %z1(%3@tlsgd)";
11154 }
11155 [(set_attr "type" "branch")
11156 (set_attr "length" "4")])
11157
11158 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10414 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11159 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10415 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s")) 11160 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10416 (match_operand 3 "" "g"))) 11161 (match_operand 3 "" "g")))
10417 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")] 11162 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10418 UNSPEC_TLSLD) 11163 UNSPEC_TLSLD)
10419 (clobber (reg:SI LR_REGNO))] 11164 (clobber (reg:SI LR_REGNO))]
10420 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX" 11165 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10421 "addi %0,%1,%&@got@tlsld\;bl %z2\;%." 11166 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
11167 "&& TARGET_TLS_MARKERS"
11168 [(set (match_dup 0)
11169 (unspec:TLSmode [(match_dup 1)]
11170 UNSPEC_TLSLD))
11171 (parallel [(set (match_dup 0)
11172 (call (mem:TLSmode (match_dup 2))
11173 (match_dup 3)))
11174 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11175 (clobber (reg:SI LR_REGNO))])]
11176 ""
10422 [(set_attr "length" "12")]) 11177 [(set_attr "length" "12")])
10423 11178
10424 (define_insn "tls_ld_sysv<TLSmode:tls_sysv_suffix>" 11179 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10425 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11180 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10426 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s")) 11181 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10427 (match_operand 3 "" "g"))) 11182 (match_operand 3 "" "g")))
10428 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")] 11183 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10429 UNSPEC_TLSLD) 11184 UNSPEC_TLSLD)
10438 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt"; 11193 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10439 } 11194 }
10440 else 11195 else
10441 return "addi %0,%1,%&@got@tlsld\;bl %z2"; 11196 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10442 } 11197 }
11198 "&& TARGET_TLS_MARKERS"
11199 [(set (match_dup 0)
11200 (unspec:TLSmode [(match_dup 1)]
11201 UNSPEC_TLSLD))
11202 (parallel [(set (match_dup 0)
11203 (call (mem:TLSmode (match_dup 2))
11204 (match_dup 3)))
11205 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11206 (clobber (reg:SI LR_REGNO))])]
11207 ""
10443 [(set_attr "length" "8")]) 11208 [(set_attr "length" "8")])
11209
11210 (define_insn "*tls_ld<TLSmode:tls_abi_suffix>"
11211 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11212 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11213 UNSPEC_TLSLD))]
11214 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11215 "addi %0,%1,%&@got@tlsld"
11216 [(set_attr "length" "4")])
11217
11218 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11219 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11220 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11221 (match_operand 2 "" "g")))
11222 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11223 (clobber (reg:SI LR_REGNO))]
11224 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11225 "bl %z1(%&@tlsld)\;%."
11226 [(set_attr "type" "branch")
11227 (set_attr "length" "8")])
11228
11229 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11230 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11231 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11232 (match_operand 2 "" "g")))
11233 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11234 (clobber (reg:SI LR_REGNO))]
11235 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11236 {
11237 if (flag_pic)
11238 {
11239 if (TARGET_SECURE_PLT && flag_pic == 2)
11240 return "bl %z1+32768(%&@tlsld)@plt";
11241 return "bl %z1(%&@tlsld)@plt";
11242 }
11243 return "bl %z1(%&@tlsld)";
11244 }
11245 [(set_attr "type" "branch")
11246 (set_attr "length" "4")])
10444 11247
10445 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>" 11248 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10446 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") 11249 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10447 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11250 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10448 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11251 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11774 12577
11775 (define_insn "blockage" 12578 (define_insn "blockage"
11776 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] 12579 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11777 "" 12580 ""
11778 "") 12581 "")
12582
12583 (define_insn "probe_stack"
12584 [(set (match_operand 0 "memory_operand" "=m")
12585 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12586 ""
12587 "{st%U0%X0|stw%U0%X0} 0,%0"
12588 [(set_attr "type" "store")
12589 (set_attr "length" "4")])
11779 12590
11780 ;; Compare insns are next. Note that the RS/6000 has two types of compares, 12591 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11781 ;; signed & unsigned, and one type of branch. 12592 ;; signed & unsigned, and one type of branch.
11782 ;; 12593 ;;
11783 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc 12594 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11784 ;; insns, and branches. We store the operands of compares until we see 12595 ;; insns, and branches.
11785 ;; how it is used. 12596
11786 (define_expand "cmp<mode>" 12597 (define_expand "cbranch<mode>4"
11787 [(set (cc0) 12598 [(use (match_operator 0 "rs6000_cbranch_operator"
11788 (compare (match_operand:GPR 0 "gpc_reg_operand" "") 12599 [(match_operand:GPR 1 "gpc_reg_operand" "")
11789 (match_operand:GPR 1 "reg_or_short_operand" "")))] 12600 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12601 (use (match_operand 3 ""))]
11790 "" 12602 ""
11791 " 12603 "
11792 { 12604 {
11793 /* Take care of the possibility that operands[1] might be negative but 12605 /* Take care of the possibility that operands[2] might be negative but
11794 this might be a logical operation. That insn doesn't exist. */ 12606 this might be a logical operation. That insn doesn't exist. */
11795 if (GET_CODE (operands[1]) == CONST_INT 12607 if (GET_CODE (operands[2]) == CONST_INT
11796 && INTVAL (operands[1]) < 0) 12608 && INTVAL (operands[2]) < 0)
11797 operands[1] = force_reg (<MODE>mode, operands[1]); 12609 {
11798 12610 operands[2] = force_reg (<MODE>mode, operands[2]);
11799 rs6000_compare_op0 = operands[0]; 12611 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11800 rs6000_compare_op1 = operands[1]; 12612 GET_MODE (operands[0]),
11801 rs6000_compare_fp_p = 0; 12613 operands[1], operands[2]);
12614 }
12615
12616 rs6000_emit_cbranch (<MODE>mode, operands);
11802 DONE; 12617 DONE;
11803 }") 12618 }")
11804 12619
11805 (define_expand "cmp<mode>" 12620 (define_expand "cbranch<mode>4"
11806 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "") 12621 [(use (match_operator 0 "rs6000_cbranch_operator"
11807 (match_operand:FP 1 "gpc_reg_operand" "")))] 12622 [(match_operand:FP 1 "gpc_reg_operand" "")
12623 (match_operand:FP 2 "gpc_reg_operand" "")]))
12624 (use (match_operand 3 ""))]
11808 "" 12625 ""
11809 " 12626 "
11810 { 12627 {
11811 rs6000_compare_op0 = operands[0]; 12628 rs6000_emit_cbranch (<MODE>mode, operands);
11812 rs6000_compare_op1 = operands[1];
11813 rs6000_compare_fp_p = 1;
11814 DONE; 12629 DONE;
11815 }") 12630 }")
11816 12631
11817 (define_expand "beq" 12632 (define_expand "cstore<mode>4"
11818 [(use (match_operand 0 "" ""))] 12633 [(use (match_operator 1 "rs6000_cbranch_operator"
11819 "" 12634 [(match_operand:GPR 2 "gpc_reg_operand" "")
11820 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") 12635 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11821 12636 (clobber (match_operand:SI 0 "register_operand"))]
11822 (define_expand "bne"
11823 [(use (match_operand 0 "" ""))]
11824 ""
11825 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11826
11827 (define_expand "bge"
11828 [(use (match_operand 0 "" ""))]
11829 ""
11830 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11831
11832 (define_expand "bgt"
11833 [(use (match_operand 0 "" ""))]
11834 ""
11835 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11836
11837 (define_expand "ble"
11838 [(use (match_operand 0 "" ""))]
11839 ""
11840 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11841
11842 (define_expand "blt"
11843 [(use (match_operand 0 "" ""))]
11844 ""
11845 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11846
11847 (define_expand "bgeu"
11848 [(use (match_operand 0 "" ""))]
11849 ""
11850 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11851
11852 (define_expand "bgtu"
11853 [(use (match_operand 0 "" ""))]
11854 ""
11855 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11856
11857 (define_expand "bleu"
11858 [(use (match_operand 0 "" ""))]
11859 ""
11860 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11861
11862 (define_expand "bltu"
11863 [(use (match_operand 0 "" ""))]
11864 ""
11865 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11866
11867 (define_expand "bunordered"
11868 [(use (match_operand 0 "" ""))]
11869 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11870 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11871
11872 (define_expand "bordered"
11873 [(use (match_operand 0 "" ""))]
11874 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11875 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11876
11877 (define_expand "buneq"
11878 [(use (match_operand 0 "" ""))]
11879 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11880 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11881
11882 (define_expand "bunge"
11883 [(use (match_operand 0 "" ""))]
11884 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11885 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11886
11887 (define_expand "bungt"
11888 [(use (match_operand 0 "" ""))]
11889 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11890 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11891
11892 (define_expand "bunle"
11893 [(use (match_operand 0 "" ""))]
11894 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11895 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11896
11897 (define_expand "bunlt"
11898 [(use (match_operand 0 "" ""))]
11899 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11900 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11901
11902 (define_expand "bltgt"
11903 [(use (match_operand 0 "" ""))]
11904 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
11905 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11906
11907 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11908 ;; For SEQ, likewise, except that comparisons with zero should be done
11909 ;; with an scc insns. However, due to the order that combine see the
11910 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11911 ;; the cases we don't want to handle.
11912 (define_expand "seq"
11913 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11914 ""
11915 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11916
11917 (define_expand "sne"
11918 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11919 "" 12637 ""
11920 " 12638 "
11921 { 12639 {
11922 if (! rs6000_compare_fp_p) 12640 /* Take care of the possibility that operands[3] might be negative but
12641 this might be a logical operation. That insn doesn't exist. */
12642 if (GET_CODE (operands[3]) == CONST_INT
12643 && INTVAL (operands[3]) < 0)
12644 {
12645 operands[3] = force_reg (<MODE>mode, operands[3]);
12646 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12647 GET_MODE (operands[1]),
12648 operands[2], operands[3]);
12649 }
12650
12651 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12652 For SEQ, likewise, except that comparisons with zero should be done
12653 with an scc insns. However, due to the order that combine see the
12654 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12655 the cases we don't want to handle or are best handled by portable
12656 code. */
12657 if (GET_CODE (operands[1]) == NE)
11923 FAIL; 12658 FAIL;
11924 12659 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11925 rs6000_emit_sCOND (NE, operands[0]); 12660 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12661 && operands[3] == const0_rtx)
12662 FAIL;
12663 rs6000_emit_sCOND (<MODE>mode, operands);
11926 DONE; 12664 DONE;
11927 }") 12665 }")
11928 12666
11929 ;; A >= 0 is best done the portable way for A an integer. 12667 (define_expand "cstore<mode>4"
11930 (define_expand "sge" 12668 [(use (match_operator 1 "rs6000_cbranch_operator"
11931 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] 12669 [(match_operand:FP 2 "gpc_reg_operand" "")
12670 (match_operand:FP 3 "gpc_reg_operand" "")]))
12671 (clobber (match_operand:SI 0 "register_operand"))]
11932 "" 12672 ""
11933 " 12673 "
11934 { 12674 {
11935 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) 12675 rs6000_emit_sCOND (<MODE>mode, operands);
11936 FAIL;
11937
11938 rs6000_emit_sCOND (GE, operands[0]);
11939 DONE; 12676 DONE;
11940 }") 12677 }")
11941 12678
11942 ;; A > 0 is best done using the portable sequence, so fail in that case.
11943 (define_expand "sgt"
11944 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11945 ""
11946 "
11947 {
11948 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11949 FAIL;
11950
11951 rs6000_emit_sCOND (GT, operands[0]);
11952 DONE;
11953 }")
11954
11955 ;; A <= 0 is best done the portable way for A an integer.
11956 (define_expand "sle"
11957 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11958 ""
11959 "
11960 {
11961 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11962 FAIL;
11963
11964 rs6000_emit_sCOND (LE, operands[0]);
11965 DONE;
11966 }")
11967
11968 ;; A < 0 is best done in the portable way for A an integer.
11969 (define_expand "slt"
11970 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11971 ""
11972 "
11973 {
11974 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11975 FAIL;
11976
11977 rs6000_emit_sCOND (LT, operands[0]);
11978 DONE;
11979 }")
11980
11981 (define_expand "sgeu"
11982 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11983 ""
11984 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11985
11986 (define_expand "sgtu"
11987 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11988 ""
11989 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11990
11991 (define_expand "sleu"
11992 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11993 ""
11994 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11995
11996 (define_expand "sltu"
11997 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11998 ""
11999 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
12000
12001 (define_expand "sunordered"
12002 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12003 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12004 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
12005
12006 (define_expand "sordered"
12007 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12008 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12009 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
12010
12011 (define_expand "suneq"
12012 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12013 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12014 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
12015
12016 (define_expand "sunge"
12017 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12018 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12019 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
12020
12021 (define_expand "sungt"
12022 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12023 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12024 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
12025
12026 (define_expand "sunle"
12027 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12028 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12029 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
12030
12031 (define_expand "sunlt"
12032 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12033 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12034 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
12035
12036 (define_expand "sltgt"
12037 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
12038 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
12039 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
12040 12679
12041 (define_expand "stack_protect_set" 12680 (define_expand "stack_protect_set"
12042 [(match_operand 0 "memory_operand" "") 12681 [(match_operand 0 "memory_operand" "")
12043 (match_operand 1 "memory_operand" "")] 12682 (match_operand 1 "memory_operand" "")]
12044 "" 12683 ""
12077 [(match_operand 0 "memory_operand" "") 12716 [(match_operand 0 "memory_operand" "")
12078 (match_operand 1 "memory_operand" "") 12717 (match_operand 1 "memory_operand" "")
12079 (match_operand 2 "" "")] 12718 (match_operand 2 "" "")]
12080 "" 12719 ""
12081 { 12720 {
12721 rtx test, op0, op1;
12082 #ifdef TARGET_THREAD_SSP_OFFSET 12722 #ifdef TARGET_THREAD_SSP_OFFSET
12083 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2); 12723 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12084 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET)); 12724 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12085 operands[1] = gen_rtx_MEM (Pmode, addr); 12725 operands[1] = gen_rtx_MEM (Pmode, addr);
12086 #endif 12726 #endif
12087 rs6000_compare_op0 = operands[0]; 12727 op0 = operands[0];
12088 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), 12728 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12089 UNSPEC_SP_TEST); 12729 test = gen_rtx_EQ (VOIDmode, op0, op1);
12090 rs6000_compare_fp_p = 0; 12730 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12091 emit_jump_insn (gen_beq (operands[2]));
12092 DONE; 12731 DONE;
12093 }) 12732 })
12094 12733
12095 (define_insn "stack_protect_testsi" 12734 (define_insn "stack_protect_testsi"
12096 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y") 12735 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12240 "fcmpu %0,%1,%2" 12879 "fcmpu %0,%1,%2"
12241 [(set_attr "type" "fpcompare")]) 12880 [(set_attr "type" "fpcompare")])
12242 12881
12243 (define_insn "*cmpdf_internal1" 12882 (define_insn "*cmpdf_internal1"
12244 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 12883 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12245 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") 12884 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12246 (match_operand:DF 2 "gpc_reg_operand" "f")))] 12885 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12247 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 12886 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
12887 && !VECTOR_UNIT_VSX_P (DFmode)"
12248 "fcmpu %0,%1,%2" 12888 "fcmpu %0,%1,%2"
12249 [(set_attr "type" "fpcompare")]) 12889 [(set_attr "type" "fpcompare")])
12250 12890
12251 ;; Only need to compare second words if first words equal 12891 ;; Only need to compare second words if first words equal
12252 (define_insn "*cmptf_internal1" 12892 (define_insn "*cmptf_internal1"
12253 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 12893 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12254 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") 12894 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12255 (match_operand:TF 2 "gpc_reg_operand" "f")))] 12895 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12256 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT 12896 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12257 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" 12897 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12258 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" 12898 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12259 [(set_attr "type" "fpcompare") 12899 [(set_attr "type" "fpcompare")
12260 (set_attr "length" "12")]) 12900 (set_attr "length" "12")])
12261 12901
12262 (define_insn_and_split "*cmptf_internal2" 12902 (define_insn_and_split "*cmptf_internal2"
12263 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 12903 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12264 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") 12904 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12265 (match_operand:TF 2 "gpc_reg_operand" "f"))) 12905 (match_operand:TF 2 "gpc_reg_operand" "d")))
12266 (clobber (match_scratch:DF 3 "=f")) 12906 (clobber (match_scratch:DF 3 "=d"))
12267 (clobber (match_scratch:DF 4 "=f")) 12907 (clobber (match_scratch:DF 4 "=d"))
12268 (clobber (match_scratch:DF 5 "=f")) 12908 (clobber (match_scratch:DF 5 "=d"))
12269 (clobber (match_scratch:DF 6 "=f")) 12909 (clobber (match_scratch:DF 6 "=d"))
12270 (clobber (match_scratch:DF 7 "=f")) 12910 (clobber (match_scratch:DF 7 "=d"))
12271 (clobber (match_scratch:DF 8 "=f")) 12911 (clobber (match_scratch:DF 8 "=d"))
12272 (clobber (match_scratch:DF 9 "=f")) 12912 (clobber (match_scratch:DF 9 "=d"))
12273 (clobber (match_scratch:DF 10 "=f"))] 12913 (clobber (match_scratch:DF 10 "=d"))]
12274 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT 12914 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12275 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" 12915 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12276 "#" 12916 "#"
12277 "&& reload_completed" 12917 "&& reload_completed"
12278 [(set (match_dup 3) (match_dup 13)) 12918 [(set (match_dup 3) (match_dup 13))
14657 [(trap_if (const_int 1) (const_int 0))] 15297 [(trap_if (const_int 1) (const_int 0))]
14658 "" 15298 ""
14659 "{t 31,0,0|trap}" 15299 "{t 31,0,0|trap}"
14660 [(set_attr "type" "trap")]) 15300 [(set_attr "type" "trap")])
14661 15301
14662 (define_expand "conditional_trap" 15302 (define_expand "ctrap<mode>4"
14663 [(trap_if (match_operator 0 "trap_comparison_operator" 15303 [(trap_if (match_operator 0 "ordered_comparison_operator"
14664 [(match_dup 2) (match_dup 3)]) 15304 [(match_operand:GPR 1 "register_operand")
14665 (match_operand 1 "const_int_operand" ""))] 15305 (match_operand:GPR 2 "reg_or_short_operand")])
14666 "" 15306 (match_operand 3 "zero_constant" ""))]
14667 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; 15307 ""
14668 operands[2] = rs6000_compare_op0; 15308 "")
14669 operands[3] = rs6000_compare_op1;")
14670 15309
14671 (define_insn "" 15310 (define_insn ""
14672 [(trap_if (match_operator 0 "trap_comparison_operator" 15311 [(trap_if (match_operator 0 "ordered_comparison_operator"
14673 [(match_operand:GPR 1 "register_operand" "r") 15312 [(match_operand:GPR 1 "register_operand" "r")
14674 (match_operand:GPR 2 "reg_or_short_operand" "rI")]) 15313 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14675 (const_int 0))] 15314 (const_int 0))]
14676 "" 15315 ""
14677 "{t|t<wd>}%V0%I2 %1,%2" 15316 "{t|t<wd>}%V0%I2 %1,%2"
14734 (use (match_operand:P 1 "symbol_ref_operand" "s")) 15373 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14735 (use (match_operand:P 2 "gpc_reg_operand" "r")) 15374 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14736 (set (match_operand:P 3 "memory_operand" "=m") 15375 (set (match_operand:P 3 "memory_operand" "=m")
14737 (match_operand:P 4 "gpc_reg_operand" "r"))])] 15376 (match_operand:P 4 "gpc_reg_operand" "r"))])]
14738 "" 15377 ""
14739 "bl %z1" 15378 "bl %1"
14740 [(set_attr "type" "branch") 15379 [(set_attr "type" "branch")
14741 (set_attr "length" "4")]) 15380 (set_attr "length" "4")])
14742 15381
14743 (define_insn "*save_fpregs_<mode>" 15382 (define_insn "*save_fpregs_<mode>"
14744 [(match_parallel 0 "any_parallel_operand" 15383 [(match_parallel 0 "any_parallel_operand"
14745 [(clobber (reg:P 65)) 15384 [(clobber (reg:P 65))
14746 (use (match_operand:P 1 "symbol_ref_operand" "s")) 15385 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14747 (use (match_operand:P 2 "gpc_reg_operand" "r")) 15386 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14748 (set (match_operand:DF 3 "memory_operand" "=m") 15387 (set (match_operand:DF 3 "memory_operand" "=m")
14749 (match_operand:DF 4 "gpc_reg_operand" "f"))])] 15388 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
14750 "" 15389 ""
14751 "bl %z1" 15390 "bl %1"
14752 [(set_attr "type" "branch") 15391 [(set_attr "type" "branch")
14753 (set_attr "length" "4")]) 15392 (set_attr "length" "4")])
14754 15393
14755 ; These are to explain that changes to the stack pointer should 15394 ; These are to explain that changes to the stack pointer should
14756 ; not be moved over stores to stack memory. 15395 ; not be moved over stores to stack memory.
14841 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15480 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14842 (use (match_operand:P 3 "gpc_reg_operand" "r")) 15481 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14843 (set (match_operand:P 4 "gpc_reg_operand" "=r") 15482 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14844 (match_operand:P 5 "memory_operand" "m"))])] 15483 (match_operand:P 5 "memory_operand" "m"))])]
14845 "" 15484 ""
14846 "bl %z2" 15485 "bl %2"
14847 [(set_attr "type" "branch") 15486 [(set_attr "type" "branch")
14848 (set_attr "length" "4")]) 15487 (set_attr "length" "4")])
14849 15488
14850 (define_insn "*return_and_restore_gpregs_<mode>" 15489 (define_insn "*return_and_restore_gpregs_<mode>"
14851 [(match_parallel 0 "any_parallel_operand" 15490 [(match_parallel 0 "any_parallel_operand"
14854 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15493 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14855 (use (match_operand:P 3 "gpc_reg_operand" "r")) 15494 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14856 (set (match_operand:P 4 "gpc_reg_operand" "=r") 15495 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14857 (match_operand:P 5 "memory_operand" "m"))])] 15496 (match_operand:P 5 "memory_operand" "m"))])]
14858 "" 15497 ""
14859 "b %z2" 15498 "b %2"
14860 [(set_attr "type" "branch") 15499 [(set_attr "type" "branch")
14861 (set_attr "length" "4")]) 15500 (set_attr "length" "4")])
14862 15501
14863 (define_insn "*return_and_restore_fpregs_<mode>" 15502 (define_insn "*return_and_restore_fpregs_<mode>"
14864 [(match_parallel 0 "any_parallel_operand" 15503 [(match_parallel 0 "any_parallel_operand"
14865 [(return) 15504 [(return)
14866 (clobber (match_operand:P 1 "register_operand" "=l")) 15505 (clobber (match_operand:P 1 "register_operand" "=l"))
14867 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15506 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14868 (use (match_operand:P 3 "gpc_reg_operand" "r")) 15507 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14869 (set (match_operand:DF 4 "gpc_reg_operand" "=f") 15508 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
14870 (match_operand:DF 5 "memory_operand" "m"))])] 15509 (match_operand:DF 5 "memory_operand" "m"))])]
14871 "" 15510 ""
14872 "b %z2" 15511 "b %2"
15512 [(set_attr "type" "branch")
15513 (set_attr "length" "4")])
15514
15515 (define_insn "*return_and_restore_fpregs_aix_<mode>"
15516 [(match_parallel 0 "any_parallel_operand"
15517 [(return)
15518 (use (match_operand:P 1 "register_operand" "l"))
15519 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15520 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15521 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15522 (match_operand:DF 5 "memory_operand" "m"))])]
15523 ""
15524 "b %2"
14873 [(set_attr "type" "branch") 15525 [(set_attr "type" "branch")
14874 (set_attr "length" "4")]) 15526 (set_attr "length" "4")])
14875 15527
14876 ; This is used in compiling the unwind routines. 15528 ; This is used in compiling the unwind routines.
14877 (define_expand "eh_return" 15529 (define_expand "eh_return"
14916 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; 15568 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14917 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; 15569 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14918 }" 15570 }"
14919 [(set_attr "type" "load")]) 15571 [(set_attr "type" "load")])
14920 15572
15573 (define_insn "bpermd_<mode>"
15574 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15575 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15576 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15577 "TARGET_POPCNTD"
15578 "bpermd %0,%1,%2"
15579 [(set_attr "type" "integer")])
15580
15581
14921 15582
14922 (include "sync.md") 15583 (include "sync.md")
15584 (include "vector.md")
15585 (include "vsx.md")
14923 (include "altivec.md") 15586 (include "altivec.md")
14924 (include "spe.md") 15587 (include "spe.md")
14925 (include "dfp.md") 15588 (include "dfp.md")
14926 (include "paired.md") 15589 (include "paired.md")