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comparison gcc/config/i386/sse.md @ 47:3bfb6c00c1e0

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update it from 4.4.2 to 4.4.3.
author kent <kent@cr.ie.u-ryukyu.ac.jp>
date Sun, 07 Feb 2010 17:44:34 +0900
parents 855418dad1a3
children 77e2b8dfacca
comparison
equal deleted inserted replaced
46:b85a337e5837 47:3bfb6c00c1e0
2305 [(vec_select:SF 2305 [(vec_select:SF
2306 (match_operand:V4SF 1 "nonimmediate_operand" "x,m") 2306 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
2307 (parallel [(const_int 0)]))] 2307 (parallel [(const_int 0)]))]
2308 UNSPEC_FIX_NOTRUNC))] 2308 UNSPEC_FIX_NOTRUNC))]
2309 "TARGET_SSE && TARGET_64BIT" 2309 "TARGET_SSE && TARGET_64BIT"
2310 "%vcvtss2siq\t{%1, %0|%0, %1}" 2310 "%vcvtss2si{q}\t{%1, %0|%0, %1}"
2311 [(set_attr "type" "sseicvt") 2311 [(set_attr "type" "sseicvt")
2312 (set_attr "athlon_decode" "double,vector") 2312 (set_attr "athlon_decode" "double,vector")
2313 (set_attr "prefix_rep" "1") 2313 (set_attr "prefix_rep" "1")
2314 (set_attr "prefix" "maybe_vex") 2314 (set_attr "prefix" "maybe_vex")
2315 (set_attr "mode" "DI")]) 2315 (set_attr "mode" "DI")])
2317 (define_insn "sse_cvtss2siq_2" 2317 (define_insn "sse_cvtss2siq_2"
2318 [(set (match_operand:DI 0 "register_operand" "=r,r") 2318 [(set (match_operand:DI 0 "register_operand" "=r,r")
2319 (unspec:DI [(match_operand:SF 1 "nonimmediate_operand" "x,m")] 2319 (unspec:DI [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
2320 UNSPEC_FIX_NOTRUNC))] 2320 UNSPEC_FIX_NOTRUNC))]
2321 "TARGET_SSE && TARGET_64BIT" 2321 "TARGET_SSE && TARGET_64BIT"
2322 "%vcvtss2siq\t{%1, %0|%0, %1}" 2322 "%vcvtss2si{q}\t{%1, %0|%0, %1}"
2323 [(set_attr "type" "sseicvt") 2323 [(set_attr "type" "sseicvt")
2324 (set_attr "athlon_decode" "double,vector") 2324 (set_attr "athlon_decode" "double,vector")
2325 (set_attr "amdfam10_decode" "double,double") 2325 (set_attr "amdfam10_decode" "double,double")
2326 (set_attr "prefix_rep" "1") 2326 (set_attr "prefix_rep" "1")
2327 (set_attr "prefix" "maybe_vex") 2327 (set_attr "prefix" "maybe_vex")
2347 (fix:DI 2347 (fix:DI
2348 (vec_select:SF 2348 (vec_select:SF
2349 (match_operand:V4SF 1 "nonimmediate_operand" "x,m") 2349 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
2350 (parallel [(const_int 0)]))))] 2350 (parallel [(const_int 0)]))))]
2351 "TARGET_SSE && TARGET_64BIT" 2351 "TARGET_SSE && TARGET_64BIT"
2352 "%vcvttss2siq\t{%1, %0|%0, %1}" 2352 "%vcvttss2si{q}\t{%1, %0|%0, %1}"
2353 [(set_attr "type" "sseicvt") 2353 [(set_attr "type" "sseicvt")
2354 (set_attr "athlon_decode" "double,vector") 2354 (set_attr "athlon_decode" "double,vector")
2355 (set_attr "amdfam10_decode" "double,double") 2355 (set_attr "amdfam10_decode" "double,double")
2356 (set_attr "prefix_rep" "1") 2356 (set_attr "prefix_rep" "1")
2357 (set_attr "prefix" "maybe_vex") 2357 (set_attr "prefix" "maybe_vex")
6588 (match_operand:SSEMODE124 1 "register_operand" "x") 6588 (match_operand:SSEMODE124 1 "register_operand" "x")
6589 (match_operand:SI 3 "const_pow2_1_to_<pinsrbits>_operand" "n")))] 6589 (match_operand:SI 3 "const_pow2_1_to_<pinsrbits>_operand" "n")))]
6590 "TARGET_AVX" 6590 "TARGET_AVX"
6591 { 6591 {
6592 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); 6592 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6593 return "vpinsr<avxmodesuffixs>\t{%3, %k2, %1, %0|%0, %1, %k2, %3}"; 6593 if (MEM_P (operands[2]))
6594 return "vpinsr<avxmodesuffixs>\t{%3, %2, %1, %0|%0, %1, %2, %3}";
6595 else
6596 return "vpinsr<avxmodesuffixs>\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
6594 } 6597 }
6595 [(set_attr "type" "sselog") 6598 [(set_attr "type" "sselog")
6596 (set_attr "prefix" "vex") 6599 (set_attr "prefix" "vex")
6597 (set_attr "mode" "TI")]) 6600 (set_attr "mode" "TI")])
6598 6601
6604 (match_operand:V16QI 1 "register_operand" "0") 6607 (match_operand:V16QI 1 "register_operand" "0")
6605 (match_operand:SI 3 "const_pow2_1_to_32768_operand" "n")))] 6608 (match_operand:SI 3 "const_pow2_1_to_32768_operand" "n")))]
6606 "TARGET_SSE4_1" 6609 "TARGET_SSE4_1"
6607 { 6610 {
6608 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); 6611 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6609 return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}"; 6612 if (MEM_P (operands[2]))
6613 return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
6614 else
6615 return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
6610 } 6616 }
6611 [(set_attr "type" "sselog") 6617 [(set_attr "type" "sselog")
6612 (set_attr "prefix_extra" "1") 6618 (set_attr "prefix_extra" "1")
6613 (set_attr "mode" "TI")]) 6619 (set_attr "mode" "TI")])
6614 6620
6620 (match_operand:V8HI 1 "register_operand" "0") 6626 (match_operand:V8HI 1 "register_operand" "0")
6621 (match_operand:SI 3 "const_pow2_1_to_128_operand" "n")))] 6627 (match_operand:SI 3 "const_pow2_1_to_128_operand" "n")))]
6622 "TARGET_SSE2" 6628 "TARGET_SSE2"
6623 { 6629 {
6624 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); 6630 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6625 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}"; 6631 if (MEM_P (operands[2]))
6632 return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
6633 else
6634 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
6626 } 6635 }
6627 [(set_attr "type" "sselog") 6636 [(set_attr "type" "sselog")
6628 (set_attr "prefix_data16" "1") 6637 (set_attr "prefix_data16" "1")
6629 (set_attr "mode" "TI")]) 6638 (set_attr "mode" "TI")])
6630 6639